diff --git a/Makefile b/Makefile
index cc68d63..ed5046e 100644
--- a/Makefile
+++ b/Makefile
@@ -16,7 +16,7 @@
 
 FILE_SIZE_LIMIT_MB = 10
 LARGE_FILES := $(shell find . -type f -size +$(FILE_SIZE_LIMIT_MB)M -not -path "./.git/*")
-=======
+
 # cannot commit files larger than 100 MB to GitHub 
 FILE_SIZE_LIMIT_MB = 100
 LARGE_FILES := $(shell find ./gds -type f -name "*.gds")
@@ -57,19 +57,23 @@
 verify:
 	echo "verify"
 
-.PHONY: copy_config_block
-copy_config_block:
+.PHONY: copy_block
+copy_block:
 	@echo
-	@echo "       overwritting config.tcl in user_proj_example"
+	@echo "       overwritting user_proj_example with 16x16 block"
 	@echo
-	cp verilog/morphle/config_block.tcl openlane/user_proj_example/config.tcl
+	cp ol_templates/config_block.tcl openlane/user_proj_example/config.tcl
+	cp ol_templates/pdn.tcl openlane/user_proj_example/pdn.tcl
+	cp ol_templates/pin_order.cfg openlane/user_proj_example/pin_order.cfg
 
-.PHONY: copy_config_block2
-copy_config_block2:
+.PHONY: copy_block2
+copy_block2:
 	@echo
-	@echo "       overwritting config.tcl in user_proj_example"
+	@echo "       overwritting user_proj_example with black box 16x16 block"
 	@echo
-	cp verilog/morphle/config_block2.tcl openlane/user_proj_example/config.tcl
+	cp ol_templates/config_block2.tcl openlane/user_proj_example/config.tcl
+	cp ol_templates/pdn.tcl openlane/user_proj_example/pdn.tcl
+	cp ol_templates/pin_order.cfg openlane/user_proj_example/pin_order.cfg
 
 .PHONY: help
 help:
diff --git a/ol_templates/README.md b/ol_templates/README.md
new file mode 100644
index 0000000..f6626d7
--- /dev/null
+++ b/ol_templates/README.md
@@ -0,0 +1,30 @@
+<!---
+< SPDX-FileCopyrightText: Copyright 2020 Jecel Mattos de Assumpcao Jr
+< 
+< SPDX-License-Identifier: Apache-2.0 
+< 
+< Licensed under the Apache License, Version 2.0 (the "License");
+< you may not use this file except in compliance with the License.
+< You may obtain a copy of the License at
+< 
+<     https://www.apache.org/licenses/LICENSE-2.0
+< 
+< Unless required by applicable law or agreed to in writing, software
+< distributed under the License is distributed on an "AS IS" BASIS,
+< WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+< See the License for the specific language governing permissions and
+< limitations under the License.
+--->
+# Templates for OpenLane configuration files
+
+Several files are used for each possible project to be included in the Caravel chip. One is a Verilog file that is used to generate *user_proj_example.gds* (the name must be this as it is what *user_project_wrapper* expects) and another is a Tcl configuration file that must be copied to *../../openlane/user_proj_example/config.tcl* so openlane can do its job.
+
+Other files are *pdn.tcl* and *pin_order.cfg*.
+
+### user_proj_block
+
+*<project root>/verilog/morphle/user_proj_block.v* is invoked from *config_block.tcl* (which gets renamed when copied to *<project root>/openlane/user_proj_example/*) and connects a single 16x16 yblock cells to the Caravel logic analyzer pins. It also attaches a dummy circuit to the Wishbone interface, but leaves all io pins dangling (so ignore warnings about that).
+
+### user_proj_block2
+
+*<project root>/verilog/morphle/user_proj_block.v* is invoked from *config_block2.tcl* (which gets renamed when copied to *<project root>/openlane/user_proj_example/*) and connects a single 16x16 yblock cells to the Caravel logic analyzer pins. It also attaches a dummy circuit to the Wishbone interface, but leaves all io pins dangling (so ignore warnings about that). In this version the ycell has been hardned and the yblock is build from that.
diff --git a/verilog/morphle/config_block.tcl b/ol_templates/config_block.tcl
similarity index 100%
rename from verilog/morphle/config_block.tcl
rename to ol_templates/config_block.tcl
diff --git a/verilog/morphle/config_block2.tcl b/ol_templates/config_block2.tcl
similarity index 100%
rename from verilog/morphle/config_block2.tcl
rename to ol_templates/config_block2.tcl
diff --git a/ol_templates/pdn.tcl b/ol_templates/pdn.tcl
new file mode 100644
index 0000000..f6d953c
--- /dev/null
+++ b/ol_templates/pdn.tcl
@@ -0,0 +1,47 @@
+# Power nets
+set ::power_nets $::env(_VDD_NET_NAME)
+set ::ground_nets $::env(_GND_NET_NAME)
+
+pdngen::specify_grid stdcell {
+    name grid
+	core_ring {
+		met5 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_H_OFFSET)}
+		met4 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_V_OFFSET)}
+	}
+	rails {
+	}
+    straps {
+	    met4 {width $::env(_WIDTH) pitch $::env(_V_PITCH) offset $::env(_V_PDN_OFFSET)}
+	    met5 {width $::env(_WIDTH) pitch $::env(_H_PITCH) offset $::env(_H_PDN_OFFSET)}
+    }
+    connect {{met4 met5}}
+}
+
+pdngen::specify_grid macro {
+	instance "obs_core_obs"
+    power_pins $::env(_VDD_NET_NAME)
+    ground_pins $::env(_GND_NET_NAME)
+    blockages "li1 met1 met2 met3 met4 met5"
+    straps { 
+    } 
+    connect {}
+}
+
+
+pdngen::specify_grid macro {
+    power_pins $::env(_VDD_NET_NAME)
+    ground_pins $::env(_GND_NET_NAME)
+    blockages ""
+    straps { 
+    } 
+    connect {}
+}
+
+set ::halo 0
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
+
diff --git a/ol_templates/pin_order.cfg b/ol_templates/pin_order.cfg
new file mode 100644
index 0000000..8128f78
--- /dev/null
+++ b/ol_templates/pin_order.cfg
@@ -0,0 +1,9 @@
+#BUS_SORT
+
+#S
+wb_.*
+wbs_.*
+la_.*
+
+#N
+io_.*
diff --git a/verilog/morphle/README.md b/verilog/morphle/README.md
index b0e3e3f..d092242 100644
--- a/verilog/morphle/README.md
+++ b/verilog/morphle/README.md
@@ -15,52 +15,17 @@
 < See the License for the specific language governing permissions and
 < limitations under the License.
 --->
-# Verilog files specific to Morphle Logic
+## Verilog Library of building blocks for Morphle Logic
 
-Pairs of files are used for each possible project to be included in the Caravel chip. One is a Verilog file that is used to generate *user_proj_example.gds* (the name must be this as it is what *user_project_wrapper* expects) and the other is a Tcl configuration file that must be copied to *../../openlane/user_proj_example/config.tcl* so openlane can do its job.
+### ycell.v
 
-- *user_proj_block.v* and *user_proj_block.v* connect a single 16x16 yblock cell to the Caravel logic analyzer pins. It also attaches a dummy circuit to the Wishbone interface, but leaves all io pins dangling (so ignore warnings about that).
+The basic element is *ycell* ("yellow cell", named so because of the first illustrations). This file also defines a trivial configuration circuit that shifts in 3 configuration bits and decodes the 8 possible combinations into the needed control signals.
 
-## library
+### yblock.v
 
-The main library contains the building blocks for Morphle Logic:
+*yblock* just being an array of ycells of the specified BLOCKWIDTH and BLOCKHEIGHT. Besides connecting the ycells to each other, yblock connects the wires at the edges of the array to ports so it can be used as a component in a larger system.
 
-- *ycell.v*: the basic element is *ycell* ("yellow cell", named so because of the first illustrations)
-- *yblock.v*: *yblock* just being an array of ycells of the specified BLOCKWIDTH and BLOCKHEIGHT. Besides connecting the ycells to each other, yblock connects the wires at the edges of the array to ports so it can be used as a component in a larger system.
+## Caravel User Project Examples
 
-## Tests
+## user_proj_block.v
 
-The circuits of this kind are simulation-only can test the components in the library
-
-The way to execute them is
-
-    iverilog testNNNdescription.v
-    vvp a.out
-
-Normally some output is printed or a .vcd file is generated which can then be examined with gtkwave.
-
-### test001ycfsm.v
-
-This puts the asynchronous finite state machine inside the basic Morphle Logic cell through its paces and prints out values from the tester and several internal signals of the fsm module. The use of internal signals helped debug the initial design, but might break this test if that design is changed in the future.
-
-Many signals are two bit busses and can have the values 0 (indicating "empty"), 1 (indicating a logical 0) or 2 (indicating a logica 1). Some internal signals can be temporarily 3 but that normally shouldn't appear.
-
-### test002ycfsm.v
-
-This is the finite state machine being tested by this and the previous test. The expected output value is indicated by the color inside each circle representing the states. The input values are indicated by the color of the arrows, which can be hard to see due to the red stripes.
-
-![Finite State Machine for basic Morphle Logic cell](ycfsmnum.png)
-
-A separate file, "test002.tv", has the actual test vectors with one 7 bit vector per line. The reset signal is a single bit but all others are pairs with 00 indicating "empty", 01 indicating a logical 0 and 10 a logical 1. The last two bits are the expected value for the output and an error is printed if that is not what comes out of the actual circuit.
-
-Since no internal signals are used, this test should work even if the circuit is changed as long as it still implements the fsm indicated above. In order to check that all transitions (arrows) are tested they were numbered and the test vector file has comments indicating where each transitions is tested for the first time. In order to get to a transition that hasn't yet been tested it is often necessary to go through many that have already been seen. That is the big problem with black box testing and why it is a good idea to include BIST (built-in self test circuits) in a design.
-
-### test003ycconfig.v
-
-This tests the configuration circuit by manually shifting in 3 bits at a time and listing the outputs. It adds a comment about which state the configuration is in after the 3 bits.
-
-A second configuration circuit is cascaded with the first in this test. Every time the first circuit has a valid configuration, the second one should have the previous valid configuration of the first circuit.
-
-### test004ycell.v
-
-A separate file, "test004.tv", has the actual test vectors as a 28 bit vector per line in the form of a 7 digit hex number. The first two bits are ignored and the rest are used as inputs to the "yellow cell" (the basic building block of Morphle Logic) or as values to be compared against the actual outputs.
diff --git a/verilog/mtests/README.md b/verilog/mtests/README.md
new file mode 100644
index 0000000..df0c667
--- /dev/null
+++ b/verilog/mtests/README.md
@@ -0,0 +1,57 @@
+<!---
+< SPDX-FileCopyrightText: Copyright 2020 Jecel Mattos de Assumpcao Jr
+< 
+< SPDX-License-Identifier: Apache-2.0 
+< 
+< Licensed under the Apache License, Version 2.0 (the "License");
+< you may not use this file except in compliance with the License.
+< You may obtain a copy of the License at
+< 
+<     https://www.apache.org/licenses/LICENSE-2.0
+< 
+< Unless required by applicable law or agreed to in writing, software
+< distributed under the License is distributed on an "AS IS" BASIS,
+< WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+< See the License for the specific language governing permissions and
+< limitations under the License.
+--->
+##  Tests
+
+The circuits of this kind are simulation-only can test the components in the library
+
+The way to execute them is
+
+    iverilog testNNNdescription.v
+    vvp a.out
+
+Normally some output is printed or a .vcd file is generated which can then be examined with gtkwave.
+
+### test001ycfsm.v
+
+This puts the asynchronous finite state machine inside the basic Morphle Logic cell through its paces and prints out values from the tester and several internal signals of the fsm module. The use of internal signals helped debug the initial design, but might break this test if that design is changed in the future.
+
+Many signals are two bit busses and can have the values 0 (indicating "empty"), 1 (indicating a logical 0) or 2 (indicating a logica 1). Some internal signals can be temporarily 3 but that normally shouldn't appear.
+
+### test002ycfsm.v
+
+This is the finite state machine being tested by this and the previous test. The expected output value is indicated by the color inside each circle representing the states. The input values are indicated by the color of the arrows, which can be hard to see due to the red stripes.
+
+![Finite State Machine for basic Morphle Logic cell](ycfsmnum.png)
+
+A separate file, "test002.tv", has the actual test vectors with one 7 bit vector per line. The reset signal is a single bit but all others are pairs with 00 indicating "empty", 01 indicating a logical 0 and 10 a logical 1. The last two bits are the expected value for the output and an error is printed if that is not what comes out of the actual circuit.
+
+Since no internal signals are used, this test should work even if the circuit is changed as long as it still implements the fsm indicated above. In order to check that all transitions (arrows) are tested they were numbered and the test vector file has comments indicating where each transitions is tested for the first time. In order to get to a transition that hasn't yet been tested it is often necessary to go through many that have already been seen. That is the big problem with black box testing and why it is a good idea to include BIST (built-in self test circuits) in a design.
+
+### test003ycconfig.v
+
+This tests the configuration circuit by manually shifting in 3 bits at a time and listing the outputs. It adds a comment about which state the configuration is in after the 3 bits.
+
+A second configuration circuit is cascaded with the first in this test. Every time the first circuit has a valid configuration, the second one should have the previous valid configuration of the first circuit.
+
+### test004ycell.v
+
+A separate file, "test004.tv", has the actual test vectors as a 28 bit vector per line in the form of a 7 digit hex number. The first two bits are ignored and the rest are used as inputs to the "yellow cell" (the basic building block of Morphle Logic) or as values to be compared against the actual outputs.
+
+### test004upblock.v
+
+A separate test file, "test005.tv", has the actual test vectors as a 100 bit vector per line in the form of a 25 digit hex number. The first two bits are use to disable comparisons with the outputs of the configuration bits and data lines respectively. These outputs have an initial value of "x" (unknown) for some three cycles in the case of data lines and until 48 bits have been shifted in for the configuration bits. The next 50 bits are what the Caravel is supposed to send to the user project via the logic analyzer pins and the last 48 bits are what should be returned by the user project.
\ No newline at end of file
diff --git a/verilog/morphle/test001ycfsm.v b/verilog/mtests/test001ycfsm.v
similarity index 97%
rename from verilog/morphle/test001ycfsm.v
rename to verilog/mtests/test001ycfsm.v
index db4e19a..c689dba 100644
--- a/verilog/morphle/test001ycfsm.v
+++ b/verilog/mtests/test001ycfsm.v
@@ -20,7 +20,7 @@
 // experiement in generating a waveform file
 
 `timescale 1ns/1ps
-`include "ycell.v"
+`include "../morphle/ycell.v"
 
 module test001fsm;
 
diff --git a/verilog/morphle/test002.tv b/verilog/mtests/test002.tv
similarity index 100%
rename from verilog/morphle/test002.tv
rename to verilog/mtests/test002.tv
diff --git a/verilog/morphle/test002ycfsm.v b/verilog/mtests/test002ycfsm.v
similarity index 98%
rename from verilog/morphle/test002ycfsm.v
rename to verilog/mtests/test002ycfsm.v
index 34cc06b..ebd2501 100644
--- a/verilog/morphle/test002ycfsm.v
+++ b/verilog/mtests/test002ycfsm.v
@@ -25,7 +25,7 @@
 // https://syssec.ethz.ch/content/dam/ethz/special-interest/infk/inst-infsec/system-security-group-dam/education/Digitaltechnik_14/14_Verilog_Testbenches.pdf
 
 `timescale 1ns/1ps
-`include "ycell.v"
+`include "../morphle/ycell.v"
 
 module test002fsm;
 
diff --git a/verilog/morphle/test003ycconfig.v b/verilog/mtests/test003ycconfig.v
similarity index 98%
rename from verilog/morphle/test003ycconfig.v
rename to verilog/mtests/test003ycconfig.v
index 0838060..8ab9365 100644
--- a/verilog/morphle/test003ycconfig.v
+++ b/verilog/mtests/test003ycconfig.v
@@ -19,7 +19,7 @@
 // checked for the desired value
 
 `timescale 1ns/1ps
-`include "ycell.v"
+`include "../morphle/ycell.v"
 
 module test003config;
 
diff --git a/verilog/morphle/test004.tv b/verilog/mtests/test004.tv
similarity index 100%
rename from verilog/morphle/test004.tv
rename to verilog/mtests/test004.tv
diff --git a/verilog/morphle/test004ycell.v b/verilog/mtests/test004ycell.v
similarity index 98%
rename from verilog/morphle/test004ycell.v
rename to verilog/mtests/test004ycell.v
index 85419b3..f1674dc 100644
--- a/verilog/morphle/test004ycell.v
+++ b/verilog/mtests/test004ycell.v
@@ -25,7 +25,7 @@
 // https://syssec.ethz.ch/content/dam/ethz/special-interest/infk/inst-infsec/system-security-group-dam/education/Digitaltechnik_14/14_Verilog_Testbenches.pdf
 
 `timescale 1ns/1ps
-`include "ycell.v"
+`include "../morphle/ycell.v"
 
 module test004ycell;
 
diff --git a/verilog/morphle/test005.tv b/verilog/mtests/test005.tv
similarity index 100%
rename from verilog/morphle/test005.tv
rename to verilog/mtests/test005.tv
diff --git a/verilog/morphle/test005upblock.v b/verilog/mtests/test005upblock.v
similarity index 97%
rename from verilog/morphle/test005upblock.v
rename to verilog/mtests/test005upblock.v
index 62265a2..4b1e16f 100644
--- a/verilog/morphle/test005upblock.v
+++ b/verilog/mtests/test005upblock.v
@@ -27,9 +27,9 @@
 
 `timescale 1ns/1ps
 `include "../rtl/defines.v"
-`include "ycell.v"
-`include "yblock.v"
-`include "user_proj_block.v"
+`include "../morphle/ycell.v"
+`include "../morphle/yblock.v"
+`include "../morphle/user_proj_block.v"
 
 module test005upblock;
 
diff --git a/verilog/morphle/ycfsmnum.png b/verilog/mtests/ycfsmnum.png
similarity index 100%
rename from verilog/morphle/ycfsmnum.png
rename to verilog/mtests/ycfsmnum.png
Binary files differ