)]}'
{
  "commit": "514dfd83c9d8143c6fb3a0cddff9b9abee15d09e",
  "tree": "a4246798bd52b47a03bcaeaa0836fcb6d81d9f8a",
  "parents": [
    "66322fde7057afb93f91b7d1f0720d72c431761e"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sat Oct 10 21:36:49 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sat Oct 10 21:36:49 2020 -0400"
  },
  "message": "Finalized the voltage clamp arrangement and the total number of pads.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ebe02345b378f50abbda6290677e1e4f1461a4e9",
      "old_mode": 33188,
      "old_path": "verilog/rtl/chip_io.v",
      "new_id": "5238bef37a24204b6c60a98ce36e7218bd1aac3d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/chip_io.v"
    },
    {
      "type": "modify",
      "old_id": "b17bf1d18031a0a8744ee7d0f254eecc89c6ac1b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/pads.v",
      "new_id": "1c3a4bf01b4d1a1cee2cb327af1f4bfb48fc7957",
      "new_mode": 33188,
      "new_path": "verilog/rtl/pads.v"
    }
  ]
}