// SPDX-FileCopyrightText: Copyright 2020 Jecel Mattos de Assumpcao Jr
// 
// SPDX-License-Identifier: Apache-2.0 
// 
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// 
//     https://www.apache.org/licenses/LICENSE-2.0
// 
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

// test vectors for user_proj_block 16x16 ycell block connected to
// the rest of the Caravel chip using the logic analyzer pins.
// The verilog test bench that reads this file is test005upblock.v
//
// each vector in the the format of 1+4+8+4+8 = 25 hex digits
//
// The first three groups are the values to be sent from Caravel's
// logic analyzer to the block while the last two groups are the
// results that the block is expected to send to the logic analyzer.
//
// The first digit only controls two bits, so only 0 to 3 are valid
// values. Bit 0 is the configuration clock and bit 1 is reset. The
// top two bits of the digit disable comparisons with the fourth
// and fifth group respectively, which has to be done for the first
// few vectors while the circuit under test is outputting unknowns
//
// The second group is the configuration bits for the 16 columns of
// ycells
//
// The third group is the uin data to be injected into the 16 columns
// with two bits each. The two bits can be 0 (empty), 1 (value 0) or
// 2 (value 1). While 3 is not supposed to be used, it might be a good
// idea to see what happens
//
// The fourth group is the expected value from the configuration bits
// coming out of the bottom of the 16 columns. They should be the same
// value as 3*BLOCKHEIGHT (48 in the default case of 16 rows) bits ago
// for the configuration in
//
// The fifth (and last) group is the expected value from uout coming
// from the 16 columns with two bits each
//
// example configuration:
// .101Y||.........
// .0+0-YN.........
// .+10-Y..........
// ................
// ................
// ................
// ................
// ................
// ................
// ................
// ................
// ................
// ................
// ................
// ................
// ................
//
// breaking it into bits:  .  +  -  |  1  0  Y  N
//                   msb   0  0  0  0  1  1  1  1
//                         0  0  1  1  0  0  1  1
//                   lsb   0  1  0  1  0  1  0  1

8_0000_00000000_0000_00000000  // ignore outputs until first configuration is in
A_0000_00000000_0000_00000000  // reset everything
A_0000_00000000_0000_00000000  // msb bit 15: ................
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // middle bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // lsb bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // msb bit 14: ................
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // middle bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // lsb bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // msb bit 13: ................
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // middle bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // lsb bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // msb bit 12: ................
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // middle bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // lsb bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // msb bit 11: ................
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // middle bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // lsb bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // msb bit 10: ................
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // middle bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // lsb bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // msb bit 09: ................
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // middle bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // lsb bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // msb bit 08: ................
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // middle bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // lsb bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // msb bit 07: ................
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // middle bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // lsb bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // msb bit 06: ................
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // middle bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // lsb bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // msb bit 05: ................
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // middle bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // lsb bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // msb bit 04: ................
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // middle bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // lsb bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // msb bit 03: ................
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // middle bit
B_0000_00000000_0000_00000000
A_0000_00000000_0000_00000000  // lsb bit
B_0000_00000000_0000_00000000
A_3400_00000000_0000_00000000  // msb bit 02: .+10 -Y.. .... ....
B_3400_00000000_0000_00000000  //             0011 0100 0000 0000
A_0C00_00000000_0000_00000000  // middle bit  0000 1100 0000 0000
B_0C00_00000000_0000_00000000  //             0101 0000 0000 0000
A_5000_00000000_0000_00000000  // lsb bit
B_5000_00000000_0000_00000000
A_5600_00000000_0000_00000000  // msb bit 01: .0+0 -YN. .... ....
B_5600_00000000_0000_00000000  //             0101 0110 0000 0000
A_0E00_00000000_0000_00000000  // middle bit  0000 1110 0000 0000
B_0E00_00000000_0000_00000000  //             0111 0010 0000 0000
A_7200_00000000_0000_00000000  // lsb bit
B_7200_00000000_0000_00000000
A_7800_00000000_0000_00000000  // msb bit 00: .101 Y||. .... ....
B_7800_00000000_0000_00000000  //             0111 1000 0000 0000
A_0E00_00000000_0000_00000000  // middle bit  0000 1110 0000 0000
B_0E00_00000000_0000_00000000  //             0010 0110 0000 0000
A_2600_00000000_0000_00000000  // lsb bit
B_2600_00000000_0000_00000000
0_0000_00000000_0000_00000000  // normal operation!
0_0000_15A80000_0000_15540000  // inject E0 00 11 1E EE EE EE EE
0_0000_00000000_0000_00000000  // normal operation
0_0000_00A80000_0000_00000000  // clear outputs
0_0000_16A80000_0000_16580000  // inject E0 01 11 1E EE EE EE EE
0_0000_00000000_0000_00000000  // normal operation
0_0000_00A80000_0000_00000000  // clear outputs
0_0000_19A80000_0000_19640000  // inject E0 10 11 1E EE EE EE EE
0_0000_00000000_0000_00000000  // normal operation
0_0000_29000000_0000_29000000  // inject E1 10 11 1E EE EE EE EE
0_0000_29000000_0000_29000000  // inject E1 10 11 1E EE EE EE EE
0_0000_00000000_0000_00000000  // normal operation
0_0000_00A80000_0000_00580000  // get pending outputs
0_0000_00A80000_0000_00580000  // get pending outputs
0_0000_00000000_0000_00000000  // everyone is empty again
0_0000_02080000_0000_02000000  // inject EE E1 EE 1E EE EE EE EE
0_0000_02080000_0000_02000000  // inject EE E1 EE 1E EE EE EE EE
0_0000_0A280000_0000_0A000000  // inject EE 11 E1 1E EE EE EE EE
0_0000_0A280000_0000_0A000000  // inject EE 11 E1 1E EE EE EE EE
0_0000_2AA80000_0000_2A580000  // inject E1 11 11 1E EE EE EE EE

// new configuration (3 bit adder with all i/o on top):
//
// ||N00|.N00|.N00|
// |NN11|NN11|NN11|
// |||..|||..|||..|
// ||0N0||0N0||0N0|
// |N1N1|N1N1|N1N1|
// |..|Y+0.|Y+0.|Y1
// Y--1.Y--1.Y--1..
// ................
// ................
// ................
// ................
// ................
// ................
// ................
// ................
// ................
//
// breaking it into bits:  .  +  -  |  1  0  Y  N
//                   msb   0  0  0  0  1  1  1  1
//                         0  0  1  1  0  0  1  1
//                   lsb   0  1  0  1  0  1  0  1
2_0000_00000000_0000_00000000  // reset everything
2_0000_00000000_0000_00000000  // msb bit 15: ................
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // middle bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // lsb bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // msb bit 14: ................
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // middle bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // lsb bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // msb bit 13: ................
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // middle bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // lsb bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // msb bit 12: ................
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // middle bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // lsb bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // msb bit 11: ................
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // middle bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // lsb bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // msb bit 10: ................
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // middle bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // lsb bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // msb bit 09: ................
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // middle bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // lsb bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // msb bit 08: ................
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // middle bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // lsb bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // msb bit 07: ................
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // middle bit
3_0000_00000000_0000_00000000
2_0000_00000000_0000_00000000  // lsb bit
3_0000_00000000_0000_00000000
2_94A4_00000000_0000_00000000  // msb bit 06: Y--1 .Y-- 1.Y- -1..
3_94A4_00000000_0000_00000000  //             1001 0100 1010 0100
2_E738_00000000_0000_00000000  // middle bit  1110 0111 0011 1000
3_E738_00000000_0000_00000000  //             0000 0000 0000 0000
2_0000_00000000_0000_00000000  // lsb bit
3_0000_00000000_0000_00000000
2_0A53_00000000_0000_00000000  // msb bit 05: |..| Y+0. |Y+0 .|Y1
3_0A53_00000000_0000_00000000  //             0000 1010 0101 0011
2_98C6_00000000_0000_00000000  // middle bit  1001 1000 1100 0110
3_98C6_00000000_0000_00000000  //             1001 0110 1011 0100
2_96B4_00000000_0000_00000000  // lsb bit
3_96B4_00000000_0000_00000000
2_7BBE_00000000_0000_00000000  // msb bit 04: |N1N 1|N1 N1|N 1N1|
3_7BBE_00000000_0000_00000000  //             0111 1011 1101 1110
2_D6B5_00000000_0000_00000000  // middle bit  1101 0110 1011 0101
3_D6B5_00000000_0000_00000000  //             1101 0110 1011 0101
2_D6B5_00000000_0000_00000000  // lsb bit
3_D6B5_00000000_0000_00000000
2_39CE_00000000_0000_00000000  // msb bit 03: ||0N 0||0 N0|| 0N0|
3_39CE_00000000_0000_00000000  //             0011 1001 1100 1110
2_D6B5_00000000_0000_00000000  // middle bit  1101 0110 1011 0101
3_D6B5_00000000_0000_00000000  //             1111 1111 1111 1111
2_FFFF_00000000_0000_00000000  // lsb bit
3_FFFF_00000000_0000_00000000
2_0000_00000000_0000_00000000  // msb bit 02: |||. .||| ..|| |..|
3_0000_00000000_0000_00000000  //             0000 0000 0000 0000
2_E739_00000000_0000_00000000  // middle bit  1110 0111 0011 1001
3_E739_00000000_0000_00000000  //             1110 0111 0011 1001
2_E739_00000000_0000_00000000  // lsb bit
3_E739_00000000_0000_00000000
2_7BBE_00000000_0000_00000000  // msb bit 01: |NN1 1|NN 11|N N11|
3_7BBE_00000000_0000_00000000  //             0111 1011 1101 1110
2_E739_00000000_0000_00000000  // middle bit  1110 0111 0011 1001
3_E739_00000000_0000_00000000  //             1110 0111 0011 1001
2_E739_00000000_0000_00000000  // lsb bit
3_E739_00000000_0000_00000000
2_39CE_00000000_0000_00000000  // msb bit 00: ||N0 0|.N 00|. N00|
3_39CE_00000000_0000_00000000  //             0011 1001 1100 1110
2_E529_00000000_0000_00000000  // middle bit  1110 0101 0010 1001
3_E529_00000000_0000_00000000  //             1111 1101 1110 1111
2_FDEF_00000000_0000_00000000  // lsb bit
3_FDEF_00000000_0000_00000000
4_0000_00000000_0000_00000000