
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 428 cell types from liberty file.

2. Executing Verilog-2005 frontend: /project/openlane/morphle_yblock/../../verilog/morphle/ycell.v
Parsing Verilog input from `/project/openlane/morphle_yblock/../../verilog/morphle/ycell.v' to AST representation.
Generating RTLIL representation for module `\ycfsm'.
Generating RTLIL representation for module `\ycconfig'.
Generating RTLIL representation for module `\ycell'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /project/openlane/morphle_yblock/../../verilog/morphle/yblock.v
Parsing Verilog input from `/project/openlane/morphle_yblock/../../verilog/morphle/yblock.v' to AST representation.
Generating RTLIL representation for module `\yblock'.
Successfully finished Verilog frontend.

4. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/morphle_yblock/runs/morphle_yblock/tmp/synthesis/hierarchy.dot'.
Dumping module yblock to page 1.

5. Executing HIERARCHY pass (managing design hierarchy).

5.1. Analyzing design hierarchy..
Top module:  \yblock

5.2. Analyzing design hierarchy..
Top module:  \yblock
Removed 0 unused modules.

6. Printing statistics.

=== yblock ===

   Number of wires:               2946
   Number of wire bits:          32130
   Number of public wires:         119
   Number of public wire bits:    1290
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:           1409
   Number of cells:                 64
     ycell                          64

7. Executing SPLITNETS pass (splitting up multi-bit signals).
Warning: Ignoring module yblock because it contains processes (run 'proc' command first).

8. Executing OPT_CLEAN pass (remove unused cells and wires).
Warning: Ignoring module yblock because it contains processes (run 'proc' command first).

9. Executing CHECK pass (checking for obvious problems).
Warning: Ignoring module yblock because it contains processes (run 'proc' command first).
found and reported 0 problems.

10. Printing statistics.

=== yblock ===

   Number of wires:               2946
   Number of wire bits:          32130
   Number of public wires:         119
   Number of public wire bits:    1290
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:           1409
   Number of cells:                 64
     ycell                          64

   Area for cell type \ycell is unknown!

11. Executing Verilog backend.
Dumping module `\yblock'.
Warning: Module yblock contains unmapped RTLIL processes. RTLIL processes
can't always be mapped directly to Verilog always blocks. Unintended
changes in simulation behavior are possible! Use "proc" to convert
processes to logic networks and registers.

Warnings: 2 unique messages, 4 total
End of script. Logfile hash: dfed0103d6, CPU: user 1.35s system 0.02s, MEM: 41.75 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 35% 2x read_liberty (0 sec), 33% 4x read_verilog (0 sec), ...