diff --git a/openlane/README.md b/openlane/README.md
index eceecbd..49aad65 100644
--- a/openlane/README.md
+++ b/openlane/README.md
@@ -25,7 +25,7 @@
 export OPENLANE_ROOT=<the absolute path to the openlane directory cloned or to be cloned>
 ```
 
-**NOTE:** rc6 and caravel are still WIP so expect to run into some issues when using it.
+**NOTE:** caravel is still a WIP so expect to run into some issues when using it.
 
 If you don't have openlane already, then you can get it from [here](https://github.com/efabless/openlane). Alternatively, you can clone and build openlane through:
 ```bash
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 182ed6b..4e5cc61 100644
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -29,7 +29,6 @@
 set ::env(DIE_AREA) "0 0 600 600"
 set ::env(DESIGN_IS_CORE) 0
 
-
 set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
 set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
 
@@ -37,3 +36,6 @@
 
 set ::env(PL_BASIC_PLACEMENT) 1
 set ::env(PL_TARGET_DENSITY) 0.15
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 53b8b7b..6e403b9 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -21,17 +21,23 @@
 
 
 # User Configurations
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
 
+## Source Verilog Files
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/defines.v \
+	$script_dir/../../verilog/rtl/user_project_wrapper.v"
+
+## Clock configurations
 set ::env(CLOCK_PORT) "user_clock2"
 set ::env(CLOCK_NET) "mprj.clk"
 
 set ::env(CLOCK_PERIOD) "10"
 
-set ::env(VERILOG_FILES) "\
-	$script_dir/../../verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_project_wrapper.v"
+## Internal Macros
+### Macro Placement
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
 
+### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
 	$script_dir/../../verilog/rtl/defines.v \
 	$script_dir/../../verilog/rtl/user_proj_example.v"
@@ -57,6 +63,9 @@
 set ::env(MAGIC_ZEROIZE_ORIGIN) 0
 set ::env(MAGIC_WRITE_FULL_LEF) 1
 
+
+# DON'T TOUCH THE FOLLOWING SECTIONS
+
 # Area Configurations. DON'T TOUCH.
 set ::env(FP_SIZING) absolute
 set ::env(DIE_AREA) "0 0 2920 3520"
@@ -76,11 +85,11 @@
 set ::env(FP_PDN_CORE_RING_VOFFSET) 0
 set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
 
-
 set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
 set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
 set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+set ::env(RUN_CVC) 0
 
 # Pin Configurations. DON'T TOUCH
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg