)]}'
{
  "commit": "36de0c857082cdbfeafa252927b1da998cdc7647",
  "tree": "365495c5c536ffed3fde34aa536d23e4ee4ee77a",
  "parents": [
    "7fd51057da3fec004354534cf9c0838e526da81c"
  ],
  "author": {
    "name": "Jecel Assumpcao Jr",
    "email": "jecel@merlintec.com",
    "time": "Tue Dec 01 20:40:59 2020 -0300"
  },
  "committer": {
    "name": "Jecel Assumpcao Jr",
    "email": "jecel@merlintec.com",
    "time": "Tue Dec 01 20:40:59 2020 -0300"
  },
  "message": "both yosys and iverilog seem to support signal arrays, so yblock can be much simpler\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0f00b045e84b1b6087b279878e7f1302f1e1aedc",
      "old_mode": 33261,
      "old_path": "verilog/morphle/config_block.tcl",
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      "new_mode": 33261,
      "new_path": "verilog/morphle/config_block.tcl"
    },
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}