
reading lef ...

units:       1000
#layers:     13
#macros:     438
#vias:       25
#viarulegen: 25

reading def ...

design:      user_id_programming
die area:    ( 0 0 ) ( 35545 35385 )
trackPts:    12
defvias:     4
#components: 113
#terminals:  34
#snets:      2
#nets:       64

reading guide ...

#guides:     157
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx
List of default vias:
  Layer mcon
    default via: L1M1_PR_MR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: via2_FR
  Layer via3
    default via: M3M4_PR_M
  Layer via4
    default via: via4_FR
Writing reference output def...

libcell analysis ...

instance analysis ...
#unique instances = 19

init region query ...
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

FR_MASTERSLICE shape region query size = 0
FR_VIA shape region query size = 0
li1 shape region query size = 600
mcon shape region query size = 954
met1 shape region query size = 261
via shape region query size = 100
met2 shape region query size = 70
via2 shape region query size = 100
met3 shape region query size = 62
via3 shape region query size = 100
met4 shape region query size = 43
via4 shape region query size = 13
met5 shape region query size = 20


start pin access
  complete 4 pins
  complete 14 unique inst patterns
  complete 27 groups
Expt1 runtime (pin-level access point gen): 0.0195728
Expt2 runtime (design-level access pattern gen): 0.00326045
#scanned instances     = 113
#unique  instances     = 19
#stdCellGenAp          = 16
#stdCellValidPlanarAp  = 0
#stdCellValidViaAp     = 16
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 64
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0

complete pin access
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.80 (MB), peak = 13.13 (MB)

post process guides ...
GCELLGRID X -1 DO 5 STEP 6900 ;
GCELLGRID Y -1 DO 5 STEP 6900 ;
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

building cmap ... 

init guide query ...
  complete FR_MASTERSLICE (guide)
  complete FR_VIA (guide)
  complete li1 (guide)
  complete mcon (guide)
  complete met1 (guide)
  complete via (guide)
  complete met2 (guide)
  complete via2 (guide)
  complete met3 (guide)
  complete via3 (guide)
  complete met4 (guide)
  complete via4 (guide)
  complete met5 (guide)

FR_MASTERSLICE guide region query size = 0
FR_VIA guide region query size = 0
li1 guide region query size = 32
mcon guide region query size = 0
met1 guide region query size = 37
via guide region query size = 0
met2 guide region query size = 41
via2 guide region query size = 0
met3 guide region query size = 12
via3 guide region query size = 0
met4 guide region query size = 0
via4 guide region query size = 0
met5 guide region query size = 0

init gr pin query ...


start track assignment
Done with 73 vertical wires in 1 frboxes and 49 horizontal wires in 1 frboxes.
Done with 16 vertical wires in 1 frboxes and 12 horizontal wires in 1 frboxes.

complete track assignment
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 13.81 (MB), peak = 13.85 (MB)

post processing ...

start routing data preparation
initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 13.81 (MB), peak = 13.85 (MB)

start detail routing ...
start 0th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 17.00 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 17.12 (MB), peak = 377.68 (MB)
total wire length = 728 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 193 um
total wire length on LAYER met2 = 397 um
total wire length on LAYER met3 = 137 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 82
up-via summary (total 82):

---------------------
 FR_MASTERSLICE     0
            li1    32
           met1    38
           met2    12
           met3     0
           met4     0
---------------------
                   82


start 1st optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 18.40 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 18.66 (MB), peak = 377.68 (MB)
total wire length = 728 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 193 um
total wire length on LAYER met2 = 397 um
total wire length on LAYER met3 = 137 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 82
up-via summary (total 82):

---------------------
 FR_MASTERSLICE     0
            li1    32
           met1    38
           met2    12
           met3     0
           met4     0
---------------------
                   82


start 2nd optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 18.66 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 19.40 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 20.32 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 20.32 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20.32 (MB), peak = 377.68 (MB)
total wire length = 728 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 193 um
total wire length on LAYER met2 = 397 um
total wire length on LAYER met3 = 137 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 82
up-via summary (total 82):

---------------------
 FR_MASTERSLICE     0
            li1    32
           met1    38
           met2    12
           met3     0
           met4     0
---------------------
                   82


start 17th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 21.93 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 21.34 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 21.59 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 21.68 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 21.68 (MB), peak = 377.68 (MB)
total wire length = 728 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 193 um
total wire length on LAYER met2 = 397 um
total wire length on LAYER met3 = 137 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 82
up-via summary (total 82):

---------------------
 FR_MASTERSLICE     0
            li1    32
           met1    38
           met2    12
           met3     0
           met4     0
---------------------
                   82


start 25th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 22.55 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 22.55 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 22.07 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 21.18 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 21.18 (MB), peak = 377.68 (MB)
total wire length = 728 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 193 um
total wire length on LAYER met2 = 397 um
total wire length on LAYER met3 = 137 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 82
up-via summary (total 82):

---------------------
 FR_MASTERSLICE     0
            li1    32
           met1    38
           met2    12
           met3     0
           met4     0
---------------------
                   82


start 33rd optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 21.18 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 21.18 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 21.18 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 22.57 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 22.57 (MB), peak = 377.68 (MB)
total wire length = 728 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 193 um
total wire length on LAYER met2 = 397 um
total wire length on LAYER met3 = 137 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 82
up-via summary (total 82):

---------------------
 FR_MASTERSLICE     0
            li1    32
           met1    38
           met2    12
           met3     0
           met4     0
---------------------
                   82


start 41st optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 22.56 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 21.35 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 19.41 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 19.41 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 19.55 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 19.56 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 19.65 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 19.72 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 21.65 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 21.65 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 21.65 (MB), peak = 377.68 (MB)
total wire length = 728 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 193 um
total wire length on LAYER met2 = 397 um
total wire length on LAYER met3 = 137 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 82
up-via summary (total 82):

---------------------
 FR_MASTERSLICE     0
            li1    32
           met1    38
           met2    12
           met3     0
           met4     0
---------------------
                   82


start 49th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 22.53 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 22.53 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 22.08 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 22.06 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 22.06 (MB), peak = 377.68 (MB)
total wire length = 728 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 193 um
total wire length on LAYER met2 = 397 um
total wire length on LAYER met3 = 137 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 82
up-via summary (total 82):

---------------------
 FR_MASTERSLICE     0
            li1    32
           met1    38
           met2    12
           met3     0
           met4     0
---------------------
                   82


start 57th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 22.06 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 21.91 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 21.91 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 20.96 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20.96 (MB), peak = 377.68 (MB)
total wire length = 728 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 193 um
total wire length on LAYER met2 = 397 um
total wire length on LAYER met3 = 137 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 82
up-via summary (total 82):

---------------------
 FR_MASTERSLICE     0
            li1    32
           met1    38
           met2    12
           met3     0
           met4     0
---------------------
                   82


complete detail routing
total wire length = 728 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 193 um
total wire length on LAYER met2 = 397 um
total wire length on LAYER met3 = 137 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 82
up-via summary (total 82):

---------------------
 FR_MASTERSLICE     0
            li1    32
           met1    38
           met2    12
           met3     0
           met4     0
---------------------
                   82

cpu time = 00:00:01, elapsed time = 00:00:00, memory = 20.96 (MB), peak = 377.68 (MB)

post processing ...

Runtime taken (hrt): 1.96486