
reading lef ...

units:       1000
#layers:     13
#macros:     437
#vias:       25
#viarulegen: 25

reading def ...

design:      ycell
die area:    ( 0 0 ) ( 63845 74565 )
trackPts:    12
defvias:     3
#components: 360
#terminals:  32
#snets:      2
#nets:       125

reading guide ...

#guides:     896
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx
List of default vias:
  Layer mcon
    default via: L1M1_PR_MR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: via2_FR
  Layer via3
    default via: M3M4_PR_M
  Layer via4
    default via: via4_FR
Writing reference output def...

libcell analysis ...

instance analysis ...
#unique instances = 54

init region query ...
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

FR_MASTERSLICE shape region query size = 0
FR_VIA shape region query size = 0
li1 shape region query size = 3996
mcon shape region query size = 4350
met1 shape region query size = 832
via shape region query size = 200
met2 shape region query size = 118
via2 shape region query size = 200
met3 shape region query size = 112
via3 shape region query size = 200
met4 shape region query size = 57
via4 shape region query size = 0
met5 shape region query size = 0


start pin access
  complete 100 pins
  complete 122 pins
  complete 48 unique inst patterns
  complete 110 groups
Expt1 runtime (pin-level access point gen): 0.185521
Expt2 runtime (design-level access pattern gen): 0.0348167
#scanned instances     = 360
#unique  instances     = 54
#stdCellGenAp          = 801
#stdCellValidPlanarAp  = 0
#stdCellValidViaAp     = 548
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 341
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0

complete pin access
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 13.45 (MB), peak = 13.85 (MB)

post process guides ...
GCELLGRID X -1 DO 10 STEP 6900 ;
GCELLGRID Y -1 DO 9 STEP 6900 ;
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

building cmap ... 

init guide query ...
  complete FR_MASTERSLICE (guide)
  complete FR_VIA (guide)
  complete li1 (guide)
  complete mcon (guide)
  complete met1 (guide)
  complete via (guide)
  complete met2 (guide)
  complete via2 (guide)
  complete met3 (guide)
  complete via3 (guide)
  complete met4 (guide)
  complete via4 (guide)
  complete met5 (guide)

FR_MASTERSLICE guide region query size = 0
FR_VIA guide region query size = 0
li1 guide region query size = 320
mcon guide region query size = 0
met1 guide region query size = 295
via guide region query size = 0
met2 guide region query size = 178
via2 guide region query size = 0
met3 guide region query size = 12
via3 guide region query size = 0
met4 guide region query size = 0
via4 guide region query size = 0
met5 guide region query size = 0

init gr pin query ...


start track assignment
Done with 498 vertical wires in 1 frboxes and 307 horizontal wires in 1 frboxes.
Done with 96 vertical wires in 1 frboxes and 116 horizontal wires in 1 frboxes.

complete track assignment
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.71 (MB), peak = 15.84 (MB)

post processing ...

start routing data preparation
initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.85 (MB), peak = 15.84 (MB)

start detail routing ...
start 0th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 26.09 (MB)
    completing 20% with 80 violations
    elapsed time = 00:00:00, memory = 22.37 (MB)
    completing 30% with 74 violations
    elapsed time = 00:00:01, memory = 19.55 (MB)
    completing 40% with 84 violations
    elapsed time = 00:00:01, memory = 17.39 (MB)
  number of violations = 92
cpu time = 00:00:01, elapsed time = 00:00:01, memory = 337.87 (MB), peak = 381.68 (MB)
total wire length = 4731 um
total wire length on LAYER li1 = 1 um
total wire length on LAYER met1 = 2370 um
total wire length on LAYER met2 = 2202 um
total wire length on LAYER met3 = 157 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 797
up-via summary (total 797):

----------------------
 FR_MASTERSLICE      0
            li1    343
           met1    440
           met2     14
           met3      0
           met4      0
----------------------
                   797


start 1st optimization iteration ...
    completing 10% with 92 violations
    elapsed time = 00:00:00, memory = 337.87 (MB)
    completing 20% with 94 violations
    elapsed time = 00:00:00, memory = 347.05 (MB)
    completing 30% with 108 violations
    elapsed time = 00:00:00, memory = 344.31 (MB)
    completing 40% with 80 violations
    elapsed time = 00:00:00, memory = 345.55 (MB)
  number of violations = 30
cpu time = 00:00:01, elapsed time = 00:00:01, memory = 338.00 (MB), peak = 381.70 (MB)
total wire length = 4674 um
total wire length on LAYER li1 = 1 um
total wire length on LAYER met1 = 2299 um
total wire length on LAYER met2 = 2221 um
total wire length on LAYER met3 = 152 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 803
up-via summary (total 803):

----------------------
 FR_MASTERSLICE      0
            li1    343
           met1    444
           met2     16
           met3      0
           met4      0
----------------------
                   803


start 2nd optimization iteration ...
    completing 10% with 30 violations
    elapsed time = 00:00:00, memory = 338.00 (MB)
    completing 20% with 30 violations
    elapsed time = 00:00:00, memory = 338.00 (MB)
    completing 30% with 30 violations
    elapsed time = 00:00:00, memory = 340.00 (MB)
    completing 40% with 30 violations
    elapsed time = 00:00:00, memory = 340.00 (MB)
    completing 50% with 30 violations
    elapsed time = 00:00:00, memory = 338.82 (MB)
    completing 60% with 30 violations
    elapsed time = 00:00:01, memory = 358.01 (MB)
  number of violations = 37
cpu time = 00:00:01, elapsed time = 00:00:01, memory = 338.00 (MB), peak = 381.70 (MB)
total wire length = 4603 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 2243 um
total wire length on LAYER met2 = 2213 um
total wire length on LAYER met3 = 147 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 773
up-via summary (total 773):

----------------------
 FR_MASTERSLICE      0
            li1    341
           met1    418
           met2     14
           met3      0
           met4      0
----------------------
                   773


start 3rd optimization iteration ...
    completing 10% with 37 violations
    elapsed time = 00:00:00, memory = 352.89 (MB)
    completing 20% with 15 violations
    elapsed time = 00:00:00, memory = 343.40 (MB)
    completing 30% with 2 violations
    elapsed time = 00:00:00, memory = 340.45 (MB)
    completing 40% with 2 violations
    elapsed time = 00:00:00, memory = 337.88 (MB)
  number of violations = 2
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 337.88 (MB), peak = 381.70 (MB)
total wire length = 4592 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 2197 um
total wire length on LAYER met2 = 2200 um
total wire length on LAYER met3 = 194 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 779
up-via summary (total 779):

----------------------
 FR_MASTERSLICE      0
            li1    341
           met1    417
           met2     21
           met3      0
           met4      0
----------------------
                   779


start 4th optimization iteration ...
    completing 10% with 2 violations
    elapsed time = 00:00:00, memory = 340.60 (MB)
    completing 20% with 2 violations
    elapsed time = 00:00:00, memory = 339.34 (MB)
    completing 30% with 2 violations
    elapsed time = 00:00:00, memory = 341.61 (MB)
    completing 40% with 2 violations
    elapsed time = 00:00:00, memory = 343.39 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 339.34 (MB), peak = 382.39 (MB)
total wire length = 4593 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 2199 um
total wire length on LAYER met2 = 2199 um
total wire length on LAYER met3 = 194 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 781
up-via summary (total 781):

----------------------
 FR_MASTERSLICE      0
            li1    341
           met1    419
           met2     21
           met3      0
           met4      0
----------------------
                   781


start 17th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 339.34 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 342.79 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 341.57 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 343.80 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 343.80 (MB), peak = 382.39 (MB)
total wire length = 4593 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 2199 um
total wire length on LAYER met2 = 2199 um
total wire length on LAYER met3 = 194 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 781
up-via summary (total 781):

----------------------
 FR_MASTERSLICE      0
            li1    341
           met1    419
           met2     21
           met3      0
           met4      0
----------------------
                   781


start 25th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 343.80 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 337.87 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 337.87 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 337.87 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 339.20 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 341.13 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 340.09 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 339.84 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 344.01 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 344.01 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 344.01 (MB), peak = 382.39 (MB)
total wire length = 4593 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 2199 um
total wire length on LAYER met2 = 2199 um
total wire length on LAYER met3 = 194 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 781
up-via summary (total 781):

----------------------
 FR_MASTERSLICE      0
            li1    341
           met1    419
           met2     21
           met3      0
           met4      0
----------------------
                   781


start 33rd optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 338.30 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 339.64 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 337.96 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 338.94 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 338.94 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 338.69 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 340.95 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 340.56 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 339.06 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 339.75 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 339.75 (MB), peak = 382.39 (MB)
total wire length = 4593 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 2199 um
total wire length on LAYER met2 = 2199 um
total wire length on LAYER met3 = 194 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 781
up-via summary (total 781):

----------------------
 FR_MASTERSLICE      0
            li1    341
           met1    419
           met2     21
           met3      0
           met4      0
----------------------
                   781


start 41st optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 339.75 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 340.59 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 340.32 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 339.92 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 339.65 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 339.65 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 340.14 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 339.83 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 341.62 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 341.44 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 341.44 (MB), peak = 382.39 (MB)
total wire length = 4593 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 2199 um
total wire length on LAYER met2 = 2199 um
total wire length on LAYER met3 = 194 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 781
up-via summary (total 781):

----------------------
 FR_MASTERSLICE      0
            li1    341
           met1    419
           met2     21
           met3      0
           met4      0
----------------------
                   781


start 49th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 340.05 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 341.08 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 340.92 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 340.18 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 340.18 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 341.08 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 340.45 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 341.38 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 340.93 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 342.71 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 342.71 (MB), peak = 382.39 (MB)
total wire length = 4593 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 2199 um
total wire length on LAYER met2 = 2199 um
total wire length on LAYER met3 = 194 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 781
up-via summary (total 781):

----------------------
 FR_MASTERSLICE      0
            li1    341
           met1    419
           met2     21
           met3      0
           met4      0
----------------------
                   781


start 57th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 338.23 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 338.31 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 338.07 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 339.62 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 339.62 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 339.62 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 340.50 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 339.22 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 338.99 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 339.53 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 339.53 (MB), peak = 382.39 (MB)
total wire length = 4593 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 2199 um
total wire length on LAYER met2 = 2199 um
total wire length on LAYER met3 = 194 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 781
up-via summary (total 781):

----------------------
 FR_MASTERSLICE      0
            li1    341
           met1    419
           met2     21
           met3      0
           met4      0
----------------------
                   781


complete detail routing
total wire length = 4593 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 2199 um
total wire length on LAYER met2 = 2199 um
total wire length on LAYER met3 = 194 um
total wire length on LAYER met4 = 0 um
total wire length on LAYER met5 = 0 um
total number of vias = 781
up-via summary (total 781):

----------------------
 FR_MASTERSLICE      0
            li1    341
           met1    419
           met2     21
           met3      0
           met4      0
----------------------
                   781

cpu time = 00:00:07, elapsed time = 00:00:05, memory = 339.53 (MB), peak = 382.39 (MB)

post processing ...

Runtime taken (hrt): 6.63546