diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem.c b/verilog/dv/caravel/mgmt_soc/mem/mem.c
index 7fbf8ad..52b0a12 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem.c
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem.c
@@ -41,11 +41,12 @@
     // start test
     reg_mprj_datal = 0xA0400000;
 
+    i = 0;
     // Test Word R/W
-    for (i=0; i<10; i++)
+    // for (i=0; i<1; i++)
 	ints[i] = i*5000 + 10000;
 	
-    for (i=0; i<10; i++)
+    // for (i=0; i<1; i++)
 	if ((i*5000+10000) != ints[i])
 	    reg_mprj_datal = 0xAB400000;
 
@@ -53,10 +54,10 @@
 	
     // Test Half Word R/W
     reg_mprj_datal = 0xA0200000;
-    for (i=0; i<10; i++)
+    // for (i=0; i<1; i++)
 	shorts[i] = i*500 + 100;
 	
-    for(i=0; i<10; i++)
+    // for(i=0; i<1; i++)
 	if((i*500+100) != shorts[i])
 	    reg_mprj_datal = 0xAB200000;
 
@@ -64,10 +65,10 @@
 
     // Test byte R/W
     reg_mprj_datal = 0xA0100000;
-    for(i=0; i<10; i++)
+    // for(i=0; i<1; i++)
 	bytes[i] = i*5 + 10;
 	
-    for(i=0; i<10; i++)
+    // for(i=0; i<1; i++)
 	if((i*5+10) != bytes[i])
 	    reg_mprj_datal = 0xAB100000;
 
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
index f3c1d3c..a82184c 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -157,6 +157,8 @@
 	assign VDD3V3 = power1;
 	assign VDD1V8 = power2;
 
+	assign mprj_io[3] = 1'b1;       // Force CSB high.
+
 	caravel uut (
 		.vddio	  (VDD3V3),
 		.vssio	  (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
index 75b41d4..4625f32 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
@@ -46,7 +46,7 @@
     reg_mprj_io_6  = GPIO_MODE_USER_STD_OUTPUT;
     reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
     reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
+    // reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
     reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
     reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
     reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index 6c295d5..ffc74a9 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -118,6 +118,8 @@
 	assign VDD1V8 = power2;
 	assign VSS = 1'b0;
 
+	assign user_io[3] = 1'b1;
+	
 	caravel uut (
 		.vddio	  (VDD3V3),
 		.vssio	  (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
index 8922a74..c086226 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
@@ -113,6 +113,8 @@
 	assign VDD1V8 = power2;
 	assign VSS = 1'b0;
 
+	assign mprj_io[3] = 1'b1;       // Force CSB high.
+
 	caravel uut (
 		.vddio	  (VDD3V3),
 		.vssio	  (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
index a15cc17..b9a6dd8 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
@@ -110,6 +110,8 @@
 	assign VDD1V8 = power2;
 	assign VSS = 1'b0;
 
+	assign mprj_io[3] = 1'b1;  // Force CSB high.
+
 	caravel uut (
 		.vddio	  (VDD3V3),
 		.vssio	  (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
index e8c4d6b..cfbe150 100644
--- a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
@@ -144,6 +144,8 @@
 	assign VDD3V3 = power1;
 	assign VDD1V8 = power2;
 
+	assign mprj_io[3] = 1'b1;  // Force CSB high.
+
 	caravel uut (
 		.vddio	  (VDD3V3),
 		.vssio	  (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
index ba048ee..509bc20 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -162,6 +162,8 @@
 	assign VDD1V8 = power2;
 	assign VSS = 1'b0;
 
+	assign mprj_io[3] = 1'b1;
+	
 	caravel uut (
 		.vddio	  (VDD3V3),
 		.vssio	  (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
index caca65a..298e882 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -98,6 +98,8 @@
 	assign VDD3V3 = power1;
 	assign VDD1V8 = power2;
 	assign VSS = 1'b0;
+	
+	assign mprj_io[3] = 1'b1;  // Force CSB high.
 
 	caravel uut (
 		.vddio	  (VDD3V3),