
reading lef ...

units:       1000
#layers:     13
#macros:     438
#vias:       25
#viarulegen: 25

reading def ...

design:      user_project_wrapper
die area:    ( 0 0 ) ( 2700000 3700000 )
trackPts:    12
defvias:     0
#components: 1
#terminals:  613
#snets:      0
#nets:       613

reading guide ...

#guides:     4638
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx
List of default vias:
  Layer mcon
    default via: L1M1_PR_MR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: via2_FR
  Layer via3
    default via: M3M4_PR_M
  Layer via4
    default via: via4_FR
Writing reference output def...

libcell analysis ...

instance analysis ...
#unique instances = 1

init region query ...
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

FR_MASTERSLICE shape region query size = 0
FR_VIA shape region query size = 0
li1 shape region query size = 1
mcon shape region query size = 0
met1 shape region query size = 1
via shape region query size = 0
met2 shape region query size = 1056
via2 shape region query size = 0
met3 shape region query size = 759
via3 shape region query size = 0
met4 shape region query size = 1
via4 shape region query size = 0
met5 shape region query size = 3


start pin access
  complete 100 pins
  complete 200 pins
  complete 300 pins
  complete 400 pins
  complete 500 pins
  complete 600 pins
  complete 612 pins
  complete 0 unique inst patterns
  complete 0 groups
Expt1 runtime (pin-level access point gen): 1.40217
Expt2 runtime (design-level access pattern gen): 5.9135e-05
#scanned instances     = 1
#unique  instances     = 1
#stdCellGenAp          = 0
#stdCellValidPlanarAp  = 0
#stdCellValidViaAp     = 0
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 0
#instTermValidViaApCnt = 0
#macroGenAp            = 3122
#macroValidPlanarAp    = 3122
#macroValidViaAp       = 0
#macroNoAp             = 0

complete pin access
cpu time = 00:00:01, elapsed time = 00:00:01, memory = 18.15 (MB), peak = 18.18 (MB)

post process guides ...
GCELLGRID X -1 DO 536 STEP 6900 ;
GCELLGRID Y -1 DO 391 STEP 6900 ;
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

building cmap ... 

init guide query ...
  complete FR_MASTERSLICE (guide)
  complete FR_VIA (guide)
  complete li1 (guide)
  complete mcon (guide)
  complete met1 (guide)
  complete via (guide)
  complete met2 (guide)
  complete via2 (guide)
  complete met3 (guide)
  complete via3 (guide)
  complete met4 (guide)
  complete via4 (guide)
  complete met5 (guide)

FR_MASTERSLICE guide region query size = 0
FR_VIA guide region query size = 0
li1 guide region query size = 0
mcon guide region query size = 0
met1 guide region query size = 812
via guide region query size = 0
met2 guide region query size = 1706
via2 guide region query size = 0
met3 guide region query size = 548
via3 guide region query size = 0
met4 guide region query size = 2
via4 guide region query size = 0
met5 guide region query size = 0

init gr pin query ...


start track assignment
Done with 1708 vertical wires in 8 frboxes and 1360 horizontal wires in 11 frboxes.
Done with 187 vertical wires in 8 frboxes and 157 horizontal wires in 11 frboxes.

complete track assignment
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 119.69 (MB), peak = 120.79 (MB)

post processing ...

start routing data preparation
initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 159.13 (MB), peak = 159.36 (MB)

start detail routing ...
start 0th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:02, memory = 219.74 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:05, memory = 262.39 (MB)
    completing 30% with 8690 violations
    elapsed time = 00:00:07, memory = 227.24 (MB)
    completing 40% with 8690 violations
    elapsed time = 00:00:10, memory = 255.09 (MB)
    completing 50% with 6878 violations
    elapsed time = 00:00:12, memory = 214.55 (MB)
    completing 60% with 6884 violations
    elapsed time = 00:00:14, memory = 239.39 (MB)
    completing 70% with 6884 violations
    elapsed time = 00:00:17, memory = 267.66 (MB)
    completing 80% with 8997 violations
    elapsed time = 00:00:19, memory = 226.10 (MB)
    completing 90% with 8997 violations
    elapsed time = 00:00:22, memory = 257.70 (MB)
    completing 100% with 1708 violations
    elapsed time = 00:00:24, memory = 206.46 (MB)
  number of violations = 1714
cpu time = 00:01:13, elapsed time = 00:00:25, memory = 436.37 (MB), peak = 471.23 (MB)
total wire length = 1514930 um
total wire length on LAYER li1 = 32 um
total wire length on LAYER met1 = 552787 um
total wire length on LAYER met2 = 942917 um
total wire length on LAYER met3 = 16117 um
total wire length on LAYER met4 = 3077 um
total wire length on LAYER met5 = 0 um
total number of vias = 2826
up-via summary (total 2826):

-----------------------
 FR_MASTERSLICE       0
            li1      22
           met1    2192
           met2     608
           met3       4
           met4       0
-----------------------
                   2826


start 1st optimization iteration ...
    completing 10% with 1714 violations
    elapsed time = 00:00:01, memory = 472.54 (MB)
    completing 20% with 1714 violations
    elapsed time = 00:00:04, memory = 500.50 (MB)
    completing 30% with 1263 violations
    elapsed time = 00:00:05, memory = 457.79 (MB)
    completing 40% with 1263 violations
    elapsed time = 00:00:07, memory = 484.72 (MB)
    completing 50% with 1590 violations
    elapsed time = 00:00:09, memory = 446.95 (MB)
    completing 60% with 1586 violations
    elapsed time = 00:00:11, memory = 469.60 (MB)
    completing 70% with 1586 violations
    elapsed time = 00:00:13, memory = 501.05 (MB)
    completing 80% with 1341 violations
    elapsed time = 00:00:15, memory = 453.29 (MB)
    completing 90% with 1341 violations
    elapsed time = 00:00:17, memory = 489.78 (MB)
    completing 100% with 1671 violations
    elapsed time = 00:00:19, memory = 440.71 (MB)
  number of violations = 1671
cpu time = 00:00:57, elapsed time = 00:00:19, memory = 440.83 (MB), peak = 512.74 (MB)
total wire length = 1515411 um
total wire length on LAYER li1 = 85 um
total wire length on LAYER met1 = 553975 um
total wire length on LAYER met2 = 943319 um
total wire length on LAYER met3 = 14962 um
total wire length on LAYER met4 = 3068 um
total wire length on LAYER met5 = 0 um
total number of vias = 3154
up-via summary (total 3154):

-----------------------
 FR_MASTERSLICE       0
            li1      68
           met1    2524
           met2     558
           met3       4
           met4       0
-----------------------
                   3154


start 2nd optimization iteration ...
    completing 10% with 1671 violations
    elapsed time = 00:00:00, memory = 444.68 (MB)
    completing 20% with 1671 violations
    elapsed time = 00:00:01, memory = 457.97 (MB)
    completing 30% with 1936 violations
    elapsed time = 00:00:01, memory = 444.33 (MB)
    completing 40% with 1936 violations
    elapsed time = 00:00:02, memory = 454.73 (MB)
    completing 50% with 1994 violations
    elapsed time = 00:00:02, memory = 442.43 (MB)
    completing 60% with 1965 violations
    elapsed time = 00:00:03, memory = 447.03 (MB)
    completing 70% with 1965 violations
    elapsed time = 00:00:04, memory = 454.11 (MB)
    completing 80% with 2403 violations
    elapsed time = 00:00:04, memory = 445.64 (MB)
    completing 90% with 2403 violations
    elapsed time = 00:00:05, memory = 453.69 (MB)
    completing 100% with 2210 violations
    elapsed time = 00:00:05, memory = 437.80 (MB)
  number of violations = 2210
cpu time = 00:00:16, elapsed time = 00:00:05, memory = 437.80 (MB), peak = 512.74 (MB)
total wire length = 1515740 um
total wire length on LAYER li1 = 89 um
total wire length on LAYER met1 = 553734 um
total wire length on LAYER met2 = 943566 um
total wire length on LAYER met3 = 15280 um
total wire length on LAYER met4 = 3068 um
total wire length on LAYER met5 = 0 um
total number of vias = 3262
up-via summary (total 3262):

-----------------------
 FR_MASTERSLICE       0
            li1      92
           met1    2610
           met2     556
           met3       4
           met4       0
-----------------------
                   3262


start 3rd optimization iteration ...
    completing 10% with 2210 violations
    elapsed time = 00:00:02, memory = 444.20 (MB)
    completing 20% with 2210 violations
    elapsed time = 00:00:12, memory = 452.73 (MB)
    completing 30% with 2167 violations
    elapsed time = 00:00:14, memory = 445.83 (MB)
    completing 40% with 2167 violations
    elapsed time = 00:00:20, memory = 453.68 (MB)
    completing 50% with 1220 violations
    elapsed time = 00:00:23, memory = 439.50 (MB)
    completing 60% with 1215 violations
    elapsed time = 00:00:24, memory = 445.71 (MB)
    completing 70% with 1215 violations
    elapsed time = 00:00:29, memory = 449.48 (MB)
    completing 80% with 1078 violations
    elapsed time = 00:00:30, memory = 444.25 (MB)
    completing 90% with 1078 violations
    elapsed time = 00:00:34, memory = 452.51 (MB)
    completing 100% with 736 violations
    elapsed time = 00:00:36, memory = 439.71 (MB)
  number of violations = 736
cpu time = 00:01:47, elapsed time = 00:00:36, memory = 439.70 (MB), peak = 512.74 (MB)
total wire length = 1515717 um
total wire length on LAYER li1 = 7143 um
total wire length on LAYER met1 = 553767 um
total wire length on LAYER met2 = 936049 um
total wire length on LAYER met3 = 15547 um
total wire length on LAYER met4 = 3209 um
total wire length on LAYER met5 = 0 um
total number of vias = 4724
up-via summary (total 4724):

-----------------------
 FR_MASTERSLICE       0
            li1     628
           met1    3432
           met2     646
           met3      18
           met4       0
-----------------------
                   4724


start 4th optimization iteration ...
    completing 10% with 736 violations
    elapsed time = 00:00:00, memory = 444.25 (MB)
    completing 20% with 736 violations
    elapsed time = 00:00:04, memory = 451.74 (MB)
    completing 30% with 622 violations
    elapsed time = 00:00:04, memory = 445.58 (MB)
    completing 40% with 622 violations
    elapsed time = 00:00:08, memory = 447.79 (MB)
    completing 50% with 507 violations
    elapsed time = 00:00:08, memory = 443.10 (MB)
    completing 60% with 507 violations
    elapsed time = 00:00:09, memory = 447.74 (MB)
    completing 70% with 507 violations
    elapsed time = 00:00:10, memory = 449.11 (MB)
    completing 80% with 449 violations
    elapsed time = 00:00:11, memory = 444.12 (MB)
    completing 90% with 449 violations
    elapsed time = 00:00:12, memory = 446.30 (MB)
    completing 100% with 403 violations
    elapsed time = 00:00:13, memory = 436.48 (MB)
  number of violations = 403
cpu time = 00:00:37, elapsed time = 00:00:13, memory = 436.48 (MB), peak = 512.74 (MB)
total wire length = 1515712 um
total wire length on LAYER li1 = 9059 um
total wire length on LAYER met1 = 553817 um
total wire length on LAYER met2 = 934037 um
total wire length on LAYER met3 = 15564 um
total wire length on LAYER met4 = 3234 um
total wire length on LAYER met5 = 0 um
total number of vias = 4978
up-via summary (total 4978):

-----------------------
 FR_MASTERSLICE       0
            li1     710
           met1    3574
           met2     674
           met3      20
           met4       0
-----------------------
                   4978


start 5th optimization iteration ...
    completing 10% with 403 violations
    elapsed time = 00:00:00, memory = 443.59 (MB)
    completing 20% with 403 violations
    elapsed time = 00:00:03, memory = 448.47 (MB)
    completing 30% with 319 violations
    elapsed time = 00:00:03, memory = 436.73 (MB)
    completing 40% with 319 violations
    elapsed time = 00:00:05, memory = 448.39 (MB)
    completing 50% with 225 violations
    elapsed time = 00:00:05, memory = 440.86 (MB)
    completing 60% with 225 violations
    elapsed time = 00:00:05, memory = 440.86 (MB)
    completing 70% with 225 violations
    elapsed time = 00:00:07, memory = 447.32 (MB)
    completing 80% with 187 violations
    elapsed time = 00:00:07, memory = 440.60 (MB)
    completing 90% with 187 violations
    elapsed time = 00:00:07, memory = 447.16 (MB)
    completing 100% with 148 violations
    elapsed time = 00:00:08, memory = 436.48 (MB)
  number of violations = 148
cpu time = 00:00:23, elapsed time = 00:00:08, memory = 436.48 (MB), peak = 512.74 (MB)
total wire length = 1515708 um
total wire length on LAYER li1 = 11014 um
total wire length on LAYER met1 = 553858 um
total wire length on LAYER met2 = 932014 um
total wire length on LAYER met3 = 15579 um
total wire length on LAYER met4 = 3241 um
total wire length on LAYER met5 = 0 um
total number of vias = 5242
up-via summary (total 5242):

-----------------------
 FR_MASTERSLICE       0
            li1     794
           met1    3726
           met2     700
           met3      22
           met4       0
-----------------------
                   5242


start 6th optimization iteration ...
    completing 10% with 148 violations
    elapsed time = 00:00:00, memory = 436.48 (MB)
    completing 20% with 148 violations
    elapsed time = 00:00:01, memory = 446.22 (MB)
    completing 30% with 122 violations
    elapsed time = 00:00:01, memory = 440.19 (MB)
    completing 40% with 122 violations
    elapsed time = 00:00:02, memory = 446.00 (MB)
    completing 50% with 62 violations
    elapsed time = 00:00:02, memory = 436.48 (MB)
    completing 60% with 62 violations
    elapsed time = 00:00:02, memory = 436.48 (MB)
    completing 70% with 62 violations
    elapsed time = 00:00:02, memory = 445.67 (MB)
    completing 80% with 52 violations
    elapsed time = 00:00:02, memory = 436.48 (MB)
    completing 90% with 52 violations
    elapsed time = 00:00:03, memory = 444.75 (MB)
    completing 100% with 38 violations
    elapsed time = 00:00:03, memory = 436.48 (MB)
  number of violations = 38
cpu time = 00:00:09, elapsed time = 00:00:03, memory = 436.48 (MB), peak = 512.74 (MB)
total wire length = 1515719 um
total wire length on LAYER li1 = 11895 um
total wire length on LAYER met1 = 553886 um
total wire length on LAYER met2 = 931113 um
total wire length on LAYER met3 = 15588 um
total wire length on LAYER met4 = 3234 um
total wire length on LAYER met5 = 0 um
total number of vias = 5374
up-via summary (total 5374):

-----------------------
 FR_MASTERSLICE       0
            li1     828
           met1    3810
           met2     716
           met3      20
           met4       0
-----------------------
                   5374


start 7th optimization iteration ...
    completing 10% with 38 violations
    elapsed time = 00:00:00, memory = 436.48 (MB)
    completing 20% with 38 violations
    elapsed time = 00:00:00, memory = 447.98 (MB)
    completing 30% with 24 violations
    elapsed time = 00:00:00, memory = 436.48 (MB)
    completing 40% with 24 violations
    elapsed time = 00:00:00, memory = 444.69 (MB)
    completing 50% with 17 violations
    elapsed time = 00:00:00, memory = 436.48 (MB)
    completing 60% with 17 violations
    elapsed time = 00:00:00, memory = 436.48 (MB)
    completing 70% with 17 violations
    elapsed time = 00:00:00, memory = 447.35 (MB)
    completing 80% with 2 violations
    elapsed time = 00:00:00, memory = 440.13 (MB)
    completing 90% with 2 violations
    elapsed time = 00:00:00, memory = 443.43 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 443.73 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 443.73 (MB), peak = 512.74 (MB)
total wire length = 1515723 um
total wire length on LAYER li1 = 12358 um
total wire length on LAYER met1 = 553894 um
total wire length on LAYER met2 = 930644 um
total wire length on LAYER met3 = 15592 um
total wire length on LAYER met4 = 3234 um
total wire length on LAYER met5 = 0 um
total number of vias = 5422
up-via summary (total 5422):

-----------------------
 FR_MASTERSLICE       0
            li1     846
           met1    3832
           met2     724
           met3      20
           met4       0
-----------------------
                   5422


start 17th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 443.73 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 440.09 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 440.09 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 440.09 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 440.09 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 440.09 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 440.09 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 440.09 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 440.09 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 440.09 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 440.09 (MB), peak = 512.74 (MB)
total wire length = 1515723 um
total wire length on LAYER li1 = 12358 um
total wire length on LAYER met1 = 553894 um
total wire length on LAYER met2 = 930644 um
total wire length on LAYER met3 = 15592 um
total wire length on LAYER met4 = 3234 um
total wire length on LAYER met5 = 0 um
total number of vias = 5422
up-via summary (total 5422):

-----------------------
 FR_MASTERSLICE       0
            li1     846
           met1    3832
           met2     724
           met3      20
           met4       0
-----------------------
                   5422


start 25th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 440.09 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 440.06 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 440.06 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 440.06 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 440.06 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 440.06 (MB), peak = 512.74 (MB)
total wire length = 1515723 um
total wire length on LAYER li1 = 12358 um
total wire length on LAYER met1 = 553894 um
total wire length on LAYER met2 = 930644 um
total wire length on LAYER met3 = 15592 um
total wire length on LAYER met4 = 3234 um
total wire length on LAYER met5 = 0 um
total number of vias = 5422
up-via summary (total 5422):

-----------------------
 FR_MASTERSLICE       0
            li1     846
           met1    3832
           met2     724
           met3      20
           met4       0
-----------------------
                   5422


start 33rd optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 440.06 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 440.06 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 440.06 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 440.05 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 440.05 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 440.05 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 440.04 (MB), peak = 512.74 (MB)
total wire length = 1515723 um
total wire length on LAYER li1 = 12358 um
total wire length on LAYER met1 = 553894 um
total wire length on LAYER met2 = 930644 um
total wire length on LAYER met3 = 15592 um
total wire length on LAYER met4 = 3234 um
total wire length on LAYER met5 = 0 um
total number of vias = 5422
up-via summary (total 5422):

-----------------------
 FR_MASTERSLICE       0
            li1     846
           met1    3832
           met2     724
           met3      20
           met4       0
-----------------------
                   5422


start 41st optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 440.04 (MB), peak = 512.74 (MB)
total wire length = 1515723 um
total wire length on LAYER li1 = 12358 um
total wire length on LAYER met1 = 553894 um
total wire length on LAYER met2 = 930644 um
total wire length on LAYER met3 = 15592 um
total wire length on LAYER met4 = 3234 um
total wire length on LAYER met5 = 0 um
total number of vias = 5422
up-via summary (total 5422):

-----------------------
 FR_MASTERSLICE       0
            li1     846
           met1    3832
           met2     724
           met3      20
           met4       0
-----------------------
                   5422


start 49th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 440.04 (MB), peak = 512.74 (MB)
total wire length = 1515723 um
total wire length on LAYER li1 = 12358 um
total wire length on LAYER met1 = 553894 um
total wire length on LAYER met2 = 930644 um
total wire length on LAYER met3 = 15592 um
total wire length on LAYER met4 = 3234 um
total wire length on LAYER met5 = 0 um
total number of vias = 5422
up-via summary (total 5422):

-----------------------
 FR_MASTERSLICE       0
            li1     846
           met1    3832
           met2     724
           met3      20
           met4       0
-----------------------
                   5422


start 57th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 440.04 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 440.04 (MB), peak = 512.74 (MB)
total wire length = 1515723 um
total wire length on LAYER li1 = 12358 um
total wire length on LAYER met1 = 553894 um
total wire length on LAYER met2 = 930644 um
total wire length on LAYER met3 = 15592 um
total wire length on LAYER met4 = 3234 um
total wire length on LAYER met5 = 0 um
total number of vias = 5422
up-via summary (total 5422):

-----------------------
 FR_MASTERSLICE       0
            li1     846
           met1    3832
           met2     724
           met3      20
           met4       0
-----------------------
                   5422


complete detail routing
total wire length = 1515723 um
total wire length on LAYER li1 = 12358 um
total wire length on LAYER met1 = 553894 um
total wire length on LAYER met2 = 930644 um
total wire length on LAYER met3 = 15592 um
total wire length on LAYER met4 = 3234 um
total wire length on LAYER met5 = 0 um
total number of vias = 5422
up-via summary (total 5422):

-----------------------
 FR_MASTERSLICE       0
            li1     846
           met1    3832
           met2     724
           met3      20
           met4       0
-----------------------
                   5422

cpu time = 00:05:30, elapsed time = 00:01:53, memory = 440.04 (MB), peak = 512.74 (MB)

post processing ...

Runtime taken (hrt): 116.109