
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 428 cell types from liberty file.

2. Executing Verilog-2005 frontend: /project/openlane/mgmt_protect/../../verilog/rtl/mgmt_protect_hv.v
Parsing SystemVerilog input from `/project/openlane/mgmt_protect/../../verilog/rtl/mgmt_protect_hv.v' to AST representation.
Generating RTLIL representation for module `\mgmt_protect_hv'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /project/openlane/mgmt_protect/../../verilog/rtl/defines.v
Parsing SystemVerilog input from `/project/openlane/mgmt_protect/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /project/openlane/mgmt_protect/../../verilog/rtl/mgmt_protect.v
Parsing SystemVerilog input from `/project/openlane/mgmt_protect/../../verilog/rtl/mgmt_protect.v' to AST representation.
Generating RTLIL representation for module `\mgmt_protect'.
Successfully finished Verilog frontend.

5. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/mgmt_protect/runs/mgmt_protect/tmp/synthesis/hierarchy.dot'.
Dumping module mgmt_protect to page 1.

6. Executing HIERARCHY pass (managing design hierarchy).

6.1. Analyzing design hierarchy..
Top module:  \mgmt_protect

6.2. Analyzing design hierarchy..
Top module:  \mgmt_protect
Removed 0 unused modules.

7. Executing SYNTH pass.

7.1. Executing HIERARCHY pass (managing design hierarchy).

7.1.1. Analyzing design hierarchy..
Top module:  \mgmt_protect

7.1.2. Analyzing design hierarchy..
Top module:  \mgmt_protect
Removed 0 unused modules.

7.2. Executing PROC pass (convert processes to netlists).

7.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

7.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

7.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

7.2.4. Executing PROC_INIT pass (extract init attributes).

7.2.5. Executing PROC_ARST pass (detect async resets in processes).

7.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).

7.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

7.2.8. Executing PROC_DFF pass (convert process syncs to FFs).

7.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

7.3. Executing FLATTEN pass (flatten design).

7.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

7.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..
Removed 1 unused cells and 4 unused wires.
<suppressed ~5 debug messages>

7.6. Executing CHECK pass (checking for obvious problems).
checking module mgmt_protect..
found and reported 0 problems.

7.7. Executing OPT pass (performing simple optimizations).

7.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

7.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_protect'.
<suppressed ~957 debug messages>
Removed a total of 319 cells.

7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_protect..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_protect.
Performed a total of 0 changes.

7.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_protect'.
Removed a total of 0 cells.

7.7.6. Executing OPT_DFF pass (perform DFF optimizations).

7.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..
Removed 0 unused cells and 319 unused wires.
<suppressed ~1 debug messages>

7.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

7.7.9. Rerunning OPT passes. (Maybe there is more to do..)

7.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_protect..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

7.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_protect.
Performed a total of 0 changes.

7.7.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_protect'.
Removed a total of 0 cells.

7.7.13. Executing OPT_DFF pass (perform DFF optimizations).

7.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..

7.7.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

7.7.16. Finished OPT passes. (There is nothing left to do.)

7.8. Executing FSM pass (extract and optimize FSM).

7.8.1. Executing FSM_DETECT pass (finding FSMs in design).

7.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).

7.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).

7.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..

7.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).

7.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

7.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

7.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

7.9. Executing OPT pass (performing simple optimizations).

7.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

7.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_protect'.
Removed a total of 0 cells.

7.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_protect..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

7.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_protect.
Performed a total of 0 changes.

7.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_protect'.
Removed a total of 0 cells.

7.9.6. Executing OPT_DFF pass (perform DFF optimizations).

7.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..

7.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

7.9.9. Finished OPT passes. (There is nothing left to do.)

7.10. Executing WREDUCE pass (reducing word size of cells).

7.11. Executing PEEPOPT pass (run peephole optimizers).

7.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..

7.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module mgmt_protect:
  created 0 $alu and 0 $macc cells.

7.14. Executing SHARE pass (SAT-based resource sharing).

7.15. Executing OPT pass (performing simple optimizations).

7.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

7.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_protect'.
Removed a total of 0 cells.

7.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_protect..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

7.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_protect.
Performed a total of 0 changes.

7.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_protect'.
Removed a total of 0 cells.

7.15.6. Executing OPT_DFF pass (perform DFF optimizations).

7.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..

7.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

7.15.9. Finished OPT passes. (There is nothing left to do.)

7.16. Executing MEMORY pass.

7.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

7.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

7.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..

7.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

7.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..

7.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).

7.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..

7.18. Executing OPT pass (performing simple optimizations).

7.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

7.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_protect'.
Removed a total of 0 cells.

7.18.3. Executing OPT_DFF pass (perform DFF optimizations).

7.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..

7.18.5. Finished fast OPT passes.

7.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

7.20. Executing OPT pass (performing simple optimizations).

7.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

7.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_protect'.
Removed a total of 0 cells.

7.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_protect..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

7.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_protect.
Performed a total of 0 changes.

7.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_protect'.
Removed a total of 0 cells.

7.20.6. Executing OPT_SHARE pass.

7.20.7. Executing OPT_DFF pass (perform DFF optimizations).

7.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..

7.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

7.20.10. Finished OPT passes. (There is nothing left to do.)

7.21. Executing TECHMAP pass (map to technology primitives).

7.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

7.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
No more expansions possible.
<suppressed ~79 debug messages>

7.22. Executing OPT pass (performing simple optimizations).

7.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

7.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_protect'.
Removed a total of 0 cells.

7.22.3. Executing OPT_DFF pass (perform DFF optimizations).

7.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..

7.22.5. Finished fast OPT passes.

7.23. Executing ABC pass (technology mapping using ABC).

7.23.1. Extracting gate netlist of module `\mgmt_protect' to `<abc-temp-dir>/input.blif'..
Extracted 331 gates and 662 wires to a netlist network with 331 inputs and 331 outputs.

7.23.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + map 
ABC: + write_blif <abc-temp-dir>/output.blif 

7.23.1.2. Re-integrating ABC results.
ABC RESULTS:               NOT cells:      331
ABC RESULTS:        internal signals:        0
ABC RESULTS:           input signals:      331
ABC RESULTS:          output signals:      331
Removing temp directory.

7.24. Executing OPT pass (performing simple optimizations).

7.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

7.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_protect'.
Removed a total of 0 cells.

7.24.3. Executing OPT_DFF pass (perform DFF optimizations).

7.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..
Removed 0 unused cells and 343 unused wires.
<suppressed ~1 debug messages>

7.24.5. Finished fast OPT passes.

7.25. Executing HIERARCHY pass (managing design hierarchy).

7.25.1. Analyzing design hierarchy..
Top module:  \mgmt_protect

7.25.2. Analyzing design hierarchy..
Top module:  \mgmt_protect
Removed 0 unused modules.

7.26. Printing statistics.

=== mgmt_protect ===

   Number of wires:                363
   Number of wire bits:           1840
   Number of public wires:          33
   Number of public wire bits:    1510
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               1381
     $_NOT_                        331
     mgmt_protect_hv                 1
     sky130_fd_sc_hd__buf_8          4
     sky130_fd_sc_hd__conb_1       459
     sky130_fd_sc_hd__einvp_8      330
     sky130_fd_sc_hd__inv_8        128
     sky130_fd_sc_hd__nand2_4      128

7.27. Executing CHECK pass (checking for obvious problems).
checking module mgmt_protect..
found and reported 0 problems.

8. Executing SHARE pass (SAT-based resource sharing).

9. Executing OPT pass (performing simple optimizations).

9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_protect'.
Removed a total of 0 cells.

9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_protect..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_protect.
Performed a total of 0 changes.

9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_protect'.
Removed a total of 0 cells.

9.6. Executing OPT_DFF pass (perform DFF optimizations).

9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..

9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_protect.

9.9. Finished OPT passes. (There is nothing left to do.)

10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..

11. Printing statistics.

=== mgmt_protect ===

   Number of wires:                363
   Number of wire bits:           1840
   Number of public wires:          33
   Number of public wire bits:    1510
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               1381
     $_NOT_                        331
     mgmt_protect_hv                 1
     sky130_fd_sc_hd__buf_8          4
     sky130_fd_sc_hd__conb_1       459
     sky130_fd_sc_hd__einvp_8      330
     sky130_fd_sc_hd__inv_8        128
     sky130_fd_sc_hd__nand2_4      128

12. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

12.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\mgmt_protect':

13. Printing statistics.

=== mgmt_protect ===

   Number of wires:                363
   Number of wire bits:           1840
   Number of public wires:          33
   Number of public wire bits:    1510
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               1381
     $_NOT_                        331
     mgmt_protect_hv                 1
     sky130_fd_sc_hd__buf_8          4
     sky130_fd_sc_hd__conb_1       459
     sky130_fd_sc_hd__einvp_8      330
     sky130_fd_sc_hd__inv_8        128
     sky130_fd_sc_hd__nand2_4      128

14. Executing ABC pass (technology mapping using ABC).

14.1. Extracting gate netlist of module `\mgmt_protect' to `/tmp/yosys-abc-NlKUXu/input.blif'..
Extracted 331 gates and 662 wires to a netlist network with 331 inputs and 331 outputs.

14.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-NlKUXu/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-NlKUXu/abc.script".
ABC: 
ABC: + read_blif /tmp/yosys-abc-NlKUXu/input.blif 
ABC: + read_lib -w /project/openlane/mgmt_protect/runs/mgmt_protect/tmp/trimmed.lib 
ABC: Parsing finished successfully.  Parsing time =     0.02 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/mgmt_protect/runs/mgmt_protect/tmp/trimmed.lib" has 43 cells (6 skipped: 6 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.03 sec
ABC: Memory =    1.82 MB. Time =     0.03 sec
ABC: + read_constr -v /project/openlane/mgmt_protect/runs/mgmt_protect/tmp/synthesis/yosys.sdc 
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
ABC: Setting output load to be 17.650000.
ABC: + read_constr /project/openlane/mgmt_protect/runs/mgmt_protect/tmp/synthesis/yosys.sdc 
ABC: + fx 
ABC: The network is unchanged by fast extract.
ABC: + mfs 
ABC: + strash 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + retime -D -D 10000 -M 5 
ABC: + scleanup 
ABC: Error: The network is combinational.
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 
ABC: + retime -D -D 10000 
ABC: + buffer -N 5 -S 1000.0 
ABC: + upsize -D 10000 
ABC: Current delay (73.76 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed.
ABC: + dnsize -D 10000 
ABC: + stime -p 
ABC: WireLoad = "none"  Gates =    331 (100.0 %)   Cap = 11.1 ff (  0.0 %)   Area =     1242.44 (100.0 %)   Delay =    73.76 ps  (100.0 %)               
ABC: Path  0 --       1 : 0    1 pi                     A =   0.00  Df =   6.1   -4.2 ps  S =  17.8 ps  Cin =  0.0 ff  Cout =   4.6 ff  Cmax =   0.0 ff  G =    0  
ABC: Path  1 --     663 : 1    1 sky130_fd_sc_hd__inv_2 A =   3.75  Df =  73.8  -24.4 ps  S =  86.9 ps  Cin =  4.5 ff  Cout =  17.6 ff  Cmax = 331.4 ff  G =  395  
ABC: Start-point = pi0 (\la_oen_mprj [62]).  End-point = po0 ($abc$734$not$/project/openlane/mgmt_protect/../../verilog/rtl/mgmt_protect.v:292$204_Y[62]).
ABC: + print_stats -m 
ABC: netlist                       : i/o =  331/  331  lat =    0  nd =   331  edge =    331  area =1241.25  delay = 1.00  lev = 1
ABC: + write_blif /tmp/yosys-abc-NlKUXu/output.blif 

14.1.2. Re-integrating ABC results.
ABC RESULTS:   sky130_fd_sc_hd__inv_2 cells:      331
ABC RESULTS:        internal signals:        0
ABC RESULTS:           input signals:      331
ABC RESULTS:          output signals:      331
Removing temp directory.

15. Executing SETUNDEF pass (replace undef values with defined constants).

16. Executing HILOMAP pass (mapping to constant drivers).

17. Executing SPLITNETS pass (splitting up multi-bit signals).

18. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_protect..
Removed 0 unused cells and 662 unused wires.
<suppressed ~1 debug messages>

19. Executing INSBUF pass (insert buffer cells for connected wires).

20. Executing CHECK pass (checking for obvious problems).
checking module mgmt_protect..
found and reported 0 problems.

21. Printing statistics.

=== mgmt_protect ===

   Number of wires:                948
   Number of wire bits:           1840
   Number of public wires:         618
   Number of public wire bits:    1510
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               1381
     mgmt_protect_hv                 1
     sky130_fd_sc_hd__buf_8          4
     sky130_fd_sc_hd__conb_1       459
     sky130_fd_sc_hd__einvp_8      330
     sky130_fd_sc_hd__inv_2        331
     sky130_fd_sc_hd__inv_8        128
     sky130_fd_sc_hd__nand2_4      128

   Area for cell type \mgmt_protect_hv is unknown!

   Chip area for module '\mgmt_protect': 13340.294400

22. Executing Verilog backend.
Dumping module `\mgmt_protect'.

End of script. Logfile hash: c91096235d, CPU: user 2.45s system 0.05s, MEM: 62.02 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 24% 3x check (0 sec), 13% 2x write_verilog (0 sec), ...