
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 428 cell types from liberty file.

2. Executing Verilog-2005 frontend: /project/openlane/digital_pll/../../verilog/rtl/digital_pll.v
Parsing SystemVerilog input from `/project/openlane/digital_pll/../../verilog/rtl/digital_pll.v' to AST representation.
Generating RTLIL representation for module `\digital_pll_controller'.
Generating RTLIL representation for module `\delay_stage'.
Generating RTLIL representation for module `\start_stage'.
Generating RTLIL representation for module `\ring_osc2x13'.
Generating RTLIL representation for module `\digital_pll'.
Successfully finished Verilog frontend.

3. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/digital_pll/runs/digital_pll/tmp/synthesis/hierarchy.dot'.
Dumping module digital_pll to page 1.

4. Executing HIERARCHY pass (managing design hierarchy).

4.1. Analyzing design hierarchy..
Top module:  \digital_pll
Used module:     \digital_pll_controller
Used module:     \ring_osc2x13
Used module:         \delay_stage
Used module:         \start_stage

4.2. Analyzing design hierarchy..
Top module:  \digital_pll
Used module:     \digital_pll_controller
Used module:     \ring_osc2x13
Used module:         \delay_stage
Used module:         \start_stage
Removed 0 unused modules.

5. Executing SYNTH pass.

5.1. Executing HIERARCHY pass (managing design hierarchy).

5.1.1. Analyzing design hierarchy..
Top module:  \digital_pll
Used module:     \digital_pll_controller
Used module:     \ring_osc2x13
Used module:         \delay_stage
Used module:         \start_stage

5.1.2. Analyzing design hierarchy..
Top module:  \digital_pll
Used module:     \digital_pll_controller
Used module:     \ring_osc2x13
Used module:         \delay_stage
Used module:         \start_stage
Removed 0 unused modules.

5.2. Executing PROC pass (convert processes to netlists).

5.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

5.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 3 switch rules as full_case in process $proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54 in module digital_pll_controller.
Removed a total of 0 dead cases.

5.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 0 assignments to connections.

5.2.4. Executing PROC_INIT pass (extract init attributes).

5.2.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \reset in `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.

5.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
     1/5: $0\oscbuf[2:0]
     2/5: $0\tval[6:0]
     3/5: $0\count1[4:0]
     4/5: $0\count0[4:0]
     5/5: $0\prep[2:0]

5.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

5.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\digital_pll_controller.\oscbuf' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$98' with positive edge clock and positive level reset.
Creating register for signal `\digital_pll_controller.\prep' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$99' with positive edge clock and positive level reset.
Creating register for signal `\digital_pll_controller.\count0' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$100' with positive edge clock and positive level reset.
Creating register for signal `\digital_pll_controller.\count1' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$101' with positive edge clock and positive level reset.
Creating register for signal `\digital_pll_controller.\tval' using process `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
  created $adff cell `$procdff$102' with positive edge clock and positive level reset.

5.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 7 empty switches in `\digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
Removing empty process `digital_pll_controller.$proc$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:85$54'.
Cleaned up 7 empty switches.

5.3. Executing FLATTEN pass (flatten design).
Deleting now unused module ring_osc2x13.
Deleting now unused module start_stage.
Deleting now unused module delay_stage.
Deleting now unused module digital_pll_controller.
<suppressed ~15 debug messages>

5.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.
<suppressed ~6 debug messages>

5.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 2 unused cells and 23 unused wires.
<suppressed ~3 debug messages>

5.6. Executing CHECK pass (checking for obvious problems).
checking module digital_pll..
Warning: multiple conflicting drivers for digital_pll.\ringosc.iss.d1:
    port Z[0] of cell ringosc.iss.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.in:
    port Z[0] of cell ringosc.iss.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb0 (sky130_fd_sc_hd__einvn_8)
    port Z[0] of cell ringosc.iss.reseten0 (sky130_fd_sc_hd__einvp_1)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[9].id.d1:
    port Z[0] of cell ringosc.dstage[9].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.in:
    port Z[0] of cell ringosc.dstage[9].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.d1:
    port Z[0] of cell ringosc.dstage[8].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.out:
    port Z[0] of cell ringosc.dstage[8].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.d1:
    port Z[0] of cell ringosc.dstage[7].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.out:
    port Z[0] of cell ringosc.dstage[7].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.d1:
    port Z[0] of cell ringosc.dstage[6].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.out:
    port Z[0] of cell ringosc.dstage[6].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.d1:
    port Z[0] of cell ringosc.dstage[5].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.out:
    port Z[0] of cell ringosc.dstage[5].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.d1:
    port Z[0] of cell ringosc.dstage[4].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.out:
    port Z[0] of cell ringosc.dstage[4].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.d1:
    port Z[0] of cell ringosc.dstage[3].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.out:
    port Z[0] of cell ringosc.dstage[3].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.d1:
    port Z[0] of cell ringosc.dstage[2].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.out:
    port Z[0] of cell ringosc.dstage[2].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.d1:
    port Z[0] of cell ringosc.dstage[1].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.out:
    port Z[0] of cell ringosc.dstage[1].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.d1:
    port Z[0] of cell ringosc.dstage[11].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.out:
    port Z[0] of cell ringosc.dstage[11].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.d1:
    port Z[0] of cell ringosc.dstage[10].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.out:
    port Z[0] of cell ringosc.dstage[10].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.d1:
    port Z[0] of cell ringosc.dstage[0].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.out:
    port Z[0] of cell ringosc.dstage[0].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
found and reported 26 problems.

5.7. Executing OPT pass (performing simple optimizations).

5.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

5.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

5.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>

5.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

5.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

5.7.6. Executing OPT_DFF pass (perform DFF optimizations).

5.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

5.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

5.7.9. Finished OPT passes. (There is nothing left to do.)

5.8. Executing FSM pass (extract and optimize FSM).

5.8.1. Executing FSM_DETECT pass (finding FSMs in design).

5.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).

5.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).

5.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

5.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).

5.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

5.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

5.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

5.9. Executing OPT pass (performing simple optimizations).

5.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

5.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

5.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>

5.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

5.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

5.9.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\pll_control.$procdff$99 ($adff) from module digital_pll (D = { \pll_control.prep [1:0] 1'1 }, Q = \pll_control.prep).
Adding EN signal on $flatten\pll_control.$procdff$102 ($adff) from module digital_pll (D = $flatten\pll_control.$procmux$81_Y, Q = \pll_control.tval).
Adding EN signal on $flatten\pll_control.$procdff$101 ($adff) from module digital_pll (D = \pll_control.count0, Q = \pll_control.count1).
Adding EN signal on $flatten\pll_control.$procdff$100 ($adff) from module digital_pll (D = $flatten\pll_control.$0\count0[4:0], Q = \pll_control.count0).

5.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 4 unused cells and 4 unused wires.
<suppressed ~5 debug messages>

5.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.
<suppressed ~2 debug messages>

5.9.9. Rerunning OPT passes. (Maybe there is more to do..)

5.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>

5.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

5.9.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

5.9.13. Executing OPT_DFF pass (perform DFF optimizations).

5.9.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

5.9.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

5.9.16. Finished OPT passes. (There is nothing left to do.)

5.10. Executing WREDUCE pass (reducing word size of cells).
Removed top 1 bits (of 3) from port B of cell digital_pll.$auto$opt_dff.cc:218:make_patterns_logic$105 ($ne).
Removed cell digital_pll.$flatten\pll_control.$procmux$90 ($mux).
Removed cell digital_pll.$flatten\pll_control.$procmux$79 ($mux).
Removed cell digital_pll.$flatten\pll_control.$procmux$76 ($mux).
Removed cell digital_pll.$flatten\pll_control.$procmux$74 ($mux).
Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65 ($add).
Removed top 27 bits (of 32) from port Y of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65 ($add).
Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63 ($sub).
Removed top 25 bits (of 32) from port Y of cell digital_pll.$flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63 ($sub).
Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:107$62 ($gt).
Removed top 31 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60 ($add).
Removed top 25 bits (of 32) from port Y of cell digital_pll.$flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60 ($add).
Removed top 25 bits (of 32) from port B of cell digital_pll.$flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:103$59 ($lt).
Removed top 5 bits (of 26) from mux cell digital_pll.$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:82$28 ($mux).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$17 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$16 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$15 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$14 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$13 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$12 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$11 ($eq).
Removed top 1 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$10 ($eq).
Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$9 ($eq).
Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$8 ($eq).
Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$7 ($eq).
Removed top 2 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$6 ($eq).
Removed top 3 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$5 ($eq).
Removed top 3 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$4 ($eq).
Removed top 4 bits (of 5) from port B of cell digital_pll.$flatten\pll_control.$eq$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$3 ($eq).
Removed top 5 bits (of 26) from wire digital_pll.$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:82$28_Y.

5.11. Executing PEEPOPT pass (run peephole optimizers).

5.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 5 unused wires.
<suppressed ~1 debug messages>

5.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module digital_pll:
  creating $macc model for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60 ($add).
  creating $macc model for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65 ($add).
  creating $macc model for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:52$1 ($add).
  creating $macc model for $flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63 ($sub).
  creating $alu model for $macc $flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63.
  creating $alu model for $macc $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:52$1.
  creating $alu model for $macc $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65.
  creating $alu model for $macc $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60.
  creating $alu model for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:102$58 ($gt): new $alu
  creating $alu model for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:107$62 ($gt): new $alu
  creating $alu model for $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:103$59 ($lt): new $alu
  creating $alu model for $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:106$61 ($lt): merged with $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:102$58.
  creating $alu cell for $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:103$59: $auto$alumacc.cc:485:replace_alu$121
  creating $alu cell for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:107$62: $auto$alumacc.cc:485:replace_alu$126
  creating $alu cell for $flatten\pll_control.$gt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:102$58, $flatten\pll_control.$lt$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:106$61: $auto$alumacc.cc:485:replace_alu$131
  creating $alu cell for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:104$60: $auto$alumacc.cc:485:replace_alu$142
  creating $alu cell for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:114$65: $auto$alumacc.cc:485:replace_alu$145
  creating $alu cell for $flatten\pll_control.$add$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:52$1: $auto$alumacc.cc:485:replace_alu$148
  creating $alu cell for $flatten\pll_control.$sub$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:108$63: $auto$alumacc.cc:485:replace_alu$151
  created 7 $alu and 0 $macc cells.

5.14. Executing SHARE pass (SAT-based resource sharing).

5.15. Executing OPT pass (performing simple optimizations).

5.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.
<suppressed ~1 debug messages>

5.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

5.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>

5.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

5.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

5.15.6. Executing OPT_DFF pass (perform DFF optimizations).

5.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 4 unused wires.
<suppressed ~1 debug messages>

5.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

5.15.9. Rerunning OPT passes. (Maybe there is more to do..)

5.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>

5.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

5.15.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

5.15.13. Executing OPT_DFF pass (perform DFF optimizations).

5.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

5.15.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

5.15.16. Finished OPT passes. (There is nothing left to do.)

5.16. Executing MEMORY pass.

5.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

5.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

5.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

5.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

5.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

5.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).

5.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

5.18. Executing OPT pass (performing simple optimizations).

5.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.
<suppressed ~1 debug messages>

5.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

5.18.3. Executing OPT_DFF pass (perform DFF optimizations).

5.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

5.18.5. Finished fast OPT passes.

5.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

5.20. Executing OPT pass (performing simple optimizations).

5.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

5.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

5.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~3 debug messages>

5.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29:
      Old ports: A={ 5'11111 $auto$wreduce.cc:454:run$117 [20:0] }, B=26'11111011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y
      New ports: A=$auto$wreduce.cc:454:run$117 [20:0], B=21'011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0]
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [25:21] = 5'11111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:82$28:
      Old ports: A=21'111111111111111111111, B=21'011111111111111111111, Y=$auto$wreduce.cc:454:run$117 [20:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$117 [20]
      New connections: $auto$wreduce.cc:454:run$117 [19:0] = 20'11111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y, B=26'10111011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y
      New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0] }, B=22'0011111011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [23:21] } = 4'1111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29:
      Old ports: A=$auto$wreduce.cc:454:run$117 [20:0], B=21'011111011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0]
      New ports: A={ $auto$wreduce.cc:454:run$117 [20] 1'1 }, B=2'00, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [19:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [13:0] } = 19'1111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y, B=26'10111011011011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] }, B=22'0011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [23:21] } = 4'1111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30:
      Old ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20:0] }, B=22'0011111011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] }
      New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:81$29_Y [14] }, B=3'000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [19:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [13:0] } = 19'1111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y, B=26'10101011011011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] }, B=23'00011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [21] } = 3'111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20:0] }, B=22'0011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [20] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:80$30_Y [14] }, B=4'0000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [19:18] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [16:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [13:0] } = 18'111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y, B=26'10101011010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] }, B=23'00011010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [21] } = 3'111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20:0] }, B=23'00011011011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:79$31_Y [14] }, B=5'00000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [19:18] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [16:15] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [13:0] } = 18'111111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y, B=26'10101010010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] }, B=23'00010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [25] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [21] } = 3'111
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20:0] }, B=23'00011010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [17] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:78$32_Y [14] }, B=6'000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [15:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [19:18] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [13:0] } = 17'11111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y, B=26'00101010010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y
      New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] }, B=24'000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [23] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [21] } = 2'11
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20:0] }, B=23'00010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [20] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:77$33_Y [15:14] }, B=7'0000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [15:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [13:0] } = 16'1111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y, B=26'00100010010011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] }, B=25'0000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] }
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [23] = 1'1
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35:
      Old ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20:0] }, B=24'000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] }
      New ports: A={ 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:76$34_Y [15:14] }, B=8'00000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [15:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [13:0] } = 16'1111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y, B=26'00100010000011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] }, B=25'0000010000011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:0] }
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [23] = 1'1
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20:0] }, B=25'0000010010011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [22] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:75$35_Y [15:14] }, B=9'000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [18:17] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [15:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [16] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [13:0] } = 16'1111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37:
      Old ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:0] }, B=25'0000010000011111111111111, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:0] }
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [18:17] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:74$36_Y [15:14] }, B=10'0000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [18:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [13:0] } = 15'111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y, B=26'00000010000011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [25:24] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [22:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:73$37_Y [18:14] }, B=11'00000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [25:20] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [18:14] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [19] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [13:0] } = 15'111111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y, B=26'00000000000011111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [25:20] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:72$38_Y [18:14] }, B=12'000000000000, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y [25:14]
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y [13:0] = 14'11111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y, B=26'00000000000001111111111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:71$39_Y [25:14] 1'1 }, B=13'0000000000000, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y [25:13]
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y [12:0] = 13'1111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y, B=26'00000000000001111101111111, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:70$40_Y [25:13] 1'1 }, B=14'00000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [7] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [12:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [6:0] } = 12'111111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y, B=26'00000000000001111101111101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:69$41_Y [7] 1'1 }, B=15'000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [12:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [6:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [0] } = 11'11111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y, B=26'00000000000001011101111101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [25:13] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:68$42_Y [1] }, B=16'0000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [10:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [6:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [0] } = 10'1111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y, B=26'00000000000001011101101101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [7] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:67$43_Y [1] }, B=17'00000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [10:8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [6:5] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [3:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [0] } = 9'111111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y, B=26'00000000000001010101101101, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [11] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:66$44_Y [1] }, B=18'000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [6:5] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [3:2] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [0] } = 8'11111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y, B=26'00000000000001010101101001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [4] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:65$45_Y [1] }, B=19'0000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [2:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [6:5] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [0] } = 7'1111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y, B=26'00000000000001010101001001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [7] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:64$46_Y [2:1] }, B=20'00000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [25:13] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [2:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [12] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [0] } = 6'111111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y, B=26'00000000000000010101001001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [25:13] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:63$47_Y [2:1] }, B=21'000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [9] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [2:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [8] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [0] } = 5'11111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y, B=26'00000000000000010001001001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [9] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:62$48_Y [2:1] }, B=22'0000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [5:4] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [2:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [3] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [0] } = 4'1111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y, B=26'00000000000000010001000001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [5:4] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:61$49_Y [2:1] }, B=23'00000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [25:11] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [5:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [10] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [0] } = 3'111
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y, B=26'00000000000000000001000001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [25:11] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [9:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:60$50_Y [5:1] }, B=24'000000000000000000000000, Y={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [25:7] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [5:1] }
      New connections: { $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [6] $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [0] } = 2'11
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52:
      Old ports: A=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y, B=26'00000000000000000000000001, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52_Y
      New ports: A={ $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [25:7] 1'1 $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:59$51_Y [5:1] }, B=25'0000000000000000000000000, Y=$flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52_Y [25:1]
      New connections: $flatten\pll_control.$ternary$/project/openlane/digital_pll/../../verilog/rtl/digital_pll_controller.v:58$52_Y [0] = 1'1
  Optimizing cells in module \digital_pll.
Performed a total of 34 changes.

5.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

5.20.6. Executing OPT_SHARE pass.
    Found cells that share an operand and can be merged by moving the $mux $flatten\pll_control.$procmux$81 in front of them:
        $auto$alumacc.cc:485:replace_alu$151
        $auto$alumacc.cc:485:replace_alu$142

5.20.7. Executing OPT_DFF pass (perform DFF optimizations).

5.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 6 unused wires.
<suppressed ~1 debug messages>

5.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.
<suppressed ~3 debug messages>

5.20.10. Rerunning OPT passes. (Maybe there is more to do..)

5.20.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~3 debug messages>

5.20.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
    Consolidated identical input bits for $mux cell $auto$opt_share.cc:241:merge_operators$157:
      Old ports: A=$auto$rtlil.cc:2123:Neg$155, B=7'0000001, Y=$auto$rtlil.cc:2218:Mux$158
      New ports: A=1'1, B=1'0, Y=$auto$rtlil.cc:2218:Mux$158 [1]
      New connections: { $auto$rtlil.cc:2218:Mux$158 [6:2] $auto$rtlil.cc:2218:Mux$158 [0] } = { $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] $auto$rtlil.cc:2218:Mux$158 [1] 1'1 }
  Optimizing cells in module \digital_pll.
Performed a total of 1 changes.

5.20.13. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

5.20.14. Executing OPT_SHARE pass.

5.20.15. Executing OPT_DFF pass (perform DFF optimizations).

5.20.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

5.20.17. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.
<suppressed ~1 debug messages>

5.20.18. Rerunning OPT passes. (Maybe there is more to do..)

5.20.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~2 debug messages>

5.20.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

5.20.21. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

5.20.22. Executing OPT_SHARE pass.

5.20.23. Executing OPT_DFF pass (perform DFF optimizations).

5.20.24. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

5.20.25. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

5.20.26. Rerunning OPT passes. (Maybe there is more to do..)

5.20.27. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~2 debug messages>

5.20.28. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

5.20.29. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

5.20.30. Executing OPT_SHARE pass.

5.20.31. Executing OPT_DFF pass (perform DFF optimizations).

5.20.32. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

5.20.33. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

5.20.34. Finished OPT passes. (There is nothing left to do.)

5.21. Executing TECHMAP pass (map to technology primitives).

5.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

5.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu.
Using extmapper simplemap for cells of type $adffe.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $adff.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=6\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=7\Y_WIDTH=7 for cells of type $alu.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $and.
Using template $paramod\_90_lcu\WIDTH=7 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=6 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=5 for cells of type $lcu.
No more expansions possible.
<suppressed ~693 debug messages>

5.22. Executing OPT pass (performing simple optimizations).

5.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.
<suppressed ~670 debug messages>

5.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
<suppressed ~363 debug messages>
Removed a total of 121 cells.

5.22.3. Executing OPT_DFF pass (perform DFF optimizations).

5.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 61 unused cells and 376 unused wires.
<suppressed ~62 debug messages>

5.22.5. Finished fast OPT passes.

5.23. Executing ABC pass (technology mapping using ABC).

5.23.1. Extracting gate netlist of module `\digital_pll' to `<abc-temp-dir>/input.blif'..
Extracted 556 gates and 614 wires to a netlist network with 56 inputs and 43 outputs.

5.23.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + map 
ABC: + write_blif <abc-temp-dir>/output.blif 

5.23.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:        4
ABC RESULTS:            ANDNOT cells:       89
ABC RESULTS:               MUX cells:       27
ABC RESULTS:              NAND cells:       17
ABC RESULTS:               NOR cells:       11
ABC RESULTS:               NOT cells:        6
ABC RESULTS:                OR cells:      331
ABC RESULTS:             ORNOT cells:       10
ABC RESULTS:              XNOR cells:       12
ABC RESULTS:               XOR cells:       19
ABC RESULTS:        internal signals:      515
ABC RESULTS:           input signals:       56
ABC RESULTS:          output signals:       43
Removing temp directory.

5.24. Executing OPT pass (performing simple optimizations).

5.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.
<suppressed ~8 debug messages>

5.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

5.24.3. Executing OPT_DFF pass (perform DFF optimizations).

5.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 242 unused wires.
<suppressed ~2 debug messages>

5.24.5. Finished fast OPT passes.

5.25. Executing HIERARCHY pass (managing design hierarchy).

5.25.1. Analyzing design hierarchy..
Top module:  \digital_pll

5.25.2. Analyzing design hierarchy..
Top module:  \digital_pll
Removed 0 unused modules.

5.26. Printing statistics.

=== digital_pll ===

   Number of wires:                613
   Number of wire bits:            808
   Number of public wires:         120
   Number of public wire bits:     303
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                646
     $_ANDNOT_                      89
     $_AND_                          4
     $_DFFE_PP0N_                    8
     $_DFFE_PP0P_                   12
     $_DFF_PP0_                      3
     $_MUX_                         27
     $_NAND_                        17
     $_NOR_                         11
     $_NOT_                          6
     $_ORNOT_                       10
     $_OR_                         331
     $_XNOR_                        12
     $_XOR_                         19
     sky130_fd_sc_hd__clkbuf_1      13
     sky130_fd_sc_hd__clkbuf_2      12
     sky130_fd_sc_hd__clkinv_1      13
     sky130_fd_sc_hd__clkinv_2       2
     sky130_fd_sc_hd__clkinv_8       2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__einvn_4       13
     sky130_fd_sc_hd__einvn_8       13
     sky130_fd_sc_hd__einvp_1        1
     sky130_fd_sc_hd__einvp_2       26
     sky130_fd_sc_hd__or2_2          1

5.27. Executing CHECK pass (checking for obvious problems).
checking module digital_pll..
Warning: multiple conflicting drivers for digital_pll.\ringosc.iss.d1:
    port Z[0] of cell ringosc.iss.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.in:
    port Z[0] of cell ringosc.iss.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb0 (sky130_fd_sc_hd__einvn_8)
    port Z[0] of cell ringosc.iss.reseten0 (sky130_fd_sc_hd__einvp_1)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[9].id.d1:
    port Z[0] of cell ringosc.dstage[9].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.in:
    port Z[0] of cell ringosc.dstage[9].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.d1:
    port Z[0] of cell ringosc.dstage[8].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.out:
    port Z[0] of cell ringosc.dstage[8].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.d1:
    port Z[0] of cell ringosc.dstage[7].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.out:
    port Z[0] of cell ringosc.dstage[7].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.d1:
    port Z[0] of cell ringosc.dstage[6].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.out:
    port Z[0] of cell ringosc.dstage[6].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.d1:
    port Z[0] of cell ringosc.dstage[5].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.out:
    port Z[0] of cell ringosc.dstage[5].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.d1:
    port Z[0] of cell ringosc.dstage[4].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.out:
    port Z[0] of cell ringosc.dstage[4].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.d1:
    port Z[0] of cell ringosc.dstage[3].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.out:
    port Z[0] of cell ringosc.dstage[3].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.d1:
    port Z[0] of cell ringosc.dstage[2].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.out:
    port Z[0] of cell ringosc.dstage[2].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.d1:
    port Z[0] of cell ringosc.dstage[1].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.out:
    port Z[0] of cell ringosc.dstage[1].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.d1:
    port Z[0] of cell ringosc.dstage[11].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.out:
    port Z[0] of cell ringosc.dstage[11].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.d1:
    port Z[0] of cell ringosc.dstage[10].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.out:
    port Z[0] of cell ringosc.dstage[10].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.d1:
    port Z[0] of cell ringosc.dstage[0].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.out:
    port Z[0] of cell ringosc.dstage[0].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
found and reported 26 problems.

6. Executing SHARE pass (SAT-based resource sharing).

7. Executing OPT pass (performing simple optimizations).

7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \digital_pll..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \digital_pll.
Performed a total of 0 changes.

7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\digital_pll'.
Removed a total of 0 cells.

7.6. Executing OPT_DFF pass (perform DFF optimizations).

7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..

7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module digital_pll.

7.9. Finished OPT passes. (There is nothing left to do.)

8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 24 unused wires.
<suppressed ~24 debug messages>

9. Printing statistics.

=== digital_pll ===

   Number of wires:                589
   Number of wire bits:            667
   Number of public wires:          96
   Number of public wire bits:     162
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                646
     $_ANDNOT_                      89
     $_AND_                          4
     $_DFFE_PP0N_                    8
     $_DFFE_PP0P_                   12
     $_DFF_PP0_                      3
     $_MUX_                         27
     $_NAND_                        17
     $_NOR_                         11
     $_NOT_                          6
     $_ORNOT_                       10
     $_OR_                         331
     $_XNOR_                        12
     $_XOR_                         19
     sky130_fd_sc_hd__clkbuf_1      13
     sky130_fd_sc_hd__clkbuf_2      12
     sky130_fd_sc_hd__clkinv_1      13
     sky130_fd_sc_hd__clkinv_2       2
     sky130_fd_sc_hd__clkinv_8       2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__einvn_4       13
     sky130_fd_sc_hd__einvn_8       13
     sky130_fd_sc_hd__einvp_1        1
     sky130_fd_sc_hd__einvp_2       26
     sky130_fd_sc_hd__or2_2          1

10. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

10.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\digital_pll':
  mapped 23 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_4 cells.

11. Printing statistics.

=== digital_pll ===

   Number of wires:                632
   Number of wire bits:            710
   Number of public wires:          96
   Number of public wire bits:     162
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                689
     $_ANDNOT_                      89
     $_AND_                          4
     $_MUX_                         47
     $_NAND_                        17
     $_NOR_                         11
     $_NOT_                         29
     $_ORNOT_                       10
     $_OR_                         331
     $_XNOR_                        12
     $_XOR_                         19
     sky130_fd_sc_hd__clkbuf_1      13
     sky130_fd_sc_hd__clkbuf_2      12
     sky130_fd_sc_hd__clkinv_1      13
     sky130_fd_sc_hd__clkinv_2       2
     sky130_fd_sc_hd__clkinv_8       2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__dfrtp_4       23
     sky130_fd_sc_hd__einvn_4       13
     sky130_fd_sc_hd__einvn_8       13
     sky130_fd_sc_hd__einvp_1        1
     sky130_fd_sc_hd__einvp_2       26
     sky130_fd_sc_hd__or2_2          1

12. Executing ABC pass (technology mapping using ABC).

12.1. Extracting gate netlist of module `\digital_pll' to `/tmp/yosys-abc-mZe6RK/input.blif'..
Extracted 569 gates and 626 wires to a netlist network with 56 inputs and 70 outputs.

12.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-mZe6RK/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-mZe6RK/abc.script".
ABC: 
ABC: + read_blif /tmp/yosys-abc-mZe6RK/input.blif 
ABC: + read_lib -w /project/openlane/digital_pll/runs/digital_pll/tmp/trimmed.lib 
ABC: Parsing finished successfully.  Parsing time =     0.03 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/digital_pll/runs/digital_pll/tmp/trimmed.lib" has 43 cells (6 skipped: 6 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.04 sec
ABC: Memory =    1.82 MB. Time =     0.04 sec
ABC: + read_constr -v /project/openlane/digital_pll/runs/digital_pll/tmp/synthesis/yosys.sdc 
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
ABC: Setting output load to be 17.650000.
ABC: + read_constr /project/openlane/digital_pll/runs/digital_pll/tmp/synthesis/yosys.sdc 
ABC: + fx 
ABC: + mfs 
ABC: + strash 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + retime -D -D 10000 -M 5 
ABC: + scleanup 
ABC: Error: The network is combinational.
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 
ABC: + retime -D -D 10000 
ABC: + 
ABC: + stime -p 
ABC: WireLoad = "none"  Gates =    286 ( 28.0 %)   Cap = 11.4 ff (  0.0 %)   Area =     3025.40 (100.0 %)   Delay =  3613.31 ps  ( 10.5 %)               
ABC: Path  0 --       7 : 0    3 pi                        A =   0.00  Df =  12.1   -8.1 ps  S =  25.2 ps  Cin =  0.0 ff  Cout =   9.7 ff  Cmax =   0.0 ff  G =    0  
ABC: Path  1 --     133 : 1    5 sky130_fd_sc_hd__inv_2    A =   3.75  Df =  93.4  -30.5 ps  S = 110.2 ps  Cin =  4.5 ff  Cout =  22.9 ff  Cmax = 331.4 ff  G =  488  
ABC: Path  2 --     178 : 4    3 sky130_fd_sc_hd__o22a_4   A =  17.52  Df = 551.4 -109.6 ps  S =  52.7 ps  Cin =  4.6 ff  Cout =  11.7 ff  Cmax = 530.1 ff  G =  243  
ABC: Path  3 --     179 : 4    3 sky130_fd_sc_hd__o22a_4   A =  17.52  Df = 748.7 -165.3 ps  S =  58.3 ps  Cin =  4.6 ff  Cout =  13.8 ff  Cmax = 530.1 ff  G =  286  
ABC: Path  4 --     180 : 4    2 sky130_fd_sc_hd__a2bb2o_4 A =  20.02  Df = 960.4   -4.5 ps  S =  52.7 ps  Cin =  4.6 ff  Cout =  11.6 ff  Cmax = 502.6 ff  G =  238  
ABC: Path  5 --     186 : 2    2 sky130_fd_sc_hd__or2_4    A =   8.76  Df =1183.4 -121.6 ps  S =  47.4 ps  Cin =  2.4 ff  Cout =   5.1 ff  Cmax = 514.5 ff  G =  204  
ABC: Path  6 --     188 : 3    2 sky130_fd_sc_hd__and3_4   A =  11.26  Df =1356.4  -20.0 ps  S =  59.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 532.8 ff  G =  381  
ABC: Path  7 --     195 : 4    1 sky130_fd_sc_hd__a211o_4  A =  17.52  Df =1657.7 -181.0 ps  S =  49.1 ps  Cin =  4.6 ff  Cout =   4.6 ff  Cmax = 559.4 ff  G =   96  
ABC: Path  8 --     196 : 1    1 sky130_fd_sc_hd__inv_2    A =   3.75  Df =1698.7 -200.1 ps  S =  23.4 ps  Cin =  4.5 ff  Cout =   2.5 ff  Cmax = 331.4 ff  G =   54  
ABC: Path  9 --     199 : 2   10 sky130_fd_sc_hd__or2_4    A =   8.76  Df =1895.4  -95.7 ps  S = 162.3 ps  Cin =  2.4 ff  Cout =  51.0 ff  Cmax = 514.5 ff  G = 2003  
ABC: Path 10 --     220 : 3    3 sky130_fd_sc_hd__o21ai_4  A =  16.27  Df =2367.6  -91.1 ps  S = 170.6 ps  Cin =  8.8 ff  Cout =  16.1 ff  Cmax = 224.3 ff  G =  175  
ABC: Path 11 --     228 : 5    3 sky130_fd_sc_hd__a32o_4   A =  21.27  Df =2703.9 -179.0 ps  S =  79.2 ps  Cin =  4.3 ff  Cout =  16.1 ff  Cmax = 536.5 ff  G =  355  
ABC: Path 12 --     232 : 5    2 sky130_fd_sc_hd__a32o_4   A =  21.27  Df =3031.1 -291.6 ps  S =  66.1 ps  Cin =  4.3 ff  Cout =  11.3 ff  Cmax = 536.5 ff  G =  252  
ABC: Path 13 --     234 : 2    1 sky130_fd_sc_hd__or2_4    A =   8.76  Df =3275.9 -423.1 ps  S =  46.3 ps  Cin =  2.4 ff  Cout =   4.7 ff  Cmax = 514.5 ff  G =  186  
ABC: Path 14 --     236 : 5    1 sky130_fd_sc_hd__a32o_4   A =  21.27  Df =3613.3 -310.4 ps  S =  83.1 ps  Cin =  4.3 ff  Cout =  17.6 ff  Cmax = 536.5 ff  G =  407  
ABC: Start-point = pi6 (\pll_control.count0 [1]).  End-point = po16 ($auto$rtlil.cc:2290:MuxGate$2331).
ABC: + print_stats -m 
ABC: netlist                       : i/o =   56/   70  lat =    0  nd =   286  edge =    733  area =3025.26  delay =20.00  lev = 20
ABC: + write_blif /tmp/yosys-abc-mZe6RK/output.blif 

12.1.2. Re-integrating ABC results.
ABC RESULTS:   sky130_fd_sc_hd__a211o_4 cells:        7
ABC RESULTS:   sky130_fd_sc_hd__a21bo_4 cells:       16
ABC RESULTS:   sky130_fd_sc_hd__a21o_4 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__a22oi_4 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__a2bb2o_4 cells:       14
ABC RESULTS:   sky130_fd_sc_hd__a32o_4 cells:        9
ABC RESULTS:   sky130_fd_sc_hd__and2_4 cells:       11
ABC RESULTS:   sky130_fd_sc_hd__and3_4 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__and4_4 cells:       22
ABC RESULTS:   sky130_fd_sc_hd__buf_2 cells:       22
ABC RESULTS:   sky130_fd_sc_hd__inv_2 cells:       58
ABC RESULTS:   sky130_fd_sc_hd__nand2_4 cells:        8
ABC RESULTS:   sky130_fd_sc_hd__nor2_4 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__o21a_4 cells:        6
ABC RESULTS:   sky130_fd_sc_hd__o21ai_4 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__o22a_4 cells:       18
ABC RESULTS:   sky130_fd_sc_hd__o32a_4 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__or2_4 cells:       50
ABC RESULTS:   sky130_fd_sc_hd__or3_4 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__or4_4 cells:       25
ABC RESULTS:        internal signals:      500
ABC RESULTS:           input signals:       56
ABC RESULTS:          output signals:       70
Removing temp directory.

13. Executing SETUNDEF pass (replace undef values with defined constants).

14. Executing HILOMAP pass (mapping to constant drivers).

15. Executing SPLITNETS pass (splitting up multi-bit signals).

16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \digital_pll..
Removed 0 unused cells and 637 unused wires.
<suppressed ~7 debug messages>

17. Executing INSBUF pass (insert buffer cells for connected wires).
Added digital_pll.$auto$insbuf.cc:79:execute$2653: \pll_control.clock -> \clockp [0]

18. Executing CHECK pass (checking for obvious problems).
checking module digital_pll..
Warning: multiple conflicting drivers for digital_pll.\ringosc.iss.d1:
    port Z[0] of cell ringosc.iss.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.in:
    port Z[0] of cell ringosc.iss.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.iss.delayenb0 (sky130_fd_sc_hd__einvn_8)
    port Z[0] of cell ringosc.iss.reseten0 (sky130_fd_sc_hd__einvp_1)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[9].id.d1:
    port Z[0] of cell ringosc.dstage[9].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.in:
    port Z[0] of cell ringosc.dstage[9].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[9].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.d1:
    port Z[0] of cell ringosc.dstage[8].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[8].id.out:
    port Z[0] of cell ringosc.dstage[8].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[8].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.d1:
    port Z[0] of cell ringosc.dstage[7].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[7].id.out:
    port Z[0] of cell ringosc.dstage[7].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[7].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.d1:
    port Z[0] of cell ringosc.dstage[6].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[6].id.out:
    port Z[0] of cell ringosc.dstage[6].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[6].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.d1:
    port Z[0] of cell ringosc.dstage[5].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[5].id.out:
    port Z[0] of cell ringosc.dstage[5].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[5].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.d1:
    port Z[0] of cell ringosc.dstage[4].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[4].id.out:
    port Z[0] of cell ringosc.dstage[4].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[4].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.d1:
    port Z[0] of cell ringosc.dstage[3].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[3].id.out:
    port Z[0] of cell ringosc.dstage[3].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[3].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.d1:
    port Z[0] of cell ringosc.dstage[2].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[2].id.out:
    port Z[0] of cell ringosc.dstage[2].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[2].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.d1:
    port Z[0] of cell ringosc.dstage[1].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[1].id.out:
    port Z[0] of cell ringosc.dstage[1].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[1].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.d1:
    port Z[0] of cell ringosc.dstage[11].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[11].id.out:
    port Z[0] of cell ringosc.dstage[11].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[11].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.d1:
    port Z[0] of cell ringosc.dstage[10].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[10].id.out:
    port Z[0] of cell ringosc.dstage[10].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[10].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.d1:
    port Z[0] of cell ringosc.dstage[0].id.delayen1 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb1 (sky130_fd_sc_hd__einvn_4)
Warning: multiple conflicting drivers for digital_pll.\ringosc.dstage[0].id.out:
    port Z[0] of cell ringosc.dstage[0].id.delayen0 (sky130_fd_sc_hd__einvp_2)
    port Z[0] of cell ringosc.dstage[0].id.delayenb0 (sky130_fd_sc_hd__einvn_8)
found and reported 26 problems.

19. Printing statistics.

=== digital_pll ===

   Number of wires:                385
   Number of wire bits:            415
   Number of public wires:         126
   Number of public wire bits:     156
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                407
     sky130_fd_sc_hd__a211o_4        7
     sky130_fd_sc_hd__a21bo_4       16
     sky130_fd_sc_hd__a21o_4         3
     sky130_fd_sc_hd__a22oi_4        1
     sky130_fd_sc_hd__a2bb2o_4      14
     sky130_fd_sc_hd__a32o_4         9
     sky130_fd_sc_hd__and2_4        11
     sky130_fd_sc_hd__and3_4         4
     sky130_fd_sc_hd__and4_4        22
     sky130_fd_sc_hd__buf_2         23
     sky130_fd_sc_hd__clkbuf_1      13
     sky130_fd_sc_hd__clkbuf_2      12
     sky130_fd_sc_hd__clkinv_1      13
     sky130_fd_sc_hd__clkinv_2       2
     sky130_fd_sc_hd__clkinv_8       2
     sky130_fd_sc_hd__conb_1         1
     sky130_fd_sc_hd__dfrtp_4       23
     sky130_fd_sc_hd__einvn_4       13
     sky130_fd_sc_hd__einvn_8       13
     sky130_fd_sc_hd__einvp_1        1
     sky130_fd_sc_hd__einvp_2       26
     sky130_fd_sc_hd__inv_2         58
     sky130_fd_sc_hd__nand2_4        8
     sky130_fd_sc_hd__nor2_4         5
     sky130_fd_sc_hd__o21a_4         6
     sky130_fd_sc_hd__o21ai_4        3
     sky130_fd_sc_hd__o22a_4        18
     sky130_fd_sc_hd__o32a_4         2
     sky130_fd_sc_hd__or2_2          1
     sky130_fd_sc_hd__or2_4         50
     sky130_fd_sc_hd__or3_4          2
     sky130_fd_sc_hd__or4_4         25

   Chip area for module '\digital_pll': 4608.169600

20. Executing Verilog backend.
Dumping module `\digital_pll'.

Warnings: 26 unique messages, 78 total
End of script. Logfile hash: 8249300493, CPU: user 2.20s system 0.07s, MEM: 45.95 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 36% 2x abc (1 sec), 13% 4x stat (0 sec), ...