Notice 0: Reading LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 438 library cells
Notice 0: Finished LEF file:  /project/openlane/digital_pll/runs/digital_pll/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/digital_pll/runs/digital_pll/results/routing/digital_pll.def
Notice 0: Design: digital_pll
Notice 0:     Created 39 pins.
Notice 0:     Created 1297 components and 6327 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 415 nets and 1360 connections.
Notice 0: Finished DEF file: /project/openlane/digital_pll/runs/digital_pll/results/routing/digital_pll.def
Top-level design name: digital_pll
Found port VPWR of type SIGNAL
Found port VGND of type SIGNAL
Power net:  VPWR
Ground net: VGND
Modified power connections of 1297 cells (Remaining: 0 ).