
reading lef ...
Warning: unknown macroClass PAD AREAIO, skipped macroClass property
Warning: unknown macroClass ENDCAP TOPRIGHT, skipped macroClass property
Warning: unknown macroClass PAD AREAIO, skipped macroClass property
Warning: unknown macroClass PAD AREAIO, skipped macroClass property
Warning: unknown macroClass PAD AREAIO, skipped macroClass property
Warning: unknown macroClass PAD INOUT, skipped macroClass property
Warning: unknown macroClass PAD INOUT, skipped macroClass property

units:       1000
#layers:     13
#macros:     485
#vias:       25
#viarulegen: 25

reading def ...

design:      chip_io
die area:    ( 0 0 ) ( 3588000 5188000 )
trackPts:    12
defvias:     0
#components: 821
#terminals:  0
#snets:      0
#nets:       65

reading guide ...

#guides:     1055
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx
List of default vias:
  Layer mcon
    default via: L1M1_PR_MR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: via2_FR
  Layer via3
    default via: M3M4_PR_M
  Layer via4
    default via: via4_FR
Writing reference output def...

libcell analysis ...

instance analysis ...
#unique instances = 327

init region query ...
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

FR_MASTERSLICE shape region query size = 0
FR_VIA shape region query size = 0
li1 shape region query size = 71
mcon shape region query size = 0
met1 shape region query size = 87
via shape region query size = 0
met2 shape region query size = 2492
via2 shape region query size = 0
met3 shape region query size = 236
via3 shape region query size = 144
met4 shape region query size = 24559
via4 shape region query size = 0
met5 shape region query size = 19299


start pin access
  complete 12 pins
  complete 0 unique inst patterns
  complete 0 groups
Expt1 runtime (pin-level access point gen): 0.110981
Expt2 runtime (design-level access pattern gen): 0.000581965
#scanned instances     = 821
#unique  instances     = 327
#stdCellGenAp          = 0
#stdCellValidPlanarAp  = 0
#stdCellValidViaAp     = 0
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 0
#instTermValidViaApCnt = 0
#macroGenAp            = 136
#macroValidPlanarAp    = 129
#macroValidViaAp       = 12
#macroNoAp             = 0

complete pin access
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 43.37 (MB), peak = 43.53 (MB)

post process guides ...
GCELLGRID X -1 DO 375 STEP 13800 ;
GCELLGRID Y -1 DO 260 STEP 13800 ;
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

building cmap ... 

init guide query ...
  complete FR_MASTERSLICE (guide)
  complete FR_VIA (guide)
  complete li1 (guide)
  complete mcon (guide)
  complete met1 (guide)
  complete via (guide)
  complete met2 (guide)
  complete via2 (guide)
  complete met3 (guide)
  complete via3 (guide)
  complete met4 (guide)
  complete via4 (guide)
  complete met5 (guide)

FR_MASTERSLICE guide region query size = 0
FR_VIA guide region query size = 0
li1 guide region query size = 0
mcon guide region query size = 0
met1 guide region query size = 151
via guide region query size = 0
met2 guide region query size = 330
via2 guide region query size = 0
met3 guide region query size = 48
via3 guide region query size = 0
met4 guide region query size = 4
via4 guide region query size = 0
met5 guide region query size = 0

init gr pin query ...


start track assignment
Done with 334 vertical wires in 6 frboxes and 199 horizontal wires in 8 frboxes.
Done with 78 vertical wires in 6 frboxes and 36 horizontal wires in 8 frboxes.

complete track assignment
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 91.09 (MB), peak = 104.64 (MB)

post processing ...

start routing data preparation
initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 91.09 (MB), peak = 104.64 (MB)

start detail routing ...
start 0th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:07, memory = 190.50 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:15, memory = 254.36 (MB)
    completing 30% with 498 violations
    elapsed time = 00:00:23, memory = 158.60 (MB)
    completing 40% with 498 violations
    elapsed time = 00:00:31, memory = 226.31 (MB)
    completing 50% with 498 violations
    elapsed time = 00:00:39, memory = 268.97 (MB)
    completing 60% with 387 violations
    elapsed time = 00:00:47, memory = 193.73 (MB)
    completing 70% with 387 violations
    elapsed time = 00:00:55, memory = 263.58 (MB)
    completing 80% with 315 violations
    elapsed time = 00:01:01, memory = 155.43 (MB)
    completing 90% with 315 violations
    elapsed time = 00:01:09, memory = 221.46 (MB)
    completing 100% with 217 violations
    elapsed time = 00:01:16, memory = 101.30 (MB)
  number of violations = 238
cpu time = 00:03:48, elapsed time = 00:01:16, memory = 445.99 (MB), peak = 446.20 (MB)
total wire length = 99370 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30761 um
total wire length on LAYER met2 = 54312 um
total wire length on LAYER met3 = 7556 um
total wire length on LAYER met4 = 6739 um
total wire length on LAYER met5 = 0 um
total number of vias = 559
up-via summary (total 559):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    488
           met2     63
           met3      8
           met4      0
----------------------
                   559


start 1st optimization iteration ...
    completing 10% with 238 violations
    elapsed time = 00:00:07, memory = 512.24 (MB)
    completing 20% with 238 violations
    elapsed time = 00:00:15, memory = 557.78 (MB)
    completing 30% with 237 violations
    elapsed time = 00:00:23, memory = 489.92 (MB)
    completing 40% with 237 violations
    elapsed time = 00:00:31, memory = 534.66 (MB)
    completing 50% with 237 violations
    elapsed time = 00:00:38, memory = 574.77 (MB)
    completing 60% with 219 violations
    elapsed time = 00:00:46, memory = 512.87 (MB)
    completing 70% with 219 violations
    elapsed time = 00:00:54, memory = 554.51 (MB)
    completing 80% with 209 violations
    elapsed time = 00:01:01, memory = 493.23 (MB)
    completing 90% with 209 violations
    elapsed time = 00:01:09, memory = 538.12 (MB)
    completing 100% with 244 violations
    elapsed time = 00:01:16, memory = 446.20 (MB)
  number of violations = 244
cpu time = 00:03:48, elapsed time = 00:01:16, memory = 446.20 (MB), peak = 581.47 (MB)
total wire length = 99095 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30768 um
total wire length on LAYER met2 = 53921 um
total wire length on LAYER met3 = 7662 um
total wire length on LAYER met4 = 6743 um
total wire length on LAYER met5 = 0 um
total number of vias = 652
up-via summary (total 652):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    571
           met2     73
           met3      8
           met4      0
----------------------
                   652


start 2nd optimization iteration ...
    completing 10% with 244 violations
    elapsed time = 00:00:00, memory = 473.38 (MB)
    completing 20% with 244 violations
    elapsed time = 00:00:00, memory = 469.51 (MB)
    completing 30% with 255 violations
    elapsed time = 00:00:01, memory = 474.81 (MB)
    completing 40% with 255 violations
    elapsed time = 00:00:02, memory = 473.01 (MB)
    completing 50% with 255 violations
    elapsed time = 00:00:02, memory = 469.66 (MB)
    completing 60% with 260 violations
    elapsed time = 00:00:02, memory = 467.87 (MB)
    completing 70% with 260 violations
    elapsed time = 00:00:02, memory = 467.87 (MB)
    completing 80% with 295 violations
    elapsed time = 00:00:03, memory = 469.05 (MB)
    completing 90% with 295 violations
    elapsed time = 00:00:04, memory = 474.46 (MB)
    completing 100% with 204 violations
    elapsed time = 00:00:05, memory = 446.46 (MB)
  number of violations = 204
cpu time = 00:00:16, elapsed time = 00:00:05, memory = 446.46 (MB), peak = 581.47 (MB)
total wire length = 99060 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30712 um
total wire length on LAYER met2 = 53959 um
total wire length on LAYER met3 = 7677 um
total wire length on LAYER met4 = 6710 um
total wire length on LAYER met5 = 0 um
total number of vias = 640
up-via summary (total 640):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    555
           met2     77
           met3      8
           met4      0
----------------------
                   640


start 3rd optimization iteration ...
    completing 10% with 204 violations
    elapsed time = 00:00:02, memory = 476.39 (MB)
    completing 20% with 204 violations
    elapsed time = 00:00:02, memory = 483.86 (MB)
    completing 30% with 153 violations
    elapsed time = 00:00:05, memory = 479.66 (MB)
    completing 40% with 153 violations
    elapsed time = 00:00:06, memory = 473.22 (MB)
    completing 50% with 153 violations
    elapsed time = 00:00:07, memory = 472.88 (MB)
    completing 60% with 76 violations
    elapsed time = 00:00:07, memory = 457.79 (MB)
    completing 70% with 76 violations
    elapsed time = 00:00:07, memory = 473.05 (MB)
    completing 80% with 62 violations
    elapsed time = 00:00:07, memory = 446.41 (MB)
    completing 90% with 62 violations
    elapsed time = 00:00:08, memory = 469.23 (MB)
    completing 100% with 50 violations
    elapsed time = 00:00:08, memory = 446.36 (MB)
  number of violations = 50
cpu time = 00:00:24, elapsed time = 00:00:08, memory = 446.36 (MB), peak = 581.47 (MB)
total wire length = 99071 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30285 um
total wire length on LAYER met2 = 53966 um
total wire length on LAYER met3 = 8149 um
total wire length on LAYER met4 = 6669 um
total wire length on LAYER met5 = 0 um
total number of vias = 844
up-via summary (total 844):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    679
           met2    123
           met3     42
           met4      0
----------------------
                   844


start 4th optimization iteration ...
    completing 10% with 50 violations
    elapsed time = 00:00:00, memory = 473.66 (MB)
    completing 20% with 50 violations
    elapsed time = 00:00:00, memory = 478.04 (MB)
    completing 30% with 31 violations
    elapsed time = 00:00:01, memory = 469.50 (MB)
    completing 40% with 31 violations
    elapsed time = 00:00:01, memory = 472.84 (MB)
    completing 50% with 31 violations
    elapsed time = 00:00:02, memory = 469.82 (MB)
    completing 60% with 16 violations
    elapsed time = 00:00:02, memory = 457.83 (MB)
    completing 70% with 16 violations
    elapsed time = 00:00:02, memory = 457.83 (MB)
    completing 80% with 16 violations
    elapsed time = 00:00:02, memory = 457.82 (MB)
    completing 90% with 16 violations
    elapsed time = 00:00:02, memory = 457.91 (MB)
    completing 100% with 7 violations
    elapsed time = 00:00:02, memory = 457.62 (MB)
  number of violations = 7
cpu time = 00:00:06, elapsed time = 00:00:02, memory = 457.62 (MB), peak = 581.47 (MB)
total wire length = 99086 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30161 um
total wire length on LAYER met2 = 53965 um
total wire length on LAYER met3 = 8300 um
total wire length on LAYER met4 = 6660 um
total wire length on LAYER met5 = 0 um
total number of vias = 893
up-via summary (total 893):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    713
           met2    132
           met3     48
           met4      0
----------------------
                   893


start 5th optimization iteration ...
    completing 10% with 7 violations
    elapsed time = 00:00:00, memory = 457.45 (MB)
    completing 20% with 7 violations
    elapsed time = 00:00:00, memory = 457.45 (MB)
    completing 30% with 7 violations
    elapsed time = 00:00:01, memory = 472.05 (MB)
    completing 40% with 7 violations
    elapsed time = 00:00:01, memory = 475.40 (MB)
    completing 50% with 7 violations
    elapsed time = 00:00:01, memory = 469.59 (MB)
    completing 60% with 4 violations
    elapsed time = 00:00:01, memory = 446.38 (MB)
    completing 70% with 4 violations
    elapsed time = 00:00:01, memory = 446.38 (MB)
    completing 80% with 4 violations
    elapsed time = 00:00:01, memory = 446.36 (MB)
    completing 90% with 4 violations
    elapsed time = 00:00:01, memory = 446.35 (MB)
    completing 100% with 4 violations
    elapsed time = 00:00:01, memory = 446.39 (MB)
  number of violations = 4
cpu time = 00:00:03, elapsed time = 00:00:01, memory = 446.39 (MB), peak = 581.47 (MB)
total wire length = 99080 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30160 um
total wire length on LAYER met2 = 53965 um
total wire length on LAYER met3 = 8294 um
total wire length on LAYER met4 = 6660 um
total wire length on LAYER met5 = 0 um
total number of vias = 893
up-via summary (total 893):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    715
           met2    132
           met3     46
           met4      0
----------------------
                   893


start 6th optimization iteration ...
    completing 10% with 4 violations
    elapsed time = 00:00:00, memory = 457.47 (MB)
    completing 20% with 4 violations
    elapsed time = 00:00:00, memory = 457.60 (MB)
    completing 30% with 4 violations
    elapsed time = 00:00:00, memory = 471.19 (MB)
    completing 40% with 4 violations
    elapsed time = 00:00:00, memory = 471.19 (MB)
    completing 50% with 4 violations
    elapsed time = 00:00:00, memory = 469.71 (MB)
    completing 60% with 4 violations
    elapsed time = 00:00:00, memory = 458.00 (MB)
    completing 70% with 4 violations
    elapsed time = 00:00:01, memory = 458.00 (MB)
    completing 80% with 4 violations
    elapsed time = 00:00:01, memory = 458.00 (MB)
    completing 90% with 4 violations
    elapsed time = 00:00:01, memory = 458.00 (MB)
    completing 100% with 4 violations
    elapsed time = 00:00:01, memory = 458.00 (MB)
  number of violations = 4
cpu time = 00:00:02, elapsed time = 00:00:01, memory = 458.00 (MB), peak = 581.47 (MB)
total wire length = 99077 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30160 um
total wire length on LAYER met2 = 53965 um
total wire length on LAYER met3 = 8289 um
total wire length on LAYER met4 = 6661 um
total wire length on LAYER met5 = 0 um
total number of vias = 889
up-via summary (total 889):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    715
           met2    132
           met3     42
           met4      0
----------------------
                   889


start 7th optimization iteration ...
    completing 10% with 4 violations
    elapsed time = 00:00:00, memory = 472.04 (MB)
    completing 20% with 4 violations
    elapsed time = 00:00:00, memory = 472.04 (MB)
    completing 30% with 4 violations
    elapsed time = 00:00:01, memory = 474.34 (MB)
    completing 40% with 4 violations
    elapsed time = 00:00:01, memory = 474.34 (MB)
    completing 50% with 4 violations
    elapsed time = 00:00:01, memory = 469.70 (MB)
    completing 60% with 4 violations
    elapsed time = 00:00:01, memory = 446.45 (MB)
    completing 70% with 4 violations
    elapsed time = 00:00:01, memory = 446.35 (MB)
    completing 80% with 4 violations
    elapsed time = 00:00:01, memory = 446.35 (MB)
    completing 90% with 4 violations
    elapsed time = 00:00:01, memory = 446.35 (MB)
    completing 100% with 4 violations
    elapsed time = 00:00:01, memory = 446.35 (MB)
  number of violations = 4
cpu time = 00:00:03, elapsed time = 00:00:01, memory = 446.35 (MB), peak = 581.47 (MB)
total wire length = 99077 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30160 um
total wire length on LAYER met2 = 53965 um
total wire length on LAYER met3 = 8289 um
total wire length on LAYER met4 = 6661 um
total wire length on LAYER met5 = 0 um
total number of vias = 889
up-via summary (total 889):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    715
           met2    132
           met3     42
           met4      0
----------------------
                   889


start 8th optimization iteration ...
    completing 10% with 4 violations
    elapsed time = 00:00:00, memory = 470.59 (MB)
    completing 20% with 4 violations
    elapsed time = 00:00:00, memory = 470.59 (MB)
    completing 30% with 1 violations
    elapsed time = 00:00:00, memory = 473.59 (MB)
    completing 40% with 1 violations
    elapsed time = 00:00:00, memory = 472.29 (MB)
    completing 50% with 1 violations
    elapsed time = 00:00:00, memory = 469.77 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 458.13 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 458.12 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
  number of violations = 0
cpu time = 00:00:02, elapsed time = 00:00:01, memory = 457.97 (MB), peak = 581.47 (MB)
total wire length = 99084 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30160 um
total wire length on LAYER met2 = 53965 um
total wire length on LAYER met3 = 8299 um
total wire length on LAYER met4 = 6658 um
total wire length on LAYER met5 = 0 um
total number of vias = 897
up-via summary (total 897):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    715
           met2    132
           met3     50
           met4      0
----------------------
                   897


start 17th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 458.02 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 458.02 (MB), peak = 581.47 (MB)
total wire length = 99084 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30160 um
total wire length on LAYER met2 = 53965 um
total wire length on LAYER met3 = 8299 um
total wire length on LAYER met4 = 6658 um
total wire length on LAYER met5 = 0 um
total number of vias = 897
up-via summary (total 897):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    715
           met2    132
           met3     50
           met4      0
----------------------
                   897


start 25th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 458.06 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 458.04 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 458.02 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 458.02 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 458.06 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 458.02 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 458.02 (MB), peak = 581.47 (MB)
total wire length = 99084 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30160 um
total wire length on LAYER met2 = 53965 um
total wire length on LAYER met3 = 8299 um
total wire length on LAYER met4 = 6658 um
total wire length on LAYER met5 = 0 um
total number of vias = 897
up-via summary (total 897):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    715
           met2    132
           met3     50
           met4      0
----------------------
                   897


start 33rd optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 457.97 (MB), peak = 581.47 (MB)
total wire length = 99084 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30160 um
total wire length on LAYER met2 = 53965 um
total wire length on LAYER met3 = 8299 um
total wire length on LAYER met4 = 6658 um
total wire length on LAYER met5 = 0 um
total number of vias = 897
up-via summary (total 897):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    715
           met2    132
           met3     50
           met4      0
----------------------
                   897


start 41st optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 457.97 (MB), peak = 581.47 (MB)
total wire length = 99084 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30160 um
total wire length on LAYER met2 = 53965 um
total wire length on LAYER met3 = 8299 um
total wire length on LAYER met4 = 6658 um
total wire length on LAYER met5 = 0 um
total number of vias = 897
up-via summary (total 897):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    715
           met2    132
           met3     50
           met4      0
----------------------
                   897


start 49th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 457.98 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 457.98 (MB), peak = 581.47 (MB)
total wire length = 99084 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30160 um
total wire length on LAYER met2 = 53965 um
total wire length on LAYER met3 = 8299 um
total wire length on LAYER met4 = 6658 um
total wire length on LAYER met5 = 0 um
total number of vias = 897
up-via summary (total 897):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    715
           met2    132
           met3     50
           met4      0
----------------------
                   897


start 57th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 457.98 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 457.98 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 457.98 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 457.98 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 457.97 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 457.97 (MB), peak = 581.47 (MB)
total wire length = 99084 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30160 um
total wire length on LAYER met2 = 53965 um
total wire length on LAYER met3 = 8299 um
total wire length on LAYER met4 = 6658 um
total wire length on LAYER met5 = 0 um
total number of vias = 897
up-via summary (total 897):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    715
           met2    132
           met3     50
           met4      0
----------------------
                   897


complete detail routing
total wire length = 99084 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 30160 um
total wire length on LAYER met2 = 53965 um
total wire length on LAYER met3 = 8299 um
total wire length on LAYER met4 = 6658 um
total wire length on LAYER met5 = 0 um
total number of vias = 897
up-via summary (total 897):

----------------------
 FR_MASTERSLICE      0
            li1      0
           met1    715
           met2    132
           met3     50
           met4      0
----------------------
                   897

cpu time = 00:08:41, elapsed time = 00:02:57, memory = 457.97 (MB), peak = 581.47 (MB)

post processing ...

Runtime taken (hrt): 178.807