
reading lef ...

units:       1000
#layers:     13
#macros:     79
#vias:       25
#viarulegen: 25

reading def ...

design:      caravel
die area:    ( 0 0 ) ( 3588000 5188000 )
trackPts:    12
defvias:     0
#components: 47
#terminals:  0
#snets:      0
#nets:       1928

reading guide ...

#guides:     16286
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx
List of default vias:
  Layer mcon
    default via: L1M1_PR_MR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: via2_FR
  Layer via3
    default via: M3M4_PR_M
  Layer via4
    default via: via4_FR
Writing reference output def...

libcell analysis ...

instance analysis ...
#unique instances = 46

init region query ...
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

FR_MASTERSLICE shape region query size = 0
FR_VIA shape region query size = 0
li1 shape region query size = 109
mcon shape region query size = 0
met1 shape region query size = 1973
via shape region query size = 715
met2 shape region query size = 9186
via2 shape region query size = 130
met3 shape region query size = 4304
via3 shape region query size = 194
met4 shape region query size = 4455
via4 shape region query size = 1208
met5 shape region query size = 4561


start pin access
  complete 100 pins
  complete 200 pins
  complete 300 pins
  complete 400 pins
  complete 500 pins
  complete 600 pins
  complete 700 pins
  complete 800 pins
  complete 900 pins
  complete 1000 pins
  complete 2000 pins
  complete 3000 pins
  complete 4000 pins
Error: no ap for por/vdd3v3
  complete 4167 pins
  complete 0 unique inst patterns
  complete 0 groups
Expt1 runtime (pin-level access point gen): 30.2159
Expt2 runtime (design-level access pattern gen): 4.7847e-05
#scanned instances     = 47
#unique  instances     = 46
#stdCellGenAp          = 0
#stdCellValidPlanarAp  = 0
#stdCellValidViaAp     = 0
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 0
#instTermValidViaApCnt = 0
#macroGenAp            = 352082
#macroValidPlanarAp    = 351916
#macroValidViaAp       = 13360
#macroNoAp             = 1

complete pin access
cpu time = 00:01:08, elapsed time = 00:00:30, memory = 73.59 (MB), peak = 73.80 (MB)

post process guides ...
GCELLGRID X -1 DO 360 STEP 14400 ;
GCELLGRID Y -1 DO 249 STEP 14400 ;
  complete 10000 orig guides
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

building cmap ... 

init guide query ...
  complete FR_MASTERSLICE (guide)
  complete FR_VIA (guide)
  complete li1 (guide)
  complete mcon (guide)
  complete met1 (guide)
  complete via (guide)
  complete met2 (guide)
  complete via2 (guide)
  complete met3 (guide)
  complete via3 (guide)
  complete met4 (guide)
  complete via4 (guide)
  complete met5 (guide)

FR_MASTERSLICE guide region query size = 0
FR_VIA guide region query size = 0
li1 guide region query size = 0
mcon guide region query size = 0
met1 guide region query size = 2311
via guide region query size = 0
met2 guide region query size = 5345
via2 guide region query size = 0
met3 guide region query size = 2059
via3 guide region query size = 0
met4 guide region query size = 379
via4 guide region query size = 0
met5 guide region query size = 5

init gr pin query ...


start track assignment
Done with 5724 vertical wires in 5 frboxes and 4375 horizontal wires in 8 frboxes.
Done with 2276 vertical wires in 5 frboxes and 1268 horizontal wires in 8 frboxes.

complete track assignment
cpu time = 00:00:02, elapsed time = 00:00:00, memory = 139.72 (MB), peak = 207.18 (MB)

post processing ...

start routing data preparation
initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 139.72 (MB), peak = 207.18 (MB)

start detail routing ...
start 0th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:11, memory = 239.99 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:22, memory = 289.95 (MB)
    completing 30% with 4334 violations
    elapsed time = 00:00:31, memory = 213.08 (MB)
    completing 40% with 4334 violations
    elapsed time = 00:00:47, memory = 276.42 (MB)
    completing 50% with 4334 violations
    elapsed time = 00:00:58, memory = 323.97 (MB)
    completing 60% with 7803 violations
    elapsed time = 00:01:07, memory = 280.06 (MB)
    completing 70% with 7803 violations
    elapsed time = 00:01:17, memory = 311.95 (MB)
    completing 80% with 7981 violations
    elapsed time = 00:01:27, memory = 251.22 (MB)
    completing 90% with 7981 violations
    elapsed time = 00:01:42, memory = 303.73 (MB)
    completing 100% with 4549 violations
    elapsed time = 00:01:54, memory = 216.67 (MB)
  number of violations = 5655
cpu time = 00:05:42, elapsed time = 00:01:54, memory = 488.14 (MB), peak = 488.38 (MB)
total wire length = 1380895 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 592741 um
total wire length on LAYER met2 = 437175 um
total wire length on LAYER met3 = 263355 um
total wire length on LAYER met4 = 87463 um
total wire length on LAYER met5 = 159 um
total number of vias = 9573
up-via summary (total 9573):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6010
           met2    2678
           met3     871
           met4      14
-----------------------
                   9573


start 1st optimization iteration ...
    completing 10% with 5655 violations
    elapsed time = 00:00:08, memory = 564.25 (MB)
    completing 20% with 5655 violations
    elapsed time = 00:00:18, memory = 595.89 (MB)
    completing 30% with 4001 violations
    elapsed time = 00:00:26, memory = 530.41 (MB)
    completing 40% with 4001 violations
    elapsed time = 00:00:37, memory = 575.44 (MB)
    completing 50% with 4001 violations
    elapsed time = 00:00:45, memory = 606.57 (MB)
    completing 60% with 2342 violations
    elapsed time = 00:00:54, memory = 549.91 (MB)
    completing 70% with 2342 violations
    elapsed time = 00:01:03, memory = 590.08 (MB)
    completing 80% with 1262 violations
    elapsed time = 00:01:10, memory = 542.59 (MB)
    completing 90% with 1262 violations
    elapsed time = 00:01:21, memory = 565.89 (MB)
    completing 100% with 735 violations
    elapsed time = 00:01:29, memory = 488.43 (MB)
  number of violations = 735
cpu time = 00:04:28, elapsed time = 00:01:29, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1376129 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 592862 um
total wire length on LAYER met2 = 435887 um
total wire length on LAYER met3 = 260446 um
total wire length on LAYER met4 = 86932 um
total wire length on LAYER met5 = 0 um
total number of vias = 9001
up-via summary (total 9001):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    5855
           met2    2295
           met3     851
           met4       0
-----------------------
                   9001


start 2nd optimization iteration ...
    completing 10% with 735 violations
    elapsed time = 00:00:03, memory = 521.76 (MB)
    completing 20% with 735 violations
    elapsed time = 00:00:06, memory = 560.01 (MB)
    completing 30% with 885 violations
    elapsed time = 00:00:08, memory = 522.16 (MB)
    completing 40% with 885 violations
    elapsed time = 00:00:11, memory = 561.86 (MB)
    completing 50% with 885 violations
    elapsed time = 00:00:12, memory = 525.52 (MB)
    completing 60% with 870 violations
    elapsed time = 00:00:14, memory = 515.85 (MB)
    completing 70% with 870 violations
    elapsed time = 00:00:17, memory = 550.28 (MB)
    completing 80% with 804 violations
    elapsed time = 00:00:18, memory = 511.98 (MB)
    completing 90% with 804 violations
    elapsed time = 00:00:21, memory = 545.23 (MB)
    completing 100% with 820 violations
    elapsed time = 00:00:22, memory = 488.43 (MB)
  number of violations = 820
cpu time = 00:01:05, elapsed time = 00:00:22, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1375260 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 592517 um
total wire length on LAYER met2 = 434914 um
total wire length on LAYER met3 = 260685 um
total wire length on LAYER met4 = 87142 um
total wire length on LAYER met5 = 0 um
total number of vias = 9181
up-via summary (total 9181):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    5994
           met2    2318
           met3     869
           met4       0
-----------------------
                   9181


start 3rd optimization iteration ...
    completing 10% with 820 violations
    elapsed time = 00:00:05, memory = 521.66 (MB)
    completing 20% with 820 violations
    elapsed time = 00:00:07, memory = 549.75 (MB)
    completing 30% with 716 violations
    elapsed time = 00:00:11, memory = 520.56 (MB)
    completing 40% with 716 violations
    elapsed time = 00:00:17, memory = 558.62 (MB)
    completing 50% with 716 violations
    elapsed time = 00:00:21, memory = 557.04 (MB)
    completing 60% with 507 violations
    elapsed time = 00:00:23, memory = 532.12 (MB)
    completing 70% with 507 violations
    elapsed time = 00:00:24, memory = 523.10 (MB)
    completing 80% with 443 violations
    elapsed time = 00:00:26, memory = 514.59 (MB)
    completing 90% with 443 violations
    elapsed time = 00:00:35, memory = 599.17 (MB)
    completing 100% with 381 violations
    elapsed time = 00:00:51, memory = 488.43 (MB)
  number of violations = 381
cpu time = 00:02:08, elapsed time = 00:00:51, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1374799 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 591863 um
total wire length on LAYER met2 = 434250 um
total wire length on LAYER met3 = 261302 um
total wire length on LAYER met4 = 87382 um
total wire length on LAYER met5 = 0 um
total number of vias = 9512
up-via summary (total 9512):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6154
           met2    2422
           met3     936
           met4       0
-----------------------
                   9512


start 4th optimization iteration ...
    completing 10% with 381 violations
    elapsed time = 00:00:01, memory = 517.96 (MB)
    completing 20% with 381 violations
    elapsed time = 00:00:03, memory = 528.78 (MB)
    completing 30% with 370 violations
    elapsed time = 00:00:06, memory = 521.45 (MB)
    completing 40% with 370 violations
    elapsed time = 00:00:20, memory = 527.12 (MB)
    completing 50% with 370 violations
    elapsed time = 00:00:39, memory = 538.65 (MB)
    completing 60% with 333 violations
    elapsed time = 00:00:39, memory = 530.19 (MB)
    completing 70% with 333 violations
    elapsed time = 00:00:41, memory = 537.41 (MB)
    completing 80% with 308 violations
    elapsed time = 00:00:49, memory = 488.69 (MB)
    completing 90% with 308 violations
    elapsed time = 00:00:53, memory = 543.81 (MB)
    completing 100% with 221 violations
    elapsed time = 00:01:02, memory = 488.43 (MB)
  number of violations = 221
cpu time = 00:02:14, elapsed time = 00:01:02, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1374852 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 590553 um
total wire length on LAYER met2 = 434393 um
total wire length on LAYER met3 = 262535 um
total wire length on LAYER met4 = 87271 um
total wire length on LAYER met5 = 99 um
total number of vias = 9666
up-via summary (total 9666):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6266
           met2    2466
           met3     932
           met4       2
-----------------------
                   9666


start 5th optimization iteration ...
    completing 10% with 221 violations
    elapsed time = 00:00:10, memory = 530.11 (MB)
    completing 20% with 221 violations
    elapsed time = 00:00:14, memory = 535.27 (MB)
    completing 30% with 209 violations
    elapsed time = 00:00:22, memory = 513.64 (MB)
    completing 40% with 209 violations
    elapsed time = 00:00:37, memory = 529.26 (MB)
    completing 50% with 209 violations
    elapsed time = 00:00:49, memory = 543.24 (MB)
    completing 60% with 181 violations
    elapsed time = 00:00:49, memory = 526.32 (MB)
    completing 70% with 181 violations
    elapsed time = 00:00:50, memory = 536.88 (MB)
    completing 80% with 162 violations
    elapsed time = 00:00:56, memory = 488.43 (MB)
    completing 90% with 162 violations
    elapsed time = 00:01:00, memory = 569.12 (MB)
    completing 100% with 131 violations
    elapsed time = 00:01:15, memory = 488.43 (MB)
  number of violations = 131
cpu time = 00:02:46, elapsed time = 00:01:15, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1374911 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 590519 um
total wire length on LAYER met2 = 434342 um
total wire length on LAYER met3 = 262591 um
total wire length on LAYER met4 = 87320 um
total wire length on LAYER met5 = 136 um
total number of vias = 9703
up-via summary (total 9703):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6276
           met2    2479
           met3     946
           met4       2
-----------------------
                   9703


start 6th optimization iteration ...
    completing 10% with 131 violations
    elapsed time = 00:00:03, memory = 527.88 (MB)
    completing 20% with 131 violations
    elapsed time = 00:00:04, memory = 536.64 (MB)
    completing 30% with 122 violations
    elapsed time = 00:00:22, memory = 500.03 (MB)
    completing 40% with 122 violations
    elapsed time = 00:00:33, memory = 524.98 (MB)
    completing 50% with 122 violations
    elapsed time = 00:00:42, memory = 520.11 (MB)
    completing 60% with 85 violations
    elapsed time = 00:00:42, memory = 488.43 (MB)
    completing 70% with 85 violations
    elapsed time = 00:00:48, memory = 541.36 (MB)
    completing 80% with 80 violations
    elapsed time = 00:00:49, memory = 488.43 (MB)
    completing 90% with 80 violations
    elapsed time = 00:00:50, memory = 555.01 (MB)
    completing 100% with 68 violations
    elapsed time = 00:01:00, memory = 488.43 (MB)
  number of violations = 68
cpu time = 00:02:05, elapsed time = 00:01:00, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1374829 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 590291 um
total wire length on LAYER met2 = 434137 um
total wire length on LAYER met3 = 262708 um
total wire length on LAYER met4 = 87555 um
total wire length on LAYER met5 = 136 um
total number of vias = 9749
up-via summary (total 9749):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6298
           met2    2491
           met3     958
           met4       2
-----------------------
                   9749


start 7th optimization iteration ...
    completing 10% with 68 violations
    elapsed time = 00:00:00, memory = 524.58 (MB)
    completing 20% with 68 violations
    elapsed time = 00:00:02, memory = 522.16 (MB)
    completing 30% with 62 violations
    elapsed time = 00:00:06, memory = 488.43 (MB)
    completing 40% with 62 violations
    elapsed time = 00:00:07, memory = 530.70 (MB)
    completing 50% with 62 violations
    elapsed time = 00:00:07, memory = 534.30 (MB)
    completing 60% with 61 violations
    elapsed time = 00:00:16, memory = 488.71 (MB)
    completing 70% with 61 violations
    elapsed time = 00:00:17, memory = 537.04 (MB)
    completing 80% with 59 violations
    elapsed time = 00:00:22, memory = 488.43 (MB)
    completing 90% with 59 violations
    elapsed time = 00:00:23, memory = 534.59 (MB)
    completing 100% with 59 violations
    elapsed time = 00:00:44, memory = 488.43 (MB)
  number of violations = 59
cpu time = 00:01:09, elapsed time = 00:00:44, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1374841 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 590194 um
total wire length on LAYER met2 = 434196 um
total wire length on LAYER met3 = 262807 um
total wire length on LAYER met4 = 87507 um
total wire length on LAYER met5 = 136 um
total number of vias = 9767
up-via summary (total 9767):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6318
           met2    2493
           met3     954
           met4       2
-----------------------
                   9767


start 8th optimization iteration ...
    completing 10% with 59 violations
    elapsed time = 00:00:00, memory = 515.75 (MB)
    completing 20% with 59 violations
    elapsed time = 00:00:00, memory = 514.61 (MB)
    completing 30% with 51 violations
    elapsed time = 00:00:01, memory = 488.60 (MB)
    completing 40% with 51 violations
    elapsed time = 00:00:01, memory = 517.00 (MB)
    completing 50% with 51 violations
    elapsed time = 00:00:01, memory = 517.00 (MB)
    completing 60% with 42 violations
    elapsed time = 00:00:02, memory = 500.83 (MB)
    completing 70% with 42 violations
    elapsed time = 00:00:04, memory = 550.86 (MB)
    completing 80% with 24 violations
    elapsed time = 00:00:08, memory = 488.43 (MB)
    completing 90% with 24 violations
    elapsed time = 00:00:09, memory = 523.43 (MB)
    completing 100% with 13 violations
    elapsed time = 00:00:09, memory = 488.43 (MB)
  number of violations = 13
cpu time = 00:00:18, elapsed time = 00:00:09, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1374850 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 589930 um
total wire length on LAYER met2 = 434205 um
total wire length on LAYER met3 = 263062 um
total wire length on LAYER met4 = 87508 um
total wire length on LAYER met5 = 144 um
total number of vias = 9785
up-via summary (total 9785):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6332
           met2    2497
           met3     954
           met4       2
-----------------------
                   9785


start 9th optimization iteration ...
    completing 10% with 13 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 20% with 13 violations
    elapsed time = 00:00:00, memory = 505.29 (MB)
    completing 30% with 13 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 40% with 13 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 50% with 13 violations
    elapsed time = 00:00:00, memory = 502.09 (MB)
    completing 60% with 12 violations
    elapsed time = 00:00:00, memory = 488.56 (MB)
    completing 70% with 12 violations
    elapsed time = 00:00:00, memory = 512.92 (MB)
    completing 80% with 4 violations
    elapsed time = 00:00:01, memory = 488.43 (MB)
    completing 90% with 4 violations
    elapsed time = 00:00:01, memory = 488.43 (MB)
    completing 100% with 4 violations
    elapsed time = 00:00:01, memory = 488.44 (MB)
  number of violations = 4
cpu time = 00:00:02, elapsed time = 00:00:01, memory = 488.44 (MB), peak = 623.29 (MB)
total wire length = 1374847 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 589881 um
total wire length on LAYER met2 = 434201 um
total wire length on LAYER met3 = 262932 um
total wire length on LAYER met4 = 87513 um
total wire length on LAYER met5 = 318 um
total number of vias = 9791
up-via summary (total 9791):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6332
           met2    2497
           met3     956
           met4       6
-----------------------
                   9791


start 10th optimization iteration ...
    completing 10% with 4 violations
    elapsed time = 00:00:00, memory = 488.46 (MB)
    completing 20% with 4 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 30% with 4 violations
    elapsed time = 00:00:00, memory = 488.47 (MB)
    completing 40% with 4 violations
    elapsed time = 00:00:00, memory = 488.71 (MB)
    completing 50% with 4 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 60% with 1 violations
    elapsed time = 00:00:00, memory = 488.50 (MB)
    completing 70% with 1 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 80% with 1 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 90% with 1 violations
    elapsed time = 00:00:00, memory = 489.09 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1374852 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 589882 um
total wire length on LAYER met2 = 434205 um
total wire length on LAYER met3 = 262932 um
total wire length on LAYER met4 = 87513 um
total wire length on LAYER met5 = 318 um
total number of vias = 9797
up-via summary (total 9797):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6338
           met2    2497
           met3     956
           met4       6
-----------------------
                   9797


start 17th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 488.49 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 488.47 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 488.46 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 488.46 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 488.44 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1374852 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 589882 um
total wire length on LAYER met2 = 434205 um
total wire length on LAYER met3 = 262932 um
total wire length on LAYER met4 = 87513 um
total wire length on LAYER met5 = 318 um
total number of vias = 9797
up-via summary (total 9797):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6338
           met2    2497
           met3     956
           met4       6
-----------------------
                   9797


start 25th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 488.47 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 488.45 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 488.69 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 488.46 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1374852 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 589882 um
total wire length on LAYER met2 = 434205 um
total wire length on LAYER met3 = 262932 um
total wire length on LAYER met4 = 87513 um
total wire length on LAYER met5 = 318 um
total number of vias = 9797
up-via summary (total 9797):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6338
           met2    2497
           met3     956
           met4       6
-----------------------
                   9797


start 33rd optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 488.44 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1374852 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 589882 um
total wire length on LAYER met2 = 434205 um
total wire length on LAYER met3 = 262932 um
total wire length on LAYER met4 = 87513 um
total wire length on LAYER met5 = 318 um
total number of vias = 9797
up-via summary (total 9797):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6338
           met2    2497
           met3     956
           met4       6
-----------------------
                   9797


start 41st optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1374852 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 589882 um
total wire length on LAYER met2 = 434205 um
total wire length on LAYER met3 = 262932 um
total wire length on LAYER met4 = 87513 um
total wire length on LAYER met5 = 318 um
total number of vias = 9797
up-via summary (total 9797):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6338
           met2    2497
           met3     956
           met4       6
-----------------------
                   9797


start 49th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 488.44 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1374852 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 589882 um
total wire length on LAYER met2 = 434205 um
total wire length on LAYER met3 = 262932 um
total wire length on LAYER met4 = 87513 um
total wire length on LAYER met5 = 318 um
total number of vias = 9797
up-via summary (total 9797):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6338
           met2    2497
           met3     956
           met4       6
-----------------------
                   9797


start 57th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 488.44 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 488.43 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 488.43 (MB), peak = 623.29 (MB)
total wire length = 1374852 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 589882 um
total wire length on LAYER met2 = 434205 um
total wire length on LAYER met3 = 262932 um
total wire length on LAYER met4 = 87513 um
total wire length on LAYER met5 = 318 um
total number of vias = 9797
up-via summary (total 9797):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6338
           met2    2497
           met3     956
           met4       6
-----------------------
                   9797


complete detail routing
total wire length = 1374852 um
total wire length on LAYER li1 = 0 um
total wire length on LAYER met1 = 589882 um
total wire length on LAYER met2 = 434205 um
total wire length on LAYER met3 = 262932 um
total wire length on LAYER met4 = 87513 um
total wire length on LAYER met5 = 318 um
total number of vias = 9797
up-via summary (total 9797):

-----------------------
 FR_MASTERSLICE       0
            li1       0
           met1    6338
           met2    2497
           met3     956
           met4       6
-----------------------
                   9797

cpu time = 00:22:10, elapsed time = 00:08:56, memory = 488.43 (MB), peak = 623.29 (MB)

post processing ...

Runtime taken (hrt): 600.326