)]}'
{
  "commit": "079d4cd037d6a8169837b3fbeae7520e02388648",
  "tree": "7a69285fd808532f69e2cf275c58120384590c95",
  "parents": [
    "56b853bde044bd687832503ecac14bcec813a945"
  ],
  "author": {
    "name": "Jecel Assumpcao Jr",
    "email": "jecel@merlintec.com",
    "time": "Sat Dec 05 15:38:23 2020 -0300"
  },
  "committer": {
    "name": "Jecel Assumpcao Jr",
    "email": "jecel@merlintec.com",
    "time": "Sat Dec 05 15:38:23 2020 -0300"
  },
  "message": "clean user_proj_example directory before filling it in\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "bc82b8278a470a9762185987531c7c1d4abef1ee",
      "old_mode": 33188,
      "old_path": "Makefile",
      "new_id": "488e8149bf50215a822b5082baa2f457e588f8bd",
      "new_mode": 33188,
      "new_path": "Makefile"
    },
    {
      "type": "modify",
      "old_id": "7801ce84a26a42951063812e7063fca653bf3ac3",
      "old_mode": 33188,
      "old_path": "openlane/user_proj_example/config.tcl",
      "new_id": "7801ce84a26a42951063812e7063fca653bf3ac3",
      "new_mode": 33261,
      "new_path": "openlane/user_proj_example/config.tcl"
    },
    {
      "type": "modify",
      "old_id": "5bfa966a444b8aa4b065a881e92c3c2783075df3",
      "old_mode": 33188,
      "old_path": "verilog/morphle/user_proj_block.v",
      "new_id": "bdbf79f4df212fb3ffb32eb90e3610c70d18d64b",
      "new_mode": 33188,
      "new_path": "verilog/morphle/user_proj_block.v"
    },
    {
      "type": "modify",
      "old_id": "15d7cf0395b3bb5a23e1cdea5cf4025245d85920",
      "old_mode": 33188,
      "old_path": "verilog/morphle/ycell.v",
      "new_id": "506e8c8425f2e60cf8ca96d730e745d12c55b1e7",
      "new_mode": 33188,
      "new_path": "verilog/morphle/ycell.v"
    },
    {
      "type": "modify",
      "old_id": "db3f4d623de12affb65438b03aef931f07105f95",
      "old_mode": 33188,
      "old_path": "verilog/mtests/test004.tv",
      "new_id": "ad2d230c276fc3552150f4c030300502debb71c2",
      "new_mode": 33188,
      "new_path": "verilog/mtests/test004.tv"
    },
    {
      "type": "modify",
      "old_id": "4b1e16fa9fcd65f46719b79225a1ef33b260d446",
      "old_mode": 33188,
      "old_path": "verilog/mtests/test005upblock.v",
      "new_id": "6e75168e5bcc4906fbdf3ec9ac012113ed73eafe",
      "new_mode": 33188,
      "new_path": "verilog/mtests/test005upblock.v"
    }
  ]
}
