diff --git a/Makefile b/Makefile
index bc82b82..488e814 100644
--- a/Makefile
+++ b/Makefile
@@ -55,19 +55,26 @@
 verify:
 	echo "verify"
 
-.PHONY: copy_block
-copy_block:
+.PHONY: init_block_flat
+init_block_flat:
+	@echo
+	@echo "       clearing user_projec_example"
+	@echo
+	rm -fR openlane/user_proj_example/*
 	@echo
 	@echo "       overwritting user_proj_example with 16x16 block"
 	@echo
 	cp ol_templates/config_block.tcl openlane/user_proj_example/config.tcl
-	cp ol_templates/pdn.tcl openlane/user_proj_example/pdn.tcl
 	cp ol_templates/pin_order.cfg openlane/user_proj_example/pin_order.cfg
 
-.PHONY: copy_block2
-copy_block2:
+.PHONY: init_block_cells
+init_block_cells:
 	@echo
-	@echo "       overwritting user_proj_example with black box 16x16 block"
+	@echo "       clearing user_projec_example"
+	@echo
+	rm -fR openlane/user_proj_example/*
+	@echo
+	@echo "       overwritting user_proj_example with 16x16 block using black box cells"
 	@echo
 	cp ol_templates/config_block2.tcl openlane/user_proj_example/config.tcl
 	cp ol_templates/pdn.tcl openlane/user_proj_example/pdn.tcl
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
old mode 100644
new mode 100755
diff --git a/verilog/morphle/user_proj_block.v b/verilog/morphle/user_proj_block.v
index 5bfa966..bdbf79f 100644
--- a/verilog/morphle/user_proj_block.v
+++ b/verilog/morphle/user_proj_block.v
@@ -100,7 +100,7 @@
   wire [HMSB:0] dvempty;   // this cell interrupts vertical signals to down
 
   // UP
-  wire [HMSB:0] uempty = {HMSB{1'b0}};    // cell U is not empty, so the LA is above us
+  wire [HMSB:0] uempty = {BLOCKWIDTH{1'b0}};    // cell U is not empty, so the LA is above us
   wire [HMSB2:0] uout;
   wire [HMSB:0] cbitout; // configuration bit to next cell (D)
   assign la_data_out = {{80{1'b0}},cbitout,uout};
@@ -111,19 +111,19 @@
   wire [HMSB2:0] uin = la_data_in[95:64];
 
   // DOWN
-  wire [HMSB:0] dempty = {HMSB{1'b1}};    // cell D is empty, so we are the bottommost of a signal
+  wire [HMSB:0] dempty = {BLOCKWIDTH{1'b1}};    // cell D is empty, so we are the bottommost of a signal
   wire [HMSB2:0] dout;                    // left dangling to avoid loops that confuse the tools
-  wire [HMSB2:0] din = {HMSB2{1'b0}};
+  wire [HMSB2:0] din = {(2*BLOCKWIDTH){1'b0}};
 
   // LEFT
-  wire [VMSB:0] lempty = {VMSB{1'b1}};    // cell L is empty, so we are the leftmost of a signal
+  wire [VMSB:0] lempty = {BLOCKHEIGHT{1'b1}};    // cell L is empty, so we are the leftmost of a signal
   wire [VMSB2:0] lout;
-  wire [VMSB2:0] lin = {VMSB2{1'b0}};
+  wire [VMSB2:0] lin = {(2*BLOCKHEIGHT){1'b0}};
 
   // RIGHT
-  wire [VMSB:0] rempty = {VMSB{1'b1}};    // cell D is empty, so we are the rightmost of a signal
+  wire [VMSB:0] rempty = {BLOCKHEIGHT{1'b1}};    // cell D is empty, so we are the rightmost of a signal
   wire [VMSB2:0] rout;
-  wire [VMSB2:0] rin = {VMSB2{1'b0}};
+  wire [VMSB2:0] rin = {(2*BLOCKHEIGHT){1'b0}};
 
     yblock #(.BLOCKWIDTH(BLOCKWIDTH), .BLOCKHEIGHT(BLOCKHEIGHT))
         blk (.reset(reset), .confclk(confclk), .cbitin(cbitin), .cbitout(cbitout),
diff --git a/verilog/morphle/ycell.v b/verilog/morphle/ycell.v
index 15d7cf0..506e8c8 100644
--- a/verilog/morphle/ycell.v
+++ b/verilog/morphle/ycell.v
@@ -92,13 +92,13 @@
        always @*
          case(cnfg)
            default: r = 9'b110001000; // . is empty and blocked
-           3'b001: r = 9'b000110011; // +     sync with don't cares
+           3'b001: r = 9'b001000100; // +     short circuit both
            3'b010: r = 9'b001001000; // -     horizontal short circuit
            3'b011: r = 9'b010000100; // |     vertical short circuit
-           3'b100: r = 9'b000110001; // 1     1 vertical, X horizontal
-           3'b101: r = 9'b000110010; // 0     0 vertical, X horizontal
-           3'b110: r = 9'b000010011; // Y     X vertical, 1 horizontal     
-           3'b111: r = 9'b000100011; // N     X vertical, 0 horizontal
+           3'b100: r = 9'b000000101; // 1     1 vertical and short
+           3'b101: r = 9'b000000110; // 0     0 vertical and short
+           3'b110: r = 9'b001010000; // Y     1 horizontal and short    
+           3'b111: r = 9'b001100000; // N     0 horizontal and short
          endcase
        
 endmodule
diff --git a/verilog/mtests/test004.tv b/verilog/mtests/test004.tv
index db3f4d6..ad2d230 100644
--- a/verilog/mtests/test004.tv
+++ b/verilog/mtests/test004.tv
@@ -50,15 +50,58 @@
 0080000
 00C0000  // another 0
 0080000
-30C0000  // configured to 000 (space)
+30C0000  // configured to 000 (.)
 3000000  // out of reset
 3008000  // 1 from U
 3008888  // 1 from all neighbors (now blocks to save energy)
 3000400  // 0 from D (now blocks)
 3080000  // reset
 30C0000  // clock in a 0
+3080000
+30C0000  // clock in a 0
 30A0000
-00E0000  // clock in a 1 (no longer empty - N)
+00E0000  // a 1 - configured to 001 (+)
+0000000  // out of reset
+0080000  // reset
+10C0000  // clock in a 0 (thinks it is 010 = -)
+10A0000
+00F0000  // clock in a 1 (thinks it is 101 = 0)
+0090000
+10C0000  // another 0 - configured to 010 (-)
+1000000  // out of reset
+1080000  // reset
+00D0000  // clock in a 0 (thinks it is 100 = 1)
+00B0000
+00E0000  // clock in a 1 (thinks it is 001 = +)
 00A0000
-20E0000  // another 1 - configured to 110 (Y)
+20E0000  // another 1 - configured to 011 (|)
 2000000  // out of reset
+20A0000  // reset
+00F0000  // clock in a 1 (thinks it is 111 = N)
+0090000
+00D0000  // clock in a 0 (thinks it is 110 = Y)
+0090000
+00D0000  // another 1 - configured to 100 (1)
+0010000  // out of reset
+00B0000  // reset
+00E0000  // clock in a 1 (thinks it is 001 = +)
+0080000
+10C0000  // clock in a 0 (thinks it is 010 = -)
+10A0000
+00F0000  // another 1 - configured to 101 (0)
+0010000  // out of reset
+00B0000  // reset
+20E0000  // clock in a 1 (thinks it is 011 = |)
+20A0000
+00F0000  // clock in a 1 (thinks it is 111 = N)
+0090000
+00D0000  // a 0 - configured to 110 (Y)
+0010000  // out of reset
+00B0000  // reset
+00F0000  // clock in a 1 (thinks it is 101 = 0)
+00B0000
+20E0000  // clock in a 1 (thinks it is 011 = |)
+20A0000
+00F0000  // another 1 - configured to 111 (N)
+0010000  // out of reset
+0090000  // reset
diff --git a/verilog/mtests/test005upblock.v b/verilog/mtests/test005upblock.v
index 4b1e16f..6e75168 100644
--- a/verilog/mtests/test005upblock.v
+++ b/verilog/mtests/test005upblock.v
@@ -121,6 +121,12 @@
   always @(posedge clk)
   begin
     #1; {tvout,xtvin} = testvectors[vectornum][99:0];
+    $display("just read vector %d %h %h", vectornum, tvout, xtvin);
+    if (xtvin === 48'bx)
+    begin
+      $display("%d tests completed with %d errors", vectornum-1, errors);
+      $finish;   // End simulation
+    end
   end
   
   wire reset = la_data_in[113];
@@ -129,11 +135,6 @@
   always @(negedge clk)
   begin
     $display("testing vector %d %h %h", vectornum, tvout, xtvin);
-    if (xtvin === 48'bx)
-    begin
-      $display("%d tests completed with %d errors", vectornum, errors);
-      $finish;   // End simulation
-    end
     if ((!tvout[51] & la_data_out[47:32] !== xtvin[47:32]) |
         (!tvout[50] & la_data_out[31:0] !== xtvin[31:0])) 
     begin
@@ -144,8 +145,45 @@
                xtvin[47:32], xtvin[31:0]);
       errors = errors + 1;
     end
+      $display(" uin0 = %b", DUT.blk.vs[0]);
+      $display(" uin1 = %b", DUT.blk.vs[1]);
+      $display(" uin2 = %b", DUT.blk.vs[2]);
+      $display(" uin3 = %b", DUT.blk.vs[3]);
+      $display(" lin0 = %b", DUT.blk.hs[0]);
+      $display(" lin1 = %b", DUT.blk.hs[1]);
+      $display(" lin2 = %b", DUT.blk.hs[2]);
+      $display(" lin3 = %b", DUT.blk.hs[3]);
+      $display(" lin4 = %b", DUT.blk.hs[4]);
+      $display(" lin5 = %b", DUT.blk.hs[5]);
+      $display(" lin6 = %b", DUT.blk.hs[6]);
+      $display(" lin7 = %b", DUT.blk.hs[7]);
+      $display(" ve0 = %b", DUT.blk.ve[0]);
+      $display(" ve1 = %b", DUT.blk.ve[1]);
+      $display(" ve2 = %b", DUT.blk.ve[2]);
+      $display(" ve3 = %b", DUT.blk.ve[3]);
+      $display(" he0 = %b", DUT.blk.he[0]);
+      $display(" he1 = %b", DUT.blk.he[1]);
+      $display(" he2 = %b", DUT.blk.he[2]);
+      $display(" he3 = %b", DUT.blk.he[3]);
+      $display(" he4 = %b", DUT.blk.he[4]);
+      $display(" he5 = %b", DUT.blk.he[5]);
+      $display(" he6 = %b", DUT.blk.he[6]);
+      $display(" he7 = %b", DUT.blk.he[7]);
+      $display(" back ve0 = %b", DUT.blk.ve2[0]);
+      $display(" ve1 = %b", DUT.blk.ve2[1]);
+      $display(" ve2 = %b", DUT.blk.ve2[2]);
+      $display(" ve3 = %b", DUT.blk.ve2[3]);
+      $display(" he0 = %b", DUT.blk.he2[0]);
+      $display(" he1 = %b", DUT.blk.he2[1]);
+      $display(" he2 = %b", DUT.blk.he2[2]);
+      $display(" he3 = %b", DUT.blk.he2[3]);
+      $display(" he4 = %b", DUT.blk.he2[4]);
+      $display(" he5 = %b", DUT.blk.he2[5]);
+      $display(" he6 = %b", DUT.blk.he2[6]);
+      $display(" he7 = %b", DUT.blk.he2[7]);
       // increment array index and read next testvector
     vectornum= vectornum + 1;
+    $display("testing vector %d next", vectornum);
   end
   
 endmodule