)]}'
{
  "commit": "058d2fc308548859f4e9d9931bf16c5cd2aa6b2e",
  "tree": "fc261432aaccec9afbb92492ead8086eb1aeb4f0",
  "parents": [
    "079d4cd037d6a8169837b3fbeae7520e02388648"
  ],
  "author": {
    "name": "Jecel Assumpcao Jr",
    "email": "jecel@merlintec.com",
    "time": "Sun Dec 06 03:40:33 2020 -0300"
  },
  "committer": {
    "name": "Jecel Assumpcao Jr",
    "email": "jecel@merlintec.com",
    "time": "Sun Dec 06 03:40:33 2020 -0300"
  },
  "message": "more tests and note that bit 0 is rightmost and 16 leftmost\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "7801ce84a26a42951063812e7063fca653bf3ac3",
      "old_mode": 33261,
      "old_path": "ol_templates/config_block.tcl",
      "new_id": "8b58a5ceca10d9b6eae26560f0cabc6ed1483233",
      "new_mode": 33261,
      "new_path": "ol_templates/config_block.tcl"
    },
    {
      "type": "modify",
      "old_id": "7801ce84a26a42951063812e7063fca653bf3ac3",
      "old_mode": 33261,
      "old_path": "openlane/user_proj_example/config.tcl",
      "new_id": "8b58a5ceca10d9b6eae26560f0cabc6ed1483233",
      "new_mode": 33261,
      "new_path": "openlane/user_proj_example/config.tcl"
    },
    {
      "type": "delete",
      "old_id": "f6d953c8ebaf5ba335d8d39c0c24c4ba7e4d95bc",
      "old_mode": 33188,
      "old_path": "openlane/user_proj_example/pdn.tcl",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "modify",
      "old_id": "506e8c8425f2e60cf8ca96d730e745d12c55b1e7",
      "old_mode": 33188,
      "old_path": "verilog/morphle/ycell.v",
      "new_id": "dccbfccaaa6efe179a1acbad3afcbca35b80ea32",
      "new_mode": 33188,
      "new_path": "verilog/morphle/ycell.v"
    },
    {
      "type": "modify",
      "old_id": "ad2d230c276fc3552150f4c030300502debb71c2",
      "old_mode": 33188,
      "old_path": "verilog/mtests/test004.tv",
      "new_id": "d133429deed856b8fc9e2240dadba8b79ae14fbc",
      "new_mode": 33188,
      "new_path": "verilog/mtests/test004.tv"
    },
    {
      "type": "modify",
      "old_id": "f1674dc6c8c83ecd2df6021d45b2ff915f5a557a",
      "old_mode": 33188,
      "old_path": "verilog/mtests/test004ycell.v",
      "new_id": "071379b30b5858da581f0390559d5d6c51ea107b",
      "new_mode": 33188,
      "new_path": "verilog/mtests/test004ycell.v"
    },
    {
      "type": "modify",
      "old_id": "ed53464c03489d21ee0f4bfd10d5bb3e7714bfea",
      "old_mode": 33188,
      "old_path": "verilog/mtests/test005.tv",
      "new_id": "b83e4861716d0cc0464ea8365057ce6c1640a066",
      "new_mode": 33188,
      "new_path": "verilog/mtests/test005.tv"
    },
    {
      "type": "modify",
      "old_id": "6e75168e5bcc4906fbdf3ec9ac012113ed73eafe",
      "old_mode": 33188,
      "old_path": "verilog/mtests/test005upblock.v",
      "new_id": "90e010bc893c54cd40f47fe272a21b50084be758",
      "new_mode": 33188,
      "new_path": "verilog/mtests/test005upblock.v"
    }
  ]
}