verilog/mtests/test004.tv

// SPDX-FileCopyrightText: Copyright 2020 Jecel Mattos de Assumpcao Jr
// 
// SPDX-License-Identifier: Apache-2.0 
// 
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// 
//     https://www.apache.org/licenses/LICENSE-2.0
// 
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

// test vectors for basic Morphle Logic "yellow cell"
// to be used with test004ycell.v
//
// each vector in the the format of 7 hex digits
//
// for two bit wide signals 00 indicates "empty",
// "01" indicates a 0 value and "10 a 1 value
//
// the first digit is: 0,0,xhempty,xvempty
// where these are the expected values of hempty and vempty
// and these depend only on what the configuration of the cell is
//
// the second digit is: uempty,dempty,lempty,rempty
// these are 1 if the corresponding neighbors are empty
//
// the third digit is: reset,confclk,cbitin,xcbitout
// where reset is 1 to freeze the cell, and cbitin is a new
// configuration bit read on each rising edge of confclk
// the expected value of cbitout is the value of cbitin
// delayed by three clocks
//
// the fourth digit is: uin,xuout (two bits each)
// where uin is a value from the neighbor at the top and the
// expected value for uout goes to that neighbor
//
// the fifth digit is: din,xdout (two bits each)
// the sixth digit is: lin,xlout (two bits each)
// the seventh digit is: rin,xrout (two bits each)

0000000  // first two vectors have the output ignored to settle down
0080000  // reset everything [1]*
0080000  // keep it in reset a little longer
00C0000  // clock in a 0
0080000
00C0000  // another 0
0080000
30C0000  // configured to 000 (.)
3000000  // out of reset
3008000  // 1 from U
3008888  // 1 from all neighbors (now blocks to save energy)
3000400  // 0 from D (now blocks)
3080000  // reset
30C0000  // clock in a 0
3080000
30C0000  // clock in a 0
30A0000
00E0000  // a 1 - configured to 001 (+)
0000000  // out of reset
0080000  // reset
10C0000  // clock in a 0 (thinks it is 010 = -)
10A0000
00F0000  // clock in a 1 (thinks it is 101 = 0)
0090000
10C0000  // another 0 - configured to 010 (-)
1000000  // out of reset
1080000  // reset
00D0000  // clock in a 0 (thinks it is 100 = 1)
00B0000
00E0000  // clock in a 1 (thinks it is 001 = +)
00A0000
20E0000  // another 1 - configured to 011 (|)
2000000  // out of reset
20A0000  // reset
00F0000  // clock in a 1 (thinks it is 111 = N)
0090000
00D0000  // clock in a 0 (thinks it is 110 = Y)
0090000
00D0000  // another 1 - configured to 100 (1)
0010000  // out of reset
00B0000  // reset
00E0000  // clock in a 1 (thinks it is 001 = +)
0080000
10C0000  // clock in a 0 (thinks it is 010 = -)
10A0000
00F0000  // another 1 - configured to 101 (0)
0010000  // out of reset
00B0000  // reset
20E0000  // clock in a 1 (thinks it is 011 = |)
20A0000
00F0000  // clock in a 1 (thinks it is 111 = N)
0090000
00D0000  // a 0 - configured to 110 (Y)
0010000  // out of reset
00B0000  // reset
00F0000  // clock in a 1 (thinks it is 101 = 0)
00B0000
20E0000  // clock in a 1 (thinks it is 011 = |)
20A0000
00F0000  // another 1 - configured to 111 (N)
0010000  // out of reset with no empty neighbors
0014000  // uin = 0
0010000
0011400  // din = 0 ==> dout = 0
0010000
0010041  // lin = 0 ==> rout = 0
0010000
0010014  // rin = 0 ==> lout = 0
0010000
0011482  // din = 0, lin = 1 (what we are looking for) ==> rout = 1, dout = 0
0011400  // lin = empty, but previous result was supposed to be latched
0010000
0011482  // repeat
0010082  // din = empty
0012882  // din = 1 (mismatch for next time)
0012800  // lin = empty ==> rout = empty
0012882  // lin = 1 ==> rout = 1 (0 hout was bypassed)
0010000
0090000  // reset