diff --git a/ol_templates/config_block.tcl b/ol_templates/config_block.tcl
index 7801ce8..8b58a5c 100755
--- a/ol_templates/config_block.tcl
+++ b/ol_templates/config_block.tcl
@@ -9,14 +9,16 @@
 	$script_dir/../../verilog/morphle/user_proj_block.v"
 
 set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_PERIOD) "200"
+set ::env(CLOCK_PERIOD) "2000"
 
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 set ::env(CLOCK_TREE_SYNTH) 0
 set ::env(FP_CONTEXT_DEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def.macro_placement.def
 set ::env(FP_CONTEXT_LEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 1000 1000"
+#set ::env(FP_SIZING) absolute
+#set ::env(DIE_AREA) "0 0 2200 2200"
+set ::env(FP_SIZING) relative
+set ::env(FP_CORE_UTIL) 35
 set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.65
+set ::env(PL_TARGET_DENSITY) 0.15
 
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 7801ce8..8b58a5c 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -9,14 +9,16 @@
 	$script_dir/../../verilog/morphle/user_proj_block.v"
 
 set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_PERIOD) "200"
+set ::env(CLOCK_PERIOD) "2000"
 
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 set ::env(CLOCK_TREE_SYNTH) 0
 set ::env(FP_CONTEXT_DEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def.macro_placement.def
 set ::env(FP_CONTEXT_LEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 1000 1000"
+#set ::env(FP_SIZING) absolute
+#set ::env(DIE_AREA) "0 0 2200 2200"
+set ::env(FP_SIZING) relative
+set ::env(FP_CORE_UTIL) 35
 set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.65
+set ::env(PL_TARGET_DENSITY) 0.15
 
diff --git a/openlane/user_proj_example/pdn.tcl b/openlane/user_proj_example/pdn.tcl
deleted file mode 100644
index f6d953c..0000000
--- a/openlane/user_proj_example/pdn.tcl
+++ /dev/null
@@ -1,47 +0,0 @@
-# Power nets
-set ::power_nets $::env(_VDD_NET_NAME)
-set ::ground_nets $::env(_GND_NET_NAME)
-
-pdngen::specify_grid stdcell {
-    name grid
-	core_ring {
-		met5 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_H_OFFSET)}
-		met4 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_V_OFFSET)}
-	}
-	rails {
-	}
-    straps {
-	    met4 {width $::env(_WIDTH) pitch $::env(_V_PITCH) offset $::env(_V_PDN_OFFSET)}
-	    met5 {width $::env(_WIDTH) pitch $::env(_H_PITCH) offset $::env(_H_PDN_OFFSET)}
-    }
-    connect {{met4 met5}}
-}
-
-pdngen::specify_grid macro {
-	instance "obs_core_obs"
-    power_pins $::env(_VDD_NET_NAME)
-    ground_pins $::env(_GND_NET_NAME)
-    blockages "li1 met1 met2 met3 met4 met5"
-    straps { 
-    } 
-    connect {}
-}
-
-
-pdngen::specify_grid macro {
-    power_pins $::env(_VDD_NET_NAME)
-    ground_pins $::env(_GND_NET_NAME)
-    blockages ""
-    straps { 
-    } 
-    connect {}
-}
-
-set ::halo 0
-
-# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
-set ::rails_start_with "POWER" ;
-
-# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
-set ::stripes_start_with "POWER" ;
-
diff --git a/verilog/morphle/ycell.v b/verilog/morphle/ycell.v
index 506e8c8..dccbfcc 100644
--- a/verilog/morphle/ycell.v
+++ b/verilog/morphle/ycell.v
@@ -165,29 +165,31 @@
                  
   assign hempty = empty | hblock;
   wire hreset = reset | hblock; // perhaps "| hbypass" to save energy?
+  wire hosc = ~hreset & ~(lempty & rempty); // safe to "oscillate" if not isolated
   wire [1:0] hin;
   wire [1:0] hout;
   wire [1:0] hback;
 
   assign vempty = empty | vblock;
   wire vreset = reset | vblock;
+  wire vosc = ~vreset & ~(uempty & dempty); // safe to "oscillate" if not isolated
   wire [1:0] vin;
   wire [1:0] vout;
   wire [1:0] vback;
 
-  wire [1:0] hmatch = {vback[1]&hmatch1,vback[0]&hmatch0};
+  wire [1:0] hmatch = {(vback[1]&hmatch1)|(vback[0]&hmatch0),(vback[1]&~hmatch1&hmatch0)|(vback[0]&~hmatch0&hmatch1)};
   ycfsm hfsm (.reset(hreset), .in(hin), .match(hmatch), .out(hout));
   wire [1:0] bhout = hbypass ? hin : hout;
   assign rout = bhout;
-  assign hin = lempty ? {~(hback[1]|hback[1'b0]),1'b0} : lin;
+  assign hin = lempty ? {hosc&(~(hback[1]|hback[1'b0])),1'b0} : lin; // no oscillation on reset
   assign hback = (rempty | hempty) ? bhout : rin; // don't propagate when rightmost or empty
   assign lout = hback;
   
-  wire [1:0] vmatch = {hback[1]&vmatch1,hback[0]&vmatch0};
+  wire [1:0] vmatch = {(hback[1]&vmatch1)|(hback[0]&vmatch0),(hback[1]&~vmatch1&vmatch0)|(hback[0]&~vmatch0&vmatch1)};
   ycfsm vfsm (.reset(vreset), .in(vin), .match(vmatch), .out(vout));
   wire [1:0] bvout = vbypass ? vin : vout;
   assign dout = bvout;
-  assign vin = uempty ? {~(vback[1]|vback[1'b0]),1'b0} : uin;
+  assign vin = uempty ? {vosc&(~(vback[1]|vback[1'b0])),1'b0} : uin; // no oscillation on reset
   assign vback = (dempty | vempty) ? bvout : din; // don't propagate when bottommost or empty
   assign uout = vback;
 
diff --git a/verilog/mtests/test004.tv b/verilog/mtests/test004.tv
index ad2d230..d133429 100644
--- a/verilog/mtests/test004.tv
+++ b/verilog/mtests/test004.tv
@@ -41,7 +41,7 @@
 //
 // the fifth digit is: din,xdout (two bits each)
 // the sixth digit is: lin,xlout (two bits each)
-// the seventh digit is: rin,xrout (two bits each 
+// the seventh digit is: rin,xrout (two bits each)
 
 0000000  // first two vectors have the output ignored to settle down
 0080000  // reset everything [1]*
@@ -103,5 +103,22 @@
 20E0000  // clock in a 1 (thinks it is 011 = |)
 20A0000
 00F0000  // another 1 - configured to 111 (N)
-0010000  // out of reset
+0010000  // out of reset with no empty neighbors
+0014000  // uin = 0
+0010000
+0011400  // din = 0 ==> dout = 0
+0010000
+0010041  // lin = 0 ==> rout = 0
+0010000
+0010014  // rin = 0 ==> lout = 0
+0010000
+0011482  // din = 0, lin = 1 (what we are looking for) ==> rout = 1, dout = 0
+0011400  // lin = empty, but previous result was supposed to be latched
+0010000
+0011482  // repeat
+0010082  // din = empty
+0012882  // din = 1 (mismatch for next time)
+0012800  // lin = empty ==> rout = empty
+0012882  // lin = 1 ==> rout = 1 (0 hout was bypassed)
+0010000
 0090000  // reset
diff --git a/verilog/mtests/test004ycell.v b/verilog/mtests/test004ycell.v
index f1674dc..071379b 100644
--- a/verilog/mtests/test004ycell.v
+++ b/verilog/mtests/test004ycell.v
@@ -104,7 +104,8 @@
       $display("%d tests completed with %d errors", vectornum, errors);
       $finish;   // End simulation
     end
-    $display("testing vector %d", vectornum);
+    $display("testing vector %d vmatch %b hmatch %b vin %b vout %b hin %b hout %b",
+              vectornum, DUT.vmatch, DUT.hmatch, DUT.vin, DUT.vout, DUT.hin, DUT.hout);
     if (vectornum>6)        // skip six entries to settle down since we
                             // can't expect unknown values
     begin
diff --git a/verilog/mtests/test005.tv b/verilog/mtests/test005.tv
index ed53464..b83e486 100644
--- a/verilog/mtests/test005.tv
+++ b/verilog/mtests/test005.tv
@@ -168,4 +168,4 @@
 A_2600_00000000_0000_00000000  // lsb bit
 B_2600_00000000_0000_00000000
 0_0000_00000000_0000_00000000  // normal operation!
-0_0000_15000000_0000_00000001  // inject E0 00 EE EE EE EE EE EE 
+0_0000_15A80000_0000_15000000  // inject E0 00 11 1E EE EE EE EE 
diff --git a/verilog/mtests/test005upblock.v b/verilog/mtests/test005upblock.v
index 6e75168..90e010b 100644
--- a/verilog/mtests/test005upblock.v
+++ b/verilog/mtests/test005upblock.v
@@ -145,42 +145,32 @@
                xtvin[47:32], xtvin[31:0]);
       errors = errors + 1;
     end
-      $display(" uin0 = %b", DUT.blk.vs[0]);
-      $display(" uin1 = %b", DUT.blk.vs[1]);
-      $display(" uin2 = %b", DUT.blk.vs[2]);
-      $display(" uin3 = %b", DUT.blk.vs[3]);
-      $display(" lin0 = %b", DUT.blk.hs[0]);
-      $display(" lin1 = %b", DUT.blk.hs[1]);
-      $display(" lin2 = %b", DUT.blk.hs[2]);
-      $display(" lin3 = %b", DUT.blk.hs[3]);
-      $display(" lin4 = %b", DUT.blk.hs[4]);
-      $display(" lin5 = %b", DUT.blk.hs[5]);
-      $display(" lin6 = %b", DUT.blk.hs[6]);
-      $display(" lin7 = %b", DUT.blk.hs[7]);
+      $display(" u0  = %b %b", DUT.blk.vs[0], DUT.blk.vb[0]);
+      $display(" u1  = %b %b", DUT.blk.vs[1], DUT.blk.vb[1]);
+      $display(" u2  = %b %b", DUT.blk.vs[2], DUT.blk.vb[2]);
+      $display(" u3  = %b %b", DUT.blk.vs[3], DUT.blk.vb[3]);
+      $display(" l8  = %b %b", DUT.blk.hs[8], DUT.blk.hb[8]);
+      $display(" l9  = %b %b", DUT.blk.hs[9], DUT.blk.hb[9]);
+      $display(" l10 = %b %b", DUT.blk.hs[10], DUT.blk.hb[10]);
+      $display(" l11 = %b %b", DUT.blk.hs[11], DUT.blk.hb[11]);
+      $display(" l12 = %b %b", DUT.blk.hs[12], DUT.blk.hb[12]);
+      $display(" l13 = %b %b", DUT.blk.hs[13], DUT.blk.hb[13]);
+      $display(" l14 = %b %b", DUT.blk.hs[14], DUT.blk.hb[14]);
+      $display(" l15 = %b %b", DUT.blk.hs[15], DUT.blk.hb[15]);
+      $display(" r15 = %b %b", DUT.blk.hs[16], DUT.blk.hb[16]);
       $display(" ve0 = %b", DUT.blk.ve[0]);
       $display(" ve1 = %b", DUT.blk.ve[1]);
       $display(" ve2 = %b", DUT.blk.ve[2]);
       $display(" ve3 = %b", DUT.blk.ve[3]);
-      $display(" he0 = %b", DUT.blk.he[0]);
-      $display(" he1 = %b", DUT.blk.he[1]);
-      $display(" he2 = %b", DUT.blk.he[2]);
-      $display(" he3 = %b", DUT.blk.he[3]);
-      $display(" he4 = %b", DUT.blk.he[4]);
-      $display(" he5 = %b", DUT.blk.he[5]);
-      $display(" he6 = %b", DUT.blk.he[6]);
-      $display(" he7 = %b", DUT.blk.he[7]);
-      $display(" back ve0 = %b", DUT.blk.ve2[0]);
-      $display(" ve1 = %b", DUT.blk.ve2[1]);
-      $display(" ve2 = %b", DUT.blk.ve2[2]);
-      $display(" ve3 = %b", DUT.blk.ve2[3]);
-      $display(" he0 = %b", DUT.blk.he2[0]);
-      $display(" he1 = %b", DUT.blk.he2[1]);
-      $display(" he2 = %b", DUT.blk.he2[2]);
-      $display(" he3 = %b", DUT.blk.he2[3]);
-      $display(" he4 = %b", DUT.blk.he2[4]);
-      $display(" he5 = %b", DUT.blk.he2[5]);
-      $display(" he6 = %b", DUT.blk.he2[6]);
-      $display(" he7 = %b", DUT.blk.he2[7]);
+      $display(" he8  = %b", DUT.blk.he[8]);
+      $display(" he9  = %b", DUT.blk.he[9]);
+      $display(" he10 = %b", DUT.blk.he[10]);
+      $display(" he11 = %b", DUT.blk.he[11]);
+      $display(" he12 = %b", DUT.blk.he[12]);
+      $display(" he13 = %b", DUT.blk.he[13]);
+      $display(" he14 = %b", DUT.blk.he[14]);
+      $display(" he15 = %b", DUT.blk.he[15]);
+      $display(" he16 = %b", DUT.blk.he[16]);
       // increment array index and read next testvector
     vectornum= vectornum + 1;
     $display("testing vector %d next", vectornum);