)]}'
{
  "commit": "02b06a9f56d4b42f9bcee1a2df5899b38918b0af",
  "tree": "0991508844c05b0df7aad78b913c973be2248acd",
  "parents": [
    "fa6de9f1d8d95ccc433d46a361eb9d9389a1591e"
  ],
  "author": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Wed Nov 25 18:38:42 2020 +0200"
  },
  "committer": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Wed Nov 25 18:38:42 2020 +0200"
  },
  "message": "Minor RTL fixes, switching to wrapped GPIOV2\n\n- use USER2_ABUTMENT_PINS for the second of the vssio and vddio pads\n- do core-facing power-to-signal connections using the auto-router\n- fix corner pad power connections and keep them for LVS purposes\n- add a bunch of missing USE_POWER_PINS guards\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "130a35ce92bc967b69af4328783a645113bc3b99",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "d895d2c5719c3620ef518039ee90190679f83f61",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "b8ba7f142cdc8361f775a5fb7bcab914f12405d1",
      "old_mode": 33188,
      "old_path": "verilog/rtl/chip_io.v",
      "new_id": "44fa93f43ee30041517386d1c8ba3a9010803e31",
      "new_mode": 33188,
      "new_path": "verilog/rtl/chip_io.v"
    },
    {
      "type": "modify",
      "old_id": "d8cb4490bd8766e70d7bea504675e24aa9c3cd3b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mprj_io.v",
      "new_id": "ad59c18db6b61e7904874a951537a98239405925",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mprj_io.v"
    },
    {
      "type": "modify",
      "old_id": "d56999ad29dfc44294e7086d61b5878810f529a4",
      "old_mode": 33188,
      "old_path": "verilog/rtl/pads.v",
      "new_id": "0e914b62e11104aafe3c7eaa8383acb1b277783b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/pads.v"
    },
    {
      "type": "modify",
      "old_id": "55461305ff2f6eeebf2175a9cbf5c336029c8607",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_proj_example.v",
      "new_id": "3445aa06a6d74493ba3e51857515b41ce4493322",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_proj_example.v"
    },
    {
      "type": "modify",
      "old_id": "b5460f5058c88c76bf97fa49d9b18eaac0467d88",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "0b23a5048299818d7940f3b12943a6f39c5c8be9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}
