diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
index 159efd5..bc8dbc3 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
@@ -66,9 +66,12 @@
 	// Configure LA probes [31:0], [127:64] as inputs to the cpu 
 	// Configure LA probes [63:32] as outputs from the cpu
 	reg_la0_ena = 0xFFFFFFFF;    // [31:0]
-	reg_la1_ena = 0x00000000;    // [63:32]
-	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
+	reg_la1_ena = 0x00000000;    // [95:64]
+	reg_la2_ena = 0x00000000;    // [63:32]
 	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
 
+	// Set Counter value to zero through LA probes [63:32]
+	reg_la2_data = 0x00000002;
+
 }
 
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index ccbbb35..3528f47 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -49,12 +49,10 @@
 	// simulation.  Normally this would be a slow clock and the digital PLL
 	// would be the fast clock.
 
-	always #5 clock <= (clock === 1'b0);
-	always #20 step <= !step;
+	always #12.5 clock <= (clock === 1'b0);
 
 	initial begin
 		clock = 0;
-		step = 0;
 	end
 
 	initial begin
@@ -127,31 +125,6 @@
 	wire USER_VDD1V8 = power4;
 	wire VSS = 1'b0;
 
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (USER_VDD3V3),
-		.vdda2    (USER_VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (USER_VDD1V8),
-		.vccd2	  (USER_VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-        	.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
 
     reg                 step;
     reg                 dir;
@@ -179,18 +152,6 @@
     wire            phase_b2_h;
 	wire 			resetn;
 
-
-	spiflash #(
-		.FILENAME("io_ports.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
 //	assign CHARGEPUMP		= mprj_io[15];
 	assign analog_out1		= mprj_io[27];
 	assign analog_out2		= mprj_io[28];
@@ -217,7 +178,7 @@
 //	assign mprj_io[22]		= COPI;
 	assign mprj_io[32]		= step;
 	assign mprj_io[33]		= dir;
-	assign resetn = ~RSTB;
+	assign resetn = RSTB;
 
     always @(posedge clock) begin
         if (!resetn) begin
@@ -254,6 +215,43 @@
         end
     end
 
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (USER_VDD3V3),
+		.vdda2    (USER_VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (USER_VDD1V8),
+		.vccd2	  (USER_VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+
+	spiflash #(
+		.FILENAME("io_ports.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
     pwm_duty duty1(
         .clk(clock),
         .resetn(resetn),
diff --git a/verilog/rtl/rapcore_caravel.v b/verilog/rtl/rapcore_caravel.v
index c1147f8..fdb979e 100644
--- a/verilog/rtl/rapcore_caravel.v
+++ b/verilog/rtl/rapcore_caravel.v
@@ -20,7 +20,7 @@
  *-------------------------------------------------------------
  */
 
-module rapcores #(
+module rapcore_caravel #(
     parameter BITS = 32
 )(
 `ifdef USE_POWER_PINS
@@ -87,8 +87,8 @@
     // Assuming LA probes [63:32] are for controlling the count register
     assign la_write = ~la_oen[63:32] & ~{BITS{valid}};
     // Assuming LA probes [65:64] are for controlling the count clk & reset
-    assign clk = wb_clk_i;
-    assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;
+    assign clk = (~la_oen[64]) ? la_data_in[64]: wb_clk_i;
+    assign rst = ~la_oen[65] && la_data_in[65] && ~wb_rst_i;
 
     // GPIO output enable (0 = output, 1 = input)
     assign io_oeb[15] = 1'b0;    // CHARGEPUMP
@@ -136,19 +136,20 @@
 
 		wire resetn;
     reg [12:0] resetn_counter = 0;
-		assign resetn = &resetn_counter;
+		assign resetn = &resetn_counter && rst;
 
 		always @(posedge wb_clk_i) begin
-		  if (!resetn && !wb_rst_i) resetn_counter <= resetn_counter +1;
+		  if (!resetn && !wb_rst_i && rst) resetn_counter <= resetn_counter +1;
 		end
 
     // IO
-    assign io_out[7:0] = resetn_counter[7:0]; //count;
+    assign io_out[7:0] = resetn_counter[12:5]; //count;
 
     rapcore rapcore0 (
 
         // IO Pads
         .CLK(wb_clk_i),
+        .resetn_in(resetn),
         .CHARGEPUMP(io_out[15]),
         .analog_cmp1(io_in[25]),
         .analog_out1(io_out[27]),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index b6e1d4f..271a862 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -64,7 +64,7 @@
     /* User project is instantiated  here   */
     /*--------------------------------------*/
 
-    rapcores rapcores0 (
+    rapcore_caravel rapcore_caravel0 (
 
 `ifndef SIM
     `ifdef USE_POWER_PINS