diff --git a/openlane/rapcores/config.tcl b/openlane/rapcores/config.tcl
index 566a428..5cf07a9 100644
--- a/openlane/rapcores/config.tcl
+++ b/openlane/rapcores/config.tcl
@@ -32,9 +32,12 @@
 set ::env(DIE_AREA) "0 0 650 650"
 
 # use the empty wrapper to help pin placement
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-set ::env(FP_CONTEXT_DEF) $script_dir/../user_project_wrapper_empty/runs/user_project_wrapper_empty/tmp/floorplan/ioPlacer.def
-set ::env(FP_CONTEXT_LEF) $script_dir/../user_project_wrapper_empty/runs/user_project_wrapper_empty/tmp/merged_unpadded.lef
+#set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+#set ::env(FP_CONTEXT_DEF) $script_dir/../user_project_wrapper_empty/runs/user_project_wrapper_empty/tmp/floorplan/ioPlacer.def
+#set ::env(FP_CONTEXT_LEF) $script_dir/../user_project_wrapper_empty/runs/user_project_wrapper_empty/tmp/merged_unpadded.lef
+
+# Since we use all the same pin names reuse the wrapper pin arrangement.
+set ::env(FP_PIN_ORDER_CFG) $script_dir/../user_project_wrapper_empty/pin_order.cfg
 
 # Some config for hardening
 set ::env(DESIGN_IS_CORE) 0
@@ -56,8 +59,12 @@
 set ::env(ROUTING_CORES) 6
 #set ::env(GLB_RT_ALLOW_CONGESTION) 1
 
+set ::env(_VDD_NET_NAME) vccd1
+set ::env(_GND_NET_NAME) vssd1
 set ::env(VDD_NETS) [list {vccd1}]
 set ::env(GND_NETS) [list {vssd1}]
+set ::env(VDD_PIN) vccd1
+set ::env(GND_PIN) vssd1
 
 # block met5 with obstruction
 set ::env(GLB_RT_OBS) "met5 0 0 1000 1000"
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index ea7bc3a..41a4af8 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -63,6 +63,10 @@
 set ::env(TAP_DECAP_INSERTION) 0
 set ::env(CLOCK_TREE_SYNTH) 0
 
+set ::env(MAGIC_GENERATE_LEF) 0
+set ::env(RUN_SPEF_EXTRACTION) 0
+set ::env(GLB_RT_OBS) "li1 0 0 2920 3520"
+set ::env(GLB_RT_MINLAYER) 2
 
 # Area Configurations. DON'T TOUCH.
 set ::env(FP_SIZING) absolute
@@ -86,15 +90,20 @@
 set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
 set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
 
-set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
-set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+#set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
+#set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(VDD_NETS) vccd1
+set ::env(GND_NETS) vssd1
+set ::env(VDD_PIN) vccd1
+set ::env(GND_PIN) vssd1
+
 set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
 
 set ::env(RUN_CVC) 0
 
 # Pin Configurations. DON'T TOUCH
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-set ::env(FP_DEF_TEMPLATE) $script_dir/../../def/user_project_wrapper_empty.def
+#set ::env(FP_DEF_TEMPLATE) $script_dir/../../def/user_project_wrapper_empty.def
 set ::unit 2.4
 set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
 set ::env(FP_IO_HEXTEND) [expr 2*$::unit]