)]}'
{
  "commit": "905a69d33f791cbe4f5523da521ee4b5967deef8",
  "tree": "826281340bf2e7207c250bdf7d6a035120b8b796",
  "parents": [
    "fc7894b55ad9040adc8b270a7306e2f441a45587"
  ],
  "author": {
    "name": "Steve Kelly",
    "email": "kd2cca@gmail.com",
    "time": "Fri Dec 18 23:15:40 2020 -0500"
  },
  "committer": {
    "name": "Steve Kelly",
    "email": "kd2cca@gmail.com",
    "time": "Fri Dec 18 23:15:40 2020 -0500"
  },
  "message": "pull missing mprj verilog from mpw-one-b\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "9eba5492c4d3b22f38bca019d800f902b0f96395",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/gpio/Makefile",
      "new_id": "0a97393cd03d805624b98aebfa079c9a80a33aca",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "24cda908b20ef14d7a5e9aeb4859529541023a3a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mprj_logic_high.v"
    }
  ]
}