diff --git a/openlane/rapcores/config.tcl b/openlane/rapcores/config.tcl
index 338e3ea..633e537 100644
--- a/openlane/rapcores/config.tcl
+++ b/openlane/rapcores/config.tcl
@@ -5,7 +5,7 @@
 set ::env(VERILOG_FILES) "\
         $script_dir/../../verilog/rtl/defines.v \
         $script_dir/../../rapcores/src/constants.v \
-        $script_dir/../../rapcore_caravel_defines.v \
+        $script_dir/../../rapcores/boards/mpw_one_defines.v \
         $script_dir/../../rapcores/src/macro_params.v \
         $script_dir/../../rapcores/src/spi_state_machine.v \
         $script_dir/../../rapcores/src/dda_timer.v \
diff --git a/openlane/rapcores/pin_order.cfg b/openlane/rapcores/pin_order.cfg
index ccb7d40..6de1406 100644
--- a/openlane/rapcores/pin_order.cfg
+++ b/openlane/rapcores/pin_order.cfg
@@ -1,3 +1,157 @@
 #BUS_SORT
+#NR
+analog_io\[15\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+analog_io\[16\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+analog_io\[17\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+analog_io\[18\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+analog_io\[19\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+analog_io\[20\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+analog_io\[21\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+analog_io\[22\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+analog_io\[23\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
 
 #S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+
+#E
+analog_io\[0\]
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+analog_io\[1\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+analog_io\[2\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+analog_io\[3\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+analog_io\[4\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+analog_io\[5\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+analog_io\[6\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+analog_io\[7\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+analog_io\[8\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+analog_io\[9\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+analog_io\[10\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+analog_io\[11\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+analog_io\[12\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+analog_io\[13\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+analog_io\[14\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+analog_io\[24\]
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+analog_io\[25\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+analog_io\[26\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+analog_io\[27\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+analog_io\[28\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+analog_io\[29\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+analog_io\[30\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
diff --git a/rapcore_caravel_defines.v b/rapcore_caravel_defines.v
deleted file mode 100644
index ed63518..0000000
--- a/rapcore_caravel_defines.v
+++ /dev/null
@@ -1,34 +0,0 @@
-
-// Enable SPI Interface
-`define SPI_INTERFACE
-
-// Use PLL for higher SPI frequencies
-//`define SPIPLL
-
-// Enable Buffer DTR pin
-`define BUFFER_DTR
-
-// Enable Move Done Pin
-`define MOVE_DONE
-
-// Enable Halt Input
-`define HALT
-
-// Motor Definitions
-//`define DUAL_HBRIDGE 1
-`define ULTIBRIDGE 1
-
-// Encoder Count
-`define QUAD_ENC 1
-
-// External Step/DIR Input
-`define STEPINPUT
-
-// Output Step/DIR signals
-`define STEPOUTPUT
-
-// Enable RESETN
-`define RESETN
-
-// Change the Move Buffer Size. Should be power of two
-//`define MOVE_BUFFER_SIZE 4
diff --git a/rapcores b/rapcores
index e82fea6..4f60942 160000
--- a/rapcores
+++ b/rapcores
@@ -1 +1 @@
-Subproject commit e82fea688adc9a6e2efc8dc312fe2d3f38623ba7
+Subproject commit 4f609427c53d898e63eed80f21e035199dddc017
diff --git a/verilog/rtl/rapcores.v b/verilog/rtl/rapcores.v
index 491d5bd..15640ba 100644
--- a/verilog/rtl/rapcores.v
+++ b/verilog/rtl/rapcores.v
@@ -43,10 +43,10 @@
     input wbs_cyc_i,
     input wbs_we_i,
     input [3:0] wbs_sel_i,
-    input [31:0] wbs_dat_i,
-    input [31:0] wbs_adr_i,
+    //input [31:0] wbs_dat_i,
+    //input [31:0] wbs_adr_i,
     output wbs_ack_o,
-    output [31:0] wbs_dat_o,
+    //output [31:0] wbs_dat_o,
 
     // Logic Analyzer Signals
     input  [127:0] la_data_in,
@@ -67,8 +67,8 @@
     wire [`MPRJ_IO_PADS-1:0] io_out;
     wire [`MPRJ_IO_PADS-1:0] io_oeb;
 
-    wire [31:0] rdata;
-    wire [31:0] wdata;
+    //wire [31:0] rdata;
+    //wire [31:0] wdata;
     wire [BITS-1:0] count;
 
     wire valid;
@@ -78,8 +78,8 @@
     // WB MI A
     assign valid = wbs_cyc_i && wbs_stb_i;
     assign wstrb = wbs_sel_i & {4{wbs_we_i}};
-    assign wbs_dat_o = rdata;
-    assign wdata = wbs_dat_i;
+    //assign wbs_dat_o = rdata;
+    //assign wdata = wbs_dat_i;
 
     // IO
     //assign io_out = count;
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 6e33af2..1515543 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -104,10 +104,10 @@
 	.wbs_stb_i(wbs_stb_i),
 	.wbs_we_i(wbs_we_i),
 	.wbs_sel_i(wbs_sel_i),
-	.wbs_adr_i(wbs_adr_i),
-	.wbs_dat_i(wbs_dat_i),
+	//.wbs_adr_i(wbs_adr_i),
+	//.wbs_dat_i(wbs_dat_i),
 	.wbs_ack_o(wbs_ack_o),
-	.wbs_dat_o(wbs_dat_o),
+	//.wbs_dat_o(wbs_dat_o),
 
 	// Logic Analyzer