diff --git a/verilog/rtl/rapcores.v b/verilog/rtl/rapcores.v
index 491d5bd..15640ba 100644
--- a/verilog/rtl/rapcores.v
+++ b/verilog/rtl/rapcores.v
@@ -43,10 +43,10 @@
     input wbs_cyc_i,
     input wbs_we_i,
     input [3:0] wbs_sel_i,
-    input [31:0] wbs_dat_i,
-    input [31:0] wbs_adr_i,
+    //input [31:0] wbs_dat_i,
+    //input [31:0] wbs_adr_i,
     output wbs_ack_o,
-    output [31:0] wbs_dat_o,
+    //output [31:0] wbs_dat_o,
 
     // Logic Analyzer Signals
     input  [127:0] la_data_in,
@@ -67,8 +67,8 @@
     wire [`MPRJ_IO_PADS-1:0] io_out;
     wire [`MPRJ_IO_PADS-1:0] io_oeb;
 
-    wire [31:0] rdata;
-    wire [31:0] wdata;
+    //wire [31:0] rdata;
+    //wire [31:0] wdata;
     wire [BITS-1:0] count;
 
     wire valid;
@@ -78,8 +78,8 @@
     // WB MI A
     assign valid = wbs_cyc_i && wbs_stb_i;
     assign wstrb = wbs_sel_i & {4{wbs_we_i}};
-    assign wbs_dat_o = rdata;
-    assign wdata = wbs_dat_i;
+    //assign wbs_dat_o = rdata;
+    //assign wdata = wbs_dat_i;
 
     // IO
     //assign io_out = count;
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 6e33af2..1515543 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -104,10 +104,10 @@
 	.wbs_stb_i(wbs_stb_i),
 	.wbs_we_i(wbs_we_i),
 	.wbs_sel_i(wbs_sel_i),
-	.wbs_adr_i(wbs_adr_i),
-	.wbs_dat_i(wbs_dat_i),
+	//.wbs_adr_i(wbs_adr_i),
+	//.wbs_dat_i(wbs_dat_i),
 	.wbs_ack_o(wbs_ack_o),
-	.wbs_dat_o(wbs_dat_o),
+	//.wbs_dat_o(wbs_dat_o),
 
 	// Logic Analyzer