diff --git a/verilog/rtl/manifest b/verilog/rtl/manifest
index f4886fb..4cdf2f2 100644
--- a/verilog/rtl/manifest
+++ b/verilog/rtl/manifest
@@ -1,5 +1,5 @@
 b2feeb2a098894d5d731a5b011858a471e855d73  caravel_clocking.v
-8a0bcbd870778416bb4e753909053881aca2368a  caravel.v
+c14d409e770072aea15b399c7c71bcb47e5a9bec  caravel.v
 38d2c674ea1f696bf2c9deaeee5f9b044f2445fb  chip_io.v
 d772308bd2a72121d7ed9dcdd40c8e6cbbe4b43c  clock_div.v
 f937b52e53d45bdbe41bcbd07c65b41104c21756  convert_gpio_sigs.v
@@ -16,13 +16,13 @@
 ff3e65a783f3807340e25efac9207787d39fb6cd  mem_wb.v
 65feb79043201d3609307a3dd5af4e75cc26e81b  mgmt_core.v
 f656dadb49cb97a46aada3d37a86a12f565e6e9e  mgmt_protect_hv.v
-85dec445f0cf7afbef4aa6b919d31f0f5c9a0b7e  mgmt_protect.v
+4d42909e102c472504739bc37559c6a34fd85ae1  mgmt_protect.v
 20a482029168de93693a92ce03c00ec16e7b4776  mgmt_soc.v
+489b31e48e0ba327b6a70748fee664406c58f7a0  mprj2_logic_high.v
 93eb7aa0f8489715145ff0870737fecf8be1fa8c  mprj_ctrl.v
 b16ace2e7a9c02ed5f8f918fe9e4a460422c7304  mprj_io.v
+98bd1d468969f47c370eb54ea8f178105953c8c9  mprj_logic_high.v
 1352e5821905dce0b8203e9bee5e1adff02a9cbc  pads.v
-5bcc269abdab76a7ddab2bee29f8032f97668043  parser.out
-b6e2bd2762a572fbf0f123412bfa7384827cc38b  parsetab.py
 5f1d9a90287fa5ae6635933c287e8e9e3e39931a  picorv32.v
 669d16642d5dd5f6824812754db20db98c9fe17b  ring_osc2x13.v
 6864cc10dacfd3edb4c66825b7a301ab097cea0d  simple_por.v