)]}'
{
  "commit": "34fa3d15b40854a13e662b1c66344a40f0c73599",
  "tree": "1a4ba2c01ccd5412eb215285ae4cf66a1142c8a1",
  "parents": [
    "5906a0fe2d4d6cd059fbff9389800609cd29c9ef"
  ],
  "author": {
    "name": "johnnyr",
    "email": "johnny@ultimachine.com",
    "time": "Sat Dec 19 00:30:36 2020 -0600"
  },
  "committer": {
    "name": "johnnyr",
    "email": "johnny@ultimachine.com",
    "time": "Sat Dec 19 00:30:36 2020 -0600"
  },
  "message": "missing mprj2 file\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "f57f173942e7bcb488b9f2af96cfb53315dc96b1",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mprj2_logic_high.v"
    }
  ]
}