diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
index ace6004..159efd5 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
@@ -63,5 +63,12 @@
         reg_mprj_xfer = 1;
         while (reg_mprj_xfer == 1);
 
+	// Configure LA probes [31:0], [127:64] as inputs to the cpu 
+	// Configure LA probes [63:32] as outputs from the cpu
+	reg_la0_ena = 0xFFFFFFFF;    // [31:0]
+	reg_la1_ena = 0x00000000;    // [63:32]
+	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
+	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
+
 }