diff --git a/openlane/digital_pll/config.tcl b/openlane/digital_pll/config.tcl
new file mode 100644
index 0000000..faa4d1b
--- /dev/null
+++ b/openlane/digital_pll/config.tcl
@@ -0,0 +1,21 @@
+set script_dir [file dirname [file normalize [info script]]]
+# User config
+set ::env(DESIGN_NAME) digital_pll
+
+# Change if needed
+set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/digital_pll.v
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+# Fill this
+set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+set ::env(SYNTH_BUFFERING) 0
+set ::env(SYNTH_SIZING) 0
+
+set ::env(CELL_PAD) 8
+
+set ::env(FP_CORE_UTIL) 60
+set ::env(PL_TARGET_DENSITY) 0.60
+set ::env(SYNTH_MAX_FANOUT) 6
diff --git a/openlane/digital_pll/pdn.tcl b/openlane/digital_pll/pdn.tcl
new file mode 100644
index 0000000..edd041e
--- /dev/null
+++ b/openlane/digital_pll/pdn.tcl
@@ -0,0 +1,29 @@
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+    }
+    connect {{met1 met4}}
+}
+
+
+set ::halo 0
+
+# Metal layer for rails on every row
+set ::rails_mlayer "met1" ;
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
+
diff --git a/openlane/mgmt_core/config.tcl b/openlane/mgmt_core/config.tcl
new file mode 100644
index 0000000..af7808e
--- /dev/null
+++ b/openlane/mgmt_core/config.tcl
@@ -0,0 +1,37 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) mgmt_core
+
+set ::env(CLOCK_PORT) "core_clk"
+set ::env(CLOCK_PERIOD) "50"
+
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+#set ::env(FP_CORE_UTIL) 40
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2700 2000"
+
+
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
+set ::env(PL_TARGET_DENSITY) 0.3
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
+
+
+set ::env(GLB_RT_ADJUSTMENT) 0
+#set ::env(GLB_RT_TILES) 12
+
+set ::env(DIODE_INSERTION_STRATEGY) 1
+
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../verilog/rtl/clock_div.v\
+	$script_dir/../../verilog/rtl/caravel_clocking.v\
+	$script_dir/../../verilog/rtl/mgmt_core.v\
+	$script_dir/../../verilog/rtl/mgmt_soc.v\
+	$script_dir/../../verilog/rtl/housekeeping_spi.v"
+
+# The removal of this pending the IO verilog files being parsable by yosys...
+set ::env(VERILOG_FILES_BLACKBOX) "$script_dir/../../verilog/rtl/digital_pll.v"
+
+set ::env(EXTRA_LEFS) "$script_dir/../../lef/digital_pll.lef"
+set ::env(EXTRA_GDS_FILES) "$script_dir/../../gds/digital_pll.gds"
diff --git a/openlane/mgmt_core/macro_placement.cfg b/openlane/mgmt_core/macro_placement.cfg
new file mode 100644
index 0000000..a472af1
--- /dev/null
+++ b/openlane/mgmt_core/macro_placement.cfg
@@ -0,0 +1 @@
+pll 665.460 756.05500 N
diff --git a/openlane/mgmt_core/pdn.tcl b/openlane/mgmt_core/pdn.tcl
new file mode 100644
index 0000000..5ed65a9
--- /dev/null
+++ b/openlane/mgmt_core/pdn.tcl
@@ -0,0 +1,35 @@
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    instance "pll"
+    power_pins "VPWR"
+    ground_pins "VGND"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 10
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/mgmt_core/pin_order.cfg b/openlane/mgmt_core/pin_order.cfg
new file mode 100644
index 0000000..88bd4a6
--- /dev/null
+++ b/openlane/mgmt_core/pin_order.cfg
@@ -0,0 +1,23 @@
+#BUS_SORT
+#N
+la_.*
+mgmt_.*
+mprj.*
+
+#S
+resetb
+clock
+flash_csb.*
+flash_clk.*
+flash_io0.*
+flash_io1.*
+gpio.*
+
+#E
+core_.*
+jtag.*
+sdo.*
+
+#W
+user_.*
+mask_rev.*
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
new file mode 100644
index 0000000..91dca3c
--- /dev/null
+++ b/openlane/user_project_wrapper/config.tcl
@@ -0,0 +1,16 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) user_project_wrapper
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/user_project_wrapper.v $script_dir/../../verilog/rtl/user_proj_example.v"
+
+set ::env(CLOCK_PORT) "user_clock2"
+set ::env(CLOCK_NET) "mprj.clk"
+
+set ::env(CLOCK_PERIOD) "10"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2700 2700"
+set ::env(PL_TARGET_DENSITY) 0.001
+
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
new file mode 100644
index 0000000..70640e0
--- /dev/null
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -0,0 +1,136 @@
+#BUS_SORT
+#NR
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+vssa1
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+vssa1
+vssd1
+vdda1
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+vdda1
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+vccd1
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+vccd2
+vssa2
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+vdda2
+vssd2
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]