
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /project/openlane/storage/../../verilog/rtl/sram_1rw1r_32_256_8_sky130.v
Parsing Verilog input from `/project/openlane/storage/../../verilog/rtl/sram_1rw1r_32_256_8_sky130.v' to AST representation.
Generating RTLIL representation for module `\sram_1rw1r_32_256_8_sky130'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /project/openlane/storage/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/storage/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /project/openlane/storage/../../verilog/rtl/storage.v
Parsing Verilog input from `/project/openlane/storage/../../verilog/rtl/storage.v' to AST representation.
Generating RTLIL representation for module `\storage'.
Successfully finished Verilog frontend.

4. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/storage/runs/storage/tmp/synthesis/hierarchy.dot'.
Dumping module storage to page 1.

5. Executing HIERARCHY pass (managing design hierarchy).

5.1. Analyzing design hierarchy..
Top module:  \storage

5.2. Analyzing design hierarchy..
Top module:  \storage
Removed 0 unused modules.

6. Printing statistics.

=== storage ===

   Number of wires:                 10
   Number of wire bits:            158
   Number of public wires:          10
   Number of public wire bits:     158
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     sram_1rw1r_32_256_8_sky130      2

7. Executing SPLITNETS pass (splitting up multi-bit signals).

8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \storage..

9. Executing CHECK pass (checking for obvious problems).
checking module storage..
found and reported 0 problems.

10. Printing statistics.

=== storage ===

   Number of wires:                 10
   Number of wire bits:            158
   Number of public wires:          10
   Number of public wire bits:     158
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     sram_1rw1r_32_256_8_sky130      2

   Area for cell type \sram_1rw1r_32_256_8_sky130 is unknown!

11. Executing Verilog backend.
Dumping module `\storage'.

End of script. Logfile hash: 7d2f9b738c, CPU: user 0.05s system 0.00s, MEM: 12.84 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 72% 2x stat (0 sec), 13% 6x read_verilog (0 sec), ...