
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/defines.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/DFFRAM.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/DFFRAM.v' to AST representation.
Generating RTLIL representation for module `\DFFRAM'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/digital_pll.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/digital_pll.v' to AST representation.
Generating RTLIL representation for module `\digital_pll_controller'.
Generating RTLIL representation for module `\delay_stage'.
Generating RTLIL representation for module `\start_stage'.
Generating RTLIL representation for module `\ring_osc2x13'.
Generating RTLIL representation for module `\digital_pll'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/defines.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v' to AST representation.
Generating RTLIL representation for module `\storage_bridge_wb'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/clock_div.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v' to AST representation.
Generating RTLIL representation for module `\clock_div'.
Generating RTLIL representation for module `\odd'.
Generating RTLIL representation for module `\even'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v' to AST representation.
Generating RTLIL representation for module `\caravel_clocking'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/mgmt_core.v' to AST representation.
Generating RTLIL representation for module `\mgmt_core'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:192)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:193)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:198)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:162)
Generating RTLIL representation for module `\picorv32'.
Generating RTLIL representation for module `\picorv32_regs'.
Generating RTLIL representation for module `\picorv32_pcpi_mul'.
Generating RTLIL representation for module `\picorv32_pcpi_fast_mul'.
Generating RTLIL representation for module `\picorv32_pcpi_div'.
Generating RTLIL representation for module `\picorv32_axi'.
Generating RTLIL representation for module `\picorv32_axi_adapter'.
Generating RTLIL representation for module `\picorv32_wb'.
Generating RTLIL representation for module `\spimemio_wb'.
Generating RTLIL representation for module `\spimemio'.
Generating RTLIL representation for module `\spimemio_xfer'.
Generating RTLIL representation for module `\simpleuart_wb'.
Generating RTLIL representation for module `\simpleuart'.
Generating RTLIL representation for module `\simple_spi_master_wb'.
Generating RTLIL representation for module `\simple_spi_master'.
Generating RTLIL representation for module `\counter_timer_high_wb'.
Generating RTLIL representation for module `\counter_timer_high'.
Generating RTLIL representation for module `\counter_timer_low_wb'.
Generating RTLIL representation for module `\counter_timer_low'.
Generating RTLIL representation for module `\wb_intercon'.
Generating RTLIL representation for module `\mem_wb'.
Generating RTLIL representation for module `\soc_mem'.
Generating RTLIL representation for module `\gpio_wb'.
Generating RTLIL representation for module `\gpio'.
Generating RTLIL representation for module `\sysctrl_wb'.
Generating RTLIL representation for module `\sysctrl'.
Generating RTLIL representation for module `\la_wb'.
Generating RTLIL representation for module `\la'.
Generating RTLIL representation for module `\mprj_ctrl_wb'.
Generating RTLIL representation for module `\mprj_ctrl'.
Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:270
Generating RTLIL representation for module `\convert_gpio_sigs'.
Generating RTLIL representation for module `\mgmt_soc'.
Generating RTLIL representation for module `\mgmt_soc_regs'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v
Parsing SystemVerilog input from `/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:129)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:130)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:131)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:133)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:134)
Warning: Yosys has only limited support for tri-state logic at the moment. (/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:135)
Generating RTLIL representation for module `\housekeeping_spi'.
Generating RTLIL representation for module `\housekeeping_spi_slave'.
Successfully finished Verilog frontend.

11. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/mgmt_core/runs/mgmt_core/tmp/synthesis/hierarchy.dot'.
Dumping module mgmt_core to page 1.

12. Executing HIERARCHY pass (managing design hierarchy).

12.1. Analyzing design hierarchy..
Top module:  \mgmt_core
Used module:     \housekeeping_spi
Used module:         \housekeeping_spi_slave
Used module:     \mgmt_soc
Used module:         \wb_intercon
Used module:         \storage_bridge_wb
Used module:         \mem_wb
Used module:             \soc_mem
Used module:         \mprj_ctrl_wb
Used module:             \mprj_ctrl
Used module:         \la_wb
Used module:             \la
Used module:         \sysctrl_wb
Used module:             \sysctrl
Used module:         \gpio_wb
Used module:             \gpio
Used module:         \counter_timer_high_wb
Used module:             \counter_timer_high
Used module:         \counter_timer_low_wb
Used module:             \counter_timer_low
Used module:         \simple_spi_master_wb
Used module:             \simple_spi_master
Used module:         \simpleuart_wb
Used module:             \simpleuart
Used module:         \spimemio_wb
Used module:             \spimemio
Used module:                 \spimemio_xfer
Used module:         \picorv32_wb
Used module:             \picorv32
Used module:                 \mgmt_soc_regs
Used module:         \convert_gpio_sigs
Used module:     \caravel_clocking
Used module:         \clock_div
Used module:             \odd
Used module:             \even
Parameter \SIZE = 3

12.2. Executing AST frontend in derive mode using pre-parsed AST for module `\clock_div'.
Parameter \SIZE = 3
Generating RTLIL representation for module `$paramod\clock_div\SIZE=3'.
Parameter \SIZE = 3
Found cached RTLIL representation for module `$paramod\clock_div\SIZE=3'.
Parameter \DW = 32
Parameter \AW = 32
Parameter \NS = 14
Parameter \ADR_MASK = 448'1111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000
Parameter \SLAVE_ADR = 448'0010111100000000000000000000000000101101000000000000000000000000001100000000000000000000000000000010011000000000000000000000000000100101000000000000000000000000001001000000000000000000000000000010001100000000000000000000000000100010000000000000000000000000001000010000000000000000000000000010000000000000000000000000000000010000000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000000000000000000000000000

12.3. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_intercon'.
Parameter \DW = 32
Parameter \AW = 32
Parameter \NS = 14
Parameter \ADR_MASK = 448'1111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000111111110000000000000000000000001111111100000000000000000000000011111111000000000000000000000000
Parameter \SLAVE_ADR = 448'0010111100000000000000000000000000101101000000000000000000000000001100000000000000000000000000000010011000000000000000000000000000100101000000000000000000000000001001000000000000000000000000000010001100000000000000000000000000100010000000000000000000000000001000010000000000000000000000000010000000000000000000000000000000010000000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
Generating RTLIL representation for module `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon'.
Parameter \RW_BLOCKS_ADR = 48'000100000000000000000000000000000000000000000000
Parameter \RO_BLOCKS_ADR = 24'000000000000000000000000

12.4. Executing AST frontend in derive mode using pre-parsed AST for module `\storage_bridge_wb'.
Parameter \RW_BLOCKS_ADR = 48'000100000000000000000000000000000000000000000000
Parameter \RO_BLOCKS_ADR = 24'000000000000000000000000
Generating RTLIL representation for module `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb'.
Parameter \BASE_ADR = 637534208

12.5. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl_wb'.
Parameter \BASE_ADR = 637534208
Generating RTLIL representation for module `$paramod\mprj_ctrl_wb\BASE_ADR=637534208'.
Parameter \BASE_ADR = 620756992
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100

12.6. Executing AST frontend in derive mode using pre-parsed AST for module `\la_wb'.
Parameter \BASE_ADR = 620756992
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100
Generating RTLIL representation for module `$paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100

12.7. Executing AST frontend in derive mode using pre-parsed AST for module `\sysctrl_wb'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100
Generating RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100

12.8. Executing AST frontend in derive mode using pre-parsed AST for module `\gpio_wb'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100
Generating RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb'.
Parameter \BASE_ADR = 587202560
Parameter \CONFIG = 8'00000000
Parameter \VALUE = 8'00000100
Parameter \DATA = 8'00001000

12.9. Executing AST frontend in derive mode using pre-parsed AST for module `\counter_timer_high_wb'.
Parameter \BASE_ADR = 587202560
Parameter \CONFIG = 8'00000000
Parameter \VALUE = 8'00000100
Parameter \DATA = 8'00001000
Generating RTLIL representation for module `$paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb'.
Parameter \BASE_ADR = 570425344
Parameter \CONFIG = 8'00000000
Parameter \VALUE = 8'00000100
Parameter \DATA = 8'00001000

12.10. Executing AST frontend in derive mode using pre-parsed AST for module `\counter_timer_low_wb'.
Parameter \BASE_ADR = 570425344
Parameter \CONFIG = 8'00000000
Parameter \VALUE = 8'00000100
Parameter \DATA = 8'00001000
Generating RTLIL representation for module `$paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb'.
Parameter \BASE_ADR = 603979776
Parameter \CONFIG = 8'00000000
Parameter \DATA = 8'00000100

12.11. Executing AST frontend in derive mode using pre-parsed AST for module `\simple_spi_master_wb'.
Parameter \BASE_ADR = 603979776
Parameter \CONFIG = 8'00000000
Parameter \DATA = 8'00000100
Generating RTLIL representation for module `$paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100'.
Parameter \BASE_ADR = 536870912
Parameter \CLK_DIV = 8'00000000
Parameter \DATA = 8'00000100

12.12. Executing AST frontend in derive mode using pre-parsed AST for module `\simpleuart_wb'.
Parameter \BASE_ADR = 536870912
Parameter \CLK_DIV = 8'00000000
Parameter \DATA = 8'00000100
Generating RTLIL representation for module `$paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100'.
Parameter \BARREL_SHIFTER = 1
Parameter \COMPRESSED_ISA = 1
Parameter \ENABLE_MUL = 1
Parameter \ENABLE_DIV = 1
Parameter \ENABLE_IRQ = 1
Parameter \ENABLE_IRQ_QREGS = 0
Parameter \PROGADDR_RESET = 268435456
Parameter \PROGADDR_IRQ = 0
Parameter \STACKADDR = 1024

12.13. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32_wb'.
Parameter \BARREL_SHIFTER = 1
Parameter \COMPRESSED_ISA = 1
Parameter \ENABLE_MUL = 1
Parameter \ENABLE_DIV = 1
Parameter \ENABLE_IRQ = 1
Parameter \ENABLE_IRQ_QREGS = 0
Parameter \PROGADDR_RESET = 268435456
Parameter \PROGADDR_IRQ = 0
Parameter \STACKADDR = 1024
Generating RTLIL representation for module `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb'.
Parameter \ENABLE_COUNTERS = 1'1
Parameter \ENABLE_COUNTERS64 = 1'1
Parameter \ENABLE_REGS_16_31 = 1'1
Parameter \ENABLE_REGS_DUALPORT = 1'1
Parameter \TWO_STAGE_SHIFT = 1'1
Parameter \BARREL_SHIFTER = 1'0
Parameter \TWO_CYCLE_COMPARE = 1'0
Parameter \TWO_CYCLE_ALU = 1'0
Parameter \COMPRESSED_ISA = 1'0
Parameter \CATCH_MISALIGN = 1'1
Parameter \CATCH_ILLINSN = 1'1
Parameter \ENABLE_PCPI = 1'0
Parameter \ENABLE_MUL = 1'0
Parameter \ENABLE_FAST_MUL = 1'0
Parameter \ENABLE_DIV = 1'0
Parameter \ENABLE_IRQ = 1'0
Parameter \ENABLE_IRQ_QREGS = 1'1
Parameter \ENABLE_IRQ_TIMER = 1'1
Parameter \ENABLE_TRACE = 1'0
Parameter \REGS_INIT_ZERO = 1'0
Parameter \MASKED_IRQ = 0
Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
Parameter \PROGADDR_RESET = 0
Parameter \PROGADDR_IRQ = 16
Parameter \STACKADDR = 32'11111111111111111111111111111111

12.14. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'.
Parameter \ENABLE_COUNTERS = 1'1
Parameter \ENABLE_COUNTERS64 = 1'1
Parameter \ENABLE_REGS_16_31 = 1'1
Parameter \ENABLE_REGS_DUALPORT = 1'1
Parameter \TWO_STAGE_SHIFT = 1'1
Parameter \BARREL_SHIFTER = 1'0
Parameter \TWO_CYCLE_COMPARE = 1'0
Parameter \TWO_CYCLE_ALU = 1'0
Parameter \COMPRESSED_ISA = 1'0
Parameter \CATCH_MISALIGN = 1'1
Parameter \CATCH_ILLINSN = 1'1
Parameter \ENABLE_PCPI = 1'0
Parameter \ENABLE_MUL = 1'0
Parameter \ENABLE_FAST_MUL = 1'0
Parameter \ENABLE_DIV = 1'0
Parameter \ENABLE_IRQ = 1'0
Parameter \ENABLE_IRQ_QREGS = 1'1
Parameter \ENABLE_IRQ_TIMER = 1'1
Parameter \ENABLE_TRACE = 1'0
Parameter \REGS_INIT_ZERO = 1'0
Parameter \MASKED_IRQ = 0
Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
Parameter \PROGADDR_RESET = 0
Parameter \PROGADDR_IRQ = 16
Parameter \STACKADDR = 32'11111111111111111111111111111111
Generating RTLIL representation for module `$paramod$4d2dfdcc1db1a7362453fb449ccdda75bb1b39f9\picorv32'.
Parameter \WORDS = 256
Parameter \ADR_WIDTH = 8

12.15. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_mem'.
Parameter \WORDS = 256
Parameter \ADR_WIDTH = 8
Generating RTLIL representation for module `$paramod\soc_mem\WORDS=256\ADR_WIDTH=8'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100

12.16. Executing AST frontend in derive mode using pre-parsed AST for module `\gpio'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100
Generating RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100

12.17. Executing AST frontend in derive mode using pre-parsed AST for module `\sysctrl'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100
Generating RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl'.
Parameter \BASE_ADR = 570425344
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_2 = 8'00001000
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100

12.18. Executing AST frontend in derive mode using pre-parsed AST for module `\la'.
Parameter \BASE_ADR = 570425344
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_2 = 8'00001000
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100
Generating RTLIL representation for module `$paramod$499b0a1c054fbe1b70d6dc28b15376e5cd987bff\la'.
Parameter \BASE_ADR = 587202560
Parameter \XFER = 8'00000000
Parameter \PWRDATA = 8'00000100
Parameter \IODATA = 8'00001000
Parameter \IOCONFIG = 8'00100000

12.19. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl'.
Parameter \BASE_ADR = 587202560
Parameter \XFER = 8'00000000
Parameter \PWRDATA = 8'00000100
Parameter \IODATA = 8'00001000
Parameter \IOCONFIG = 8'00100000
Generating RTLIL representation for module `$paramod$ed88d8bd975b89882ecfbd510fe3c5e6ac127a6b\mprj_ctrl'.
Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:270

12.20. Analyzing design hierarchy..
Top module:  \mgmt_core
Used module:     \housekeeping_spi
Used module:         \housekeeping_spi_slave
Used module:     \mgmt_soc
Used module:         $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module:         $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module:         \mem_wb
Used module:             $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module:         $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module:             \mprj_ctrl
Used module:         $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module:             \la
Used module:         $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module:             \sysctrl
Used module:         $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module:             \gpio
Used module:         $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module:             \counter_timer_high
Used module:         $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module:             \counter_timer_low
Used module:         $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module:             \simple_spi_master
Used module:         $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module:             \simpleuart
Used module:         \spimemio_wb
Used module:             \spimemio
Used module:                 \spimemio_xfer
Used module:         $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module:             \picorv32
Used module:                 \mgmt_soc_regs
Used module:         \convert_gpio_sigs
Used module:     \caravel_clocking
Used module:         $paramod\clock_div\SIZE=3
Used module:             \odd
Used module:             \even
Parameter \BASE_ADR = 637534208
Parameter \XFER = 8'00000000
Parameter \PWRDATA = 8'00000100
Parameter \IODATA = 8'00001000
Parameter \IOCONFIG = 8'00100000

12.21. Executing AST frontend in derive mode using pre-parsed AST for module `\mprj_ctrl'.
Parameter \BASE_ADR = 637534208
Parameter \XFER = 8'00000000
Parameter \PWRDATA = 8'00000100
Parameter \IODATA = 8'00001000
Parameter \IOCONFIG = 8'00100000
Generating RTLIL representation for module `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl'.
Warning: Replacing memory \io_ctrl with list of registers. See /project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:270
Parameter \BASE_ADR = 620756992
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_2 = 8'00001000
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100

12.22. Executing AST frontend in derive mode using pre-parsed AST for module `\la'.
Parameter \BASE_ADR = 620756992
Parameter \LA_DATA_0 = 8'00000000
Parameter \LA_DATA_1 = 8'00000100
Parameter \LA_DATA_2 = 8'00001000
Parameter \LA_DATA_3 = 8'00001100
Parameter \LA_ENA_0 = 8'00010000
Parameter \LA_ENA_1 = 8'00010100
Parameter \LA_ENA_2 = 8'00011000
Parameter \LA_ENA_3 = 8'00011100
Generating RTLIL representation for module `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la'.
Parameter \BASE_ADR = 788529152
Parameter \PWRGOOD = 8'00000000
Parameter \CLK_OUT = 8'00000100
Parameter \TRAP_OUT = 8'00001000
Parameter \IRQ_SRC = 8'00001100
Found cached RTLIL representation for module `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl'.
Parameter \BASE_ADR = 553648128
Parameter \GPIO_DATA = 8'00000000
Parameter \GPIO_ENA = 8'00000100
Parameter \GPIO_PU = 8'00001000
Parameter \GPIO_PD = 8'00001100
Found cached RTLIL representation for module `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio'.
Parameter \ENABLE_COUNTERS = 1'1
Parameter \ENABLE_COUNTERS64 = 1'1
Parameter \ENABLE_REGS_16_31 = 1'1
Parameter \ENABLE_REGS_DUALPORT = 1'1
Parameter \TWO_STAGE_SHIFT = 1'1
Parameter \BARREL_SHIFTER = 1'1
Parameter \TWO_CYCLE_COMPARE = 1'0
Parameter \TWO_CYCLE_ALU = 1'0
Parameter \COMPRESSED_ISA = 1'1
Parameter \CATCH_MISALIGN = 1'1
Parameter \CATCH_ILLINSN = 1'1
Parameter \ENABLE_PCPI = 1'0
Parameter \ENABLE_MUL = 1'1
Parameter \ENABLE_FAST_MUL = 1'0
Parameter \ENABLE_DIV = 1'1
Parameter \ENABLE_IRQ = 1'1
Parameter \ENABLE_IRQ_QREGS = 1'0
Parameter \ENABLE_IRQ_TIMER = 1'1
Parameter \ENABLE_TRACE = 1'0
Parameter \REGS_INIT_ZERO = 1'0
Parameter \MASKED_IRQ = 0
Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
Parameter \PROGADDR_RESET = 268435456
Parameter \PROGADDR_IRQ = 0
Parameter \STACKADDR = 1024

12.23. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'.
Parameter \ENABLE_COUNTERS = 1'1
Parameter \ENABLE_COUNTERS64 = 1'1
Parameter \ENABLE_REGS_16_31 = 1'1
Parameter \ENABLE_REGS_DUALPORT = 1'1
Parameter \TWO_STAGE_SHIFT = 1'1
Parameter \BARREL_SHIFTER = 1'1
Parameter \TWO_CYCLE_COMPARE = 1'0
Parameter \TWO_CYCLE_ALU = 1'0
Parameter \COMPRESSED_ISA = 1'1
Parameter \CATCH_MISALIGN = 1'1
Parameter \CATCH_ILLINSN = 1'1
Parameter \ENABLE_PCPI = 1'0
Parameter \ENABLE_MUL = 1'1
Parameter \ENABLE_FAST_MUL = 1'0
Parameter \ENABLE_DIV = 1'1
Parameter \ENABLE_IRQ = 1'1
Parameter \ENABLE_IRQ_QREGS = 1'0
Parameter \ENABLE_IRQ_TIMER = 1'1
Parameter \ENABLE_TRACE = 1'0
Parameter \REGS_INIT_ZERO = 1'0
Parameter \MASKED_IRQ = 0
Parameter \LATCHED_IRQ = 32'11111111111111111111111111111111
Parameter \PROGADDR_RESET = 268435456
Parameter \PROGADDR_IRQ = 0
Parameter \STACKADDR = 1024
Generating RTLIL representation for module `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32'.

12.24. Analyzing design hierarchy..
Top module:  \mgmt_core
Used module:     \housekeeping_spi
Used module:         \housekeeping_spi_slave
Used module:     \mgmt_soc
Used module:         $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module:         $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module:         \mem_wb
Used module:             $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module:         $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module:             $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl
Used module:         $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module:             $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la
Used module:         $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module:             $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl
Used module:         $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module:             $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio
Used module:         $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module:             \counter_timer_high
Used module:         $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module:             \counter_timer_low
Used module:         $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module:             \simple_spi_master
Used module:         $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module:             \simpleuart
Used module:         \spimemio_wb
Used module:             \spimemio
Used module:                 \spimemio_xfer
Used module:         $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module:             $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32
Used module:                 \picorv32_pcpi_div
Used module:                 \picorv32_pcpi_mul
Used module:                 \mgmt_soc_regs
Used module:         \convert_gpio_sigs
Used module:     \caravel_clocking
Used module:         $paramod\clock_div\SIZE=3
Used module:             \odd
Used module:             \even

12.25. Analyzing design hierarchy..
Top module:  \mgmt_core
Used module:     \housekeeping_spi
Used module:         \housekeeping_spi_slave
Used module:     \mgmt_soc
Used module:         $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module:         $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module:         \mem_wb
Used module:             $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module:         $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module:             $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl
Used module:         $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module:             $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la
Used module:         $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module:             $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl
Used module:         $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module:             $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio
Used module:         $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module:             \counter_timer_high
Used module:         $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module:             \counter_timer_low
Used module:         $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module:             \simple_spi_master
Used module:         $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module:             \simpleuart
Used module:         \spimemio_wb
Used module:             \spimemio
Used module:                 \spimemio_xfer
Used module:         $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module:             $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32
Used module:                 \picorv32_pcpi_div
Used module:                 \picorv32_pcpi_mul
Used module:                 \mgmt_soc_regs
Used module:         \convert_gpio_sigs
Used module:     \caravel_clocking
Used module:         $paramod\clock_div\SIZE=3
Used module:             \odd
Used module:             \even
Removing unused module `$paramod$ed88d8bd975b89882ecfbd510fe3c5e6ac127a6b\mprj_ctrl'.
Removing unused module `$paramod$499b0a1c054fbe1b70d6dc28b15376e5cd987bff\la'.
Removing unused module `$paramod$4d2dfdcc1db1a7362453fb449ccdda75bb1b39f9\picorv32'.
Removing unused module `\mprj_ctrl'.
Removing unused module `\mprj_ctrl_wb'.
Removing unused module `\la'.
Removing unused module `\la_wb'.
Removing unused module `\sysctrl'.
Removing unused module `\sysctrl_wb'.
Removing unused module `\gpio'.
Removing unused module `\gpio_wb'.
Removing unused module `\soc_mem'.
Removing unused module `\wb_intercon'.
Removing unused module `\counter_timer_low_wb'.
Removing unused module `\counter_timer_high_wb'.
Removing unused module `\simple_spi_master_wb'.
Removing unused module `\simpleuart_wb'.
Removing unused module `\picorv32_wb'.
Removing unused module `\picorv32_axi_adapter'.
Removing unused module `\picorv32_axi'.
Removing unused module `\picorv32_pcpi_fast_mul'.
Removing unused module `\picorv32_regs'.
Removing unused module `\picorv32'.
Removing unused module `\clock_div'.
Removing unused module `\storage_bridge_wb'.
Removed 25 unused modules.
Mapping positional arguments of cell $paramod\clock_div\SIZE=3.odd_0 (odd).
Mapping positional arguments of cell $paramod\clock_div\SIZE=3.even_0 (even).

13. Executing SYNTH pass.

13.1. Executing HIERARCHY pass (managing design hierarchy).

13.1.1. Analyzing design hierarchy..
Top module:  \mgmt_core
Used module:     \housekeeping_spi
Used module:         \housekeeping_spi_slave
Used module:     \mgmt_soc
Used module:         $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module:         $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module:         \mem_wb
Used module:             $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module:         $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module:             $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl
Used module:         $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module:             $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la
Used module:         $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module:             $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl
Used module:         $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module:             $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio
Used module:         $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module:             \counter_timer_high
Used module:         $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module:             \counter_timer_low
Used module:         $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module:             \simple_spi_master
Used module:         $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module:             \simpleuart
Used module:         \spimemio_wb
Used module:             \spimemio
Used module:                 \spimemio_xfer
Used module:         $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module:             $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32
Used module:                 \picorv32_pcpi_div
Used module:                 \picorv32_pcpi_mul
Used module:                 \mgmt_soc_regs
Used module:         \convert_gpio_sigs
Used module:     \caravel_clocking
Used module:         $paramod\clock_div\SIZE=3
Used module:             \odd
Used module:             \even

13.1.2. Analyzing design hierarchy..
Top module:  \mgmt_core
Used module:     \housekeeping_spi
Used module:         \housekeeping_spi_slave
Used module:     \mgmt_soc
Used module:         $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon
Used module:         $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb
Used module:         \mem_wb
Used module:             $paramod\soc_mem\WORDS=256\ADR_WIDTH=8
Used module:         $paramod\mprj_ctrl_wb\BASE_ADR=637534208
Used module:             $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl
Used module:         $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb
Used module:             $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la
Used module:         $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb
Used module:             $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl
Used module:         $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb
Used module:             $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio
Used module:         $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb
Used module:             \counter_timer_high
Used module:         $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb
Used module:             \counter_timer_low
Used module:         $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100
Used module:             \simple_spi_master
Used module:         $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100
Used module:             \simpleuart
Used module:         \spimemio_wb
Used module:             \spimemio
Used module:                 \spimemio_xfer
Used module:         $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb
Used module:             $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32
Used module:                 \picorv32_pcpi_div
Used module:                 \picorv32_pcpi_mul
Used module:                 \mgmt_soc_regs
Used module:         \convert_gpio_sigs
Used module:     \caravel_clocking
Used module:         $paramod\clock_div\SIZE=3
Used module:             \odd
Used module:             \even
Removed 0 unused modules.

13.2. Executing PROC pass (convert processes to netlists).

13.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 16 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
Found and cleaned up 1 empty switch in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
Found and cleaned up 6 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:546$6993'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:546$6993'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
Found and cleaned up 1 empty switch in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
Found and cleaned up 1 empty switch in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
Cleaned up 62 empty switches.

13.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 41 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 8 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 47 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Removed 2 dead cases from process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882 in module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Marked 8 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855 in module $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443 in module $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433 in module $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 11 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 43 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367 in module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757 in module $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156 in module mem_wb.
Marked 22 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519 in module counter_timer_low.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509 in module counter_timer_low.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507 in module counter_timer_low.
Marked 17 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458 in module counter_timer_high.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450 in module counter_timer_high.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448 in module counter_timer_high.
Marked 5 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413 in module simple_spi_master.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407 in module simple_spi_master.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401 in module simple_spi_master.
Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390 in module simple_spi_master.
Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373 in module simple_spi_master.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371 in module simple_spi_master.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326 in module simpleuart.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316 in module simpleuart.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314 in module simpleuart.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268 in module spimemio_xfer.
Marked 5 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244 in module spimemio_xfer.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214 in module spimemio.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146 in module spimemio.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506 in module $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066 in module picorv32_pcpi_div.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045 in module $paramod\clock_div\SIZE=3.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023 in module picorv32_pcpi_mul.
Marked 16 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011 in module housekeeping_spi_slave.
Marked 6 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001 in module housekeeping_spi_slave.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994 in module housekeeping_spi.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263 in module caravel_clocking.
Marked 1 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258 in module caravel_clocking.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252 in module even.
Marked 2 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244 in module odd.
Marked 4 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236 in module odd.
Marked 3 switch rules as full_case in process $proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230 in module odd.
Removed a total of 2 dead cases.

13.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 24 redundant assignments.
Promoted 263 assignments to connections.

13.2.4. Executing PROC_INIT pass (extract init attributes).

13.2.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \resetn in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
Found async reset \resetn in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
Found async reset \resetn in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
Found async reset \resetn in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
Found async reset \resetb in `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
Found async reset \csb_reset in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
Found async reset \csb_reset in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
Found async reset \RSTB in `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
Found async reset \resetb in `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'.
Found async reset \resetb in `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
Found async reset \resetb in `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'.
Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Found async reset \resetb in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.

13.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
     1/86: $23\next_irq_pending[2:2]
     2/86: $22\next_irq_pending[2:2]
     3/86: $21\next_irq_pending[2:2]
     4/86: $20\next_irq_pending[2:2]
     5/86: $19\next_irq_pending[2:2]
     6/86: $18\next_irq_pending[2:2]
     7/86: $17\next_irq_pending[2:2]
     8/86: $16\next_irq_pending[0:0]
     9/86: $15\next_irq_pending[0:0]
    10/86: $14\next_irq_pending[31:0] [0]
    11/86: $14\next_irq_pending[31:0] [31:1]
    12/86: $2\next_irq_pending[31:0] [31:2]
    13/86: $3\set_mem_do_rdata[0:0]
    14/86: $2\next_irq_pending[31:0] [1]
    15/86: $3\set_mem_do_wdata[0:0]
    16/86: $2\next_irq_pending[31:0] [0]
    17/86: $4\set_mem_do_rinst[0:0]
    18/86: $3\set_mem_do_rinst[0:0]
    19/86: $4\set_mem_do_wdata[0:0]
    20/86: $12\next_irq_pending[1:1]
    21/86: $11\next_irq_pending[1:1]
    22/86: $10\next_irq_pending[1:1]
    23/86: $4\set_mem_do_rdata[0:0]
    24/86: $8\next_irq_pending[1:1]
    25/86: $7\next_irq_pending[1:1]
    26/86: $6\next_irq_pending[1:1]
    27/86: $5\next_irq_pending[1:1]
    28/86: $4\next_irq_pending[1:1]
    29/86: $13\next_irq_pending[1:1]
    30/86: $5\set_mem_do_rinst[0:0]
    31/86: $9\next_irq_pending[1:1]
    32/86: $3\next_irq_pending[31:0]
    33/86: $3\current_pc[31:0]
    34/86: $2\current_pc[31:0]
    35/86: $2\set_mem_do_wdata[0:0]
    36/86: $2\set_mem_do_rdata[0:0]
    37/86: $2\set_mem_do_rinst[0:0]
    38/86: $1\next_irq_pending[31:0]
    39/86: $1\current_pc[31:0]
    40/86: $1\set_mem_do_wdata[0:0]
    41/86: $1\set_mem_do_rdata[0:0]
    42/86: $1\set_mem_do_rinst[0:0]
    43/86: $0\trace_data[35:0]
    44/86: $0\count_cycle[63:0]
    45/86: $0\pcpi_timeout[0:0]
    46/86: $0\trace_valid[0:0]
    47/86: $0\do_waitirq[0:0]
    48/86: $0\decoder_pseudo_trigger[0:0]
    49/86: $0\decoder_trigger[0:0]
    50/86: $0\alu_wait_2[0:0]
    51/86: $0\alu_wait[0:0]
    52/86: $0\reg_out[31:0]
    53/86: $0\reg_sh[4:0]
    54/86: $0\trap[0:0]
    55/86: $0\pcpi_timeout_counter[3:0]
    56/86: $0\latched_rd[4:0]
    57/86: $0\latched_is_lb[0:0]
    58/86: $0\latched_is_lh[0:0]
    59/86: $0\latched_is_lu[0:0]
    60/86: $0\latched_trace[0:0]
    61/86: $0\latched_compr[0:0]
    62/86: $0\latched_branch[0:0]
    63/86: $0\latched_stalu[0:0]
    64/86: $0\latched_store[0:0]
    65/86: $0\irq_state[1:0]
    66/86: $0\cpu_state[7:0]
    67/86: $0\dbg_rs2val_valid[0:0]
    68/86: $0\dbg_rs1val_valid[0:0]
    69/86: $0\dbg_rs2val[31:0]
    70/86: $0\dbg_rs1val[31:0]
    71/86: $0\mem_do_wdata[0:0]
    72/86: $0\mem_do_rdata[0:0]
    73/86: $0\mem_do_rinst[0:0]
    74/86: $0\mem_do_prefetch[0:0]
    75/86: $0\mem_wordsize[1:0]
    76/86: $0\timer[31:0]
    77/86: $0\irq_mask[31:0]
    78/86: $0\irq_active[0:0]
    79/86: $0\irq_delay[0:0]
    80/86: $0\reg_op2[31:0]
    81/86: $0\reg_op1[31:0]
    82/86: $0\reg_next_pc[31:0]
    83/86: $0\reg_pc[31:0]
    84/86: $0\count_instr[63:0]
    85/86: $0\eoi[31:0]
    86/86: $0\pcpi_valid[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
     1/4: $2\cpuregs_write[0:0]
     2/4: $2\cpuregs_wrdata[31:0]
     3/4: $1\cpuregs_wrdata[31:0]
     4/4: $1\cpuregs_write[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'.
     1/2: $2\clear_prefetched_high_word[0:0]
     2/2: $1\clear_prefetched_high_word[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$7327'.
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
     1/2: $1\alu_out[31:0]
     2/2: $1\alu_out_0[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'.
     1/8: $8\dbg_ascii_state[127:0]
     2/8: $7\dbg_ascii_state[127:0]
     3/8: $6\dbg_ascii_state[127:0]
     4/8: $5\dbg_ascii_state[127:0]
     5/8: $4\dbg_ascii_state[127:0]
     6/8: $3\dbg_ascii_state[127:0]
     7/8: $2\dbg_ascii_state[127:0]
     8/8: $1\dbg_ascii_state[127:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
     1/76: $0\decoded_rs1[4:0] [4]
     2/76: $0\decoded_imm_j[31:0] [10]
     3/76: $0\decoded_imm_j[31:0] [7]
     4/76: $0\decoded_imm_j[31:0] [6]
     5/76: $0\decoded_imm_j[31:0] [3:1]
     6/76: $0\decoded_imm_j[31:0] [5]
     7/76: $0\decoded_imm_j[31:0] [9:8]
     8/76: $0\decoded_imm_j[31:0] [31:20]
     9/76: $0\decoded_imm_j[31:0] [4]
    10/76: $0\decoded_imm_j[31:0] [11]
    11/76: $0\decoded_imm_j[31:0] [0]
    12/76: $0\decoded_rs1[4:0] [3:0]
    13/76: $0\is_lui_auipc_jal_jalr_addi_add_sub[0:0]
    14/76: $0\is_alu_reg_reg[0:0]
    15/76: $0\is_alu_reg_imm[0:0]
    16/76: $0\is_beq_bne_blt_bge_bltu_bgeu[0:0]
    17/76: $0\is_sll_srl_sra[0:0]
    18/76: $0\is_sb_sh_sw[0:0]
    19/76: $0\is_jalr_addi_slti_sltiu_xori_ori_andi[0:0]
    20/76: $0\is_slli_srli_srai[0:0]
    21/76: $0\is_lb_lh_lw_lbu_lhu[0:0]
    22/76: $0\compressed_instr[0:0]
    23/76: $0\is_compare[0:0]
    24/76: $0\decoded_imm[31:0]
    25/76: $0\decoded_rs2[4:0]
    26/76: $0\decoded_imm_j[31:0] [19:12]
    27/76: $0\decoded_rd[4:0]
    28/76: $0\instr_timer[0:0]
    29/76: $0\instr_waitirq[0:0]
    30/76: $0\instr_maskirq[0:0]
    31/76: $0\instr_retirq[0:0]
    32/76: $0\instr_setq[0:0]
    33/76: $0\instr_getq[0:0]
    34/76: $0\instr_ecall_ebreak[0:0]
    35/76: $0\instr_rdinstrh[0:0]
    36/76: $0\instr_rdinstr[0:0]
    37/76: $0\instr_rdcycleh[0:0]
    38/76: $0\instr_rdcycle[0:0]
    39/76: $0\instr_and[0:0]
    40/76: $0\instr_or[0:0]
    41/76: $0\instr_sra[0:0]
    42/76: $0\instr_srl[0:0]
    43/76: $0\instr_xor[0:0]
    44/76: $0\instr_sltu[0:0]
    45/76: $0\instr_slt[0:0]
    46/76: $0\instr_sll[0:0]
    47/76: $0\instr_sub[0:0]
    48/76: $0\instr_add[0:0]
    49/76: $0\instr_srai[0:0]
    50/76: $0\instr_srli[0:0]
    51/76: $0\instr_slli[0:0]
    52/76: $0\instr_andi[0:0]
    53/76: $0\instr_ori[0:0]
    54/76: $0\instr_xori[0:0]
    55/76: $0\instr_sltiu[0:0]
    56/76: $0\instr_slti[0:0]
    57/76: $0\instr_addi[0:0]
    58/76: $0\instr_sw[0:0]
    59/76: $0\instr_sh[0:0]
    60/76: $0\instr_sb[0:0]
    61/76: $0\instr_lhu[0:0]
    62/76: $0\instr_lbu[0:0]
    63/76: $0\instr_lw[0:0]
    64/76: $0\instr_lh[0:0]
    65/76: $0\instr_lb[0:0]
    66/76: $0\instr_bgeu[0:0]
    67/76: $0\instr_bltu[0:0]
    68/76: $0\instr_bge[0:0]
    69/76: $0\instr_blt[0:0]
    70/76: $0\instr_bne[0:0]
    71/76: $0\instr_beq[0:0]
    72/76: $0\instr_jalr[0:0]
    73/76: $0\instr_jal[0:0]
    74/76: $0\instr_auipc[0:0]
    75/76: $0\instr_lui[0:0]
    76/76: $0\pcpi_insn[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
     1/13: $3\dbg_insn_opcode[31:0]
     2/13: $2\dbg_insn_rd[4:0]
     3/13: $2\dbg_insn_rs2[4:0]
     4/13: $2\dbg_insn_rs1[4:0]
     5/13: $2\dbg_insn_opcode[31:0]
     6/13: $2\dbg_insn_imm[31:0]
     7/13: $2\dbg_ascii_instr[63:0]
     8/13: $1\dbg_insn_rd[4:0]
     9/13: $1\dbg_insn_rs2[4:0]
    10/13: $1\dbg_insn_rs1[4:0]
    11/13: $1\dbg_insn_imm[31:0]
    12/13: $1\dbg_ascii_instr[63:0]
    13/13: $1\dbg_insn_opcode[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
     1/8: $0\cached_insn_rd[4:0]
     2/8: $0\cached_insn_rs2[4:0]
     3/8: $0\cached_insn_rs1[4:0]
     4/8: $0\cached_insn_opcode[31:0]
     5/8: $0\cached_insn_imm[31:0]
     6/8: $0\cached_ascii_instr[63:0]
     7/8: $0\dbg_valid_insn[0:0]
     8/8: $0\dbg_insn_addr[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'.
     1/47: $47\new_ascii_instr[63:0]
     2/47: $46\new_ascii_instr[63:0]
     3/47: $45\new_ascii_instr[63:0]
     4/47: $44\new_ascii_instr[63:0]
     5/47: $43\new_ascii_instr[63:0]
     6/47: $42\new_ascii_instr[63:0]
     7/47: $41\new_ascii_instr[63:0]
     8/47: $40\new_ascii_instr[63:0]
     9/47: $39\new_ascii_instr[63:0]
    10/47: $38\new_ascii_instr[63:0]
    11/47: $37\new_ascii_instr[63:0]
    12/47: $36\new_ascii_instr[63:0]
    13/47: $35\new_ascii_instr[63:0]
    14/47: $34\new_ascii_instr[63:0]
    15/47: $33\new_ascii_instr[63:0]
    16/47: $32\new_ascii_instr[63:0]
    17/47: $31\new_ascii_instr[63:0]
    18/47: $30\new_ascii_instr[63:0]
    19/47: $29\new_ascii_instr[63:0]
    20/47: $28\new_ascii_instr[63:0]
    21/47: $27\new_ascii_instr[63:0]
    22/47: $26\new_ascii_instr[63:0]
    23/47: $25\new_ascii_instr[63:0]
    24/47: $24\new_ascii_instr[63:0]
    25/47: $23\new_ascii_instr[63:0]
    26/47: $22\new_ascii_instr[63:0]
    27/47: $21\new_ascii_instr[63:0]
    28/47: $20\new_ascii_instr[63:0]
    29/47: $19\new_ascii_instr[63:0]
    30/47: $18\new_ascii_instr[63:0]
    31/47: $17\new_ascii_instr[63:0]
    32/47: $16\new_ascii_instr[63:0]
    33/47: $15\new_ascii_instr[63:0]
    34/47: $14\new_ascii_instr[63:0]
    35/47: $13\new_ascii_instr[63:0]
    36/47: $12\new_ascii_instr[63:0]
    37/47: $11\new_ascii_instr[63:0]
    38/47: $10\new_ascii_instr[63:0]
    39/47: $9\new_ascii_instr[63:0]
    40/47: $8\new_ascii_instr[63:0]
    41/47: $7\new_ascii_instr[63:0]
    42/47: $6\new_ascii_instr[63:0]
    43/47: $5\new_ascii_instr[63:0]
    44/47: $4\new_ascii_instr[63:0]
    45/47: $3\new_ascii_instr[63:0]
    46/47: $2\new_ascii_instr[63:0]
    47/47: $1\new_ascii_instr[63:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
     1/9: $0\mem_16bit_buffer[15:0]
     2/9: $0\prefetched_high_word[0:0]
     3/9: $0\mem_la_secondword[0:0]
     4/9: $0\mem_state[1:0]
     5/9: $0\mem_wstrb[3:0]
     6/9: $0\mem_wdata[31:0]
     7/9: $0\mem_addr[31:0]
     8/9: $0\mem_instr[0:0]
     9/9: $0\mem_valid[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
     1/9: $0\mem_rdata_q[31:0] [31]
     2/9: $0\mem_rdata_q[31:0] [7]
     3/9: $0\mem_rdata_q[31:0] [24:20]
     4/9: $0\mem_rdata_q[31:0] [19:15]
     5/9: $0\mem_rdata_q[31:0] [6:0]
     6/9: $0\mem_rdata_q[31:0] [14:12]
     7/9: $0\mem_rdata_q[31:0] [11:8]
     8/9: $0\mem_rdata_q[31:0] [30:25]
     9/9: $0\next_insn_opcode[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
     1/5: $3\mem_rdata_word[31:0]
     2/5: $2\mem_rdata_word[31:0]
     3/5: $1\mem_rdata_word[31:0]
     4/5: $1\mem_la_wstrb[3:0]
     5/5: $1\mem_la_wdata[31:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
     1/2: $0\last_mem_valid[0:0]
     2/2: $0\mem_la_firstword_reg[0:0]
Creating decoders for process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
     1/2: $1\pcpi_int_rd[31:0]
     2/2: $1\pcpi_int_wr[0:0]
Creating decoders for process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
     1/34: $0\la_ena_3[31:0] [31:24]
     2/34: $0\la_ena_3[31:0] [23:16]
     3/34: $0\la_ena_3[31:0] [15:8]
     4/34: $0\la_ena_3[31:0] [7:0]
     5/34: $0\la_ena_2[31:0] [23:16]
     6/34: $0\la_ena_2[31:0] [15:8]
     7/34: $0\la_ena_2[31:0] [7:0]
     8/34: $0\la_ena_1[31:0] [23:16]
     9/34: $0\la_ena_1[31:0] [15:8]
    10/34: $0\la_ena_1[31:0] [7:0]
    11/34: $0\la_ena_0[31:0] [23:16]
    12/34: $0\la_ena_0[31:0] [15:8]
    13/34: $0\la_ena_0[31:0] [7:0]
    14/34: $0\la_data_3[31:0] [23:16]
    15/34: $0\la_data_3[31:0] [15:8]
    16/34: $0\la_data_3[31:0] [7:0]
    17/34: $0\la_data_2[31:0] [23:16]
    18/34: $0\la_data_2[31:0] [15:8]
    19/34: $0\la_data_2[31:0] [7:0]
    20/34: $0\la_data_1[31:0] [23:16]
    21/34: $0\la_data_1[31:0] [15:8]
    22/34: $0\la_data_1[31:0] [7:0]
    23/34: $0\la_data_0[31:0] [23:16]
    24/34: $0\la_data_0[31:0] [15:8]
    25/34: $0\la_data_0[31:0] [7:0]
    26/34: $0\la_ena_1[31:0] [31:24]
    27/34: $0\la_ena_0[31:0] [31:24]
    28/34: $0\la_data_3[31:0] [31:24]
    29/34: $0\la_data_2[31:0] [31:24]
    30/34: $0\la_data_1[31:0] [31:24]
    31/34: $0\la_data_0[31:0] [31:24]
    32/34: $0\la_ena_2[31:0] [31:24]
    33/34: $0\iomem_ready[0:0]
    34/34: $0\iomem_rdata[31:0]
Creating decoders for process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
     1/7: $0\irq_8_inputsrc[0:0]
     2/7: $0\irq_7_inputsrc[0:0]
     3/7: $0\trap_output_dest[0:0]
     4/7: $0\clk2_output_dest[0:0]
     5/7: $0\clk1_output_dest[0:0]
     6/7: $0\iomem_ready[0:0]
     7/7: $0\iomem_rdata[31:0]
Creating decoders for process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
     1/6: $0\iomem_ready[0:0]
     2/6: $0\iomem_rdata[31:0]
     3/6: $0\gpio_pd[0:0]
     4/6: $0\gpio_pu[0:0]
     5/6: $0\gpio_oeb[0:0]
     6/6: $0\gpio[0:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
     1/1: $0\io_ctrl[37][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
     1/1: $0\io_ctrl[36][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
     1/1: $0\io_ctrl[35][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
     1/1: $0\io_ctrl[34][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
     1/1: $0\io_ctrl[33][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
     1/1: $0\io_ctrl[32][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
     1/1: $0\io_ctrl[31][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
     1/1: $0\io_ctrl[30][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
     1/1: $0\io_ctrl[29][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
     1/1: $0\io_ctrl[28][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
     1/1: $0\io_ctrl[27][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
     1/1: $0\io_ctrl[26][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
     1/1: $0\io_ctrl[25][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
     1/1: $0\io_ctrl[24][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
     1/1: $0\io_ctrl[23][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
     1/1: $0\io_ctrl[22][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
     1/1: $0\io_ctrl[21][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
     1/1: $0\io_ctrl[20][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
     1/1: $0\io_ctrl[19][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
     1/1: $0\io_ctrl[18][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
     1/1: $0\io_ctrl[17][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
     1/1: $0\io_ctrl[16][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
     1/1: $0\io_ctrl[15][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
     1/1: $0\io_ctrl[14][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
     1/1: $0\io_ctrl[13][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
     1/1: $0\io_ctrl[12][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
     1/1: $0\io_ctrl[11][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
     1/1: $0\io_ctrl[10][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
     1/1: $0\io_ctrl[9][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
     1/1: $0\io_ctrl[8][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
     1/1: $0\io_ctrl[7][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
     1/1: $0\io_ctrl[6][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
     1/1: $0\io_ctrl[5][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
     1/1: $0\io_ctrl[4][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
     1/1: $0\io_ctrl[3][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
     1/1: $0\io_ctrl[2][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
     1/1: $0\io_ctrl[1][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
     1/1: $0\io_ctrl[0][12:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'.
     1/1: $0\mgmt_gpio_outr[37:32]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'.
     1/1: $0\mgmt_gpio_outr[31:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6602'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6597'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6592'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6587'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6582'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6577'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6572'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6567'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6562'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6557'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6552'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6547'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6542'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6537'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6532'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6527'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6522'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6517'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6512'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6507'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6502'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6497'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6492'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6487'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6482'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6477'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6472'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6467'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6462'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6457'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6452'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6447'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6442'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6437'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6432'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6427'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6422'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6417'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6412'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6410'.
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
     1/13: $4$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6397
     2/13: $3$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6394
     3/13: $3$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR[5:0]$6393
     4/13: $2$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6390
     5/13: $2$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR[5:0]$6389
     6/13: $1$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6387
     7/13: $1$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR[5:0]$6386
     8/13: $0\serial_data_staging[12:0]
     9/13: $0\xfer_state[1:0]
    10/13: $0\pad_count[5:0]
    11/13: $0\xfer_count[3:0]
    12/13: $0\serial_resetn[0:0]
    13/13: $0\serial_clock[0:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
     1/2: $0\xfer_ctrl[0:0]
     2/2: $0\pwr_ctrl_out[3:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
     1/2: $0\iomem_ready[0:0]
     2/2: $0\iomem_rdata[31:0]
Creating decoders for process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'.
     1/46: $43\iomem_rdata_pre[31:0]
     2/46: $42\iomem_rdata_pre[31:0]
     3/46: $41\iomem_rdata_pre[31:0]
     4/46: $40\iomem_rdata_pre[31:0]
     5/46: $39\iomem_rdata_pre[31:0]
     6/46: $38\iomem_rdata_pre[31:0]
     7/46: $37\iomem_rdata_pre[31:0]
     8/46: $36\iomem_rdata_pre[31:0]
     9/46: $35\iomem_rdata_pre[31:0]
    10/46: $34\iomem_rdata_pre[31:0]
    11/46: $33\iomem_rdata_pre[31:0]
    12/46: $32\iomem_rdata_pre[31:0]
    13/46: $31\iomem_rdata_pre[31:0]
    14/46: $30\iomem_rdata_pre[31:0]
    15/46: $29\iomem_rdata_pre[31:0]
    16/46: $28\iomem_rdata_pre[31:0]
    17/46: $27\iomem_rdata_pre[31:0]
    18/46: $26\iomem_rdata_pre[31:0]
    19/46: $25\iomem_rdata_pre[31:0]
    20/46: $24\iomem_rdata_pre[31:0]
    21/46: $23\iomem_rdata_pre[31:0]
    22/46: $22\iomem_rdata_pre[31:0]
    23/46: $21\iomem_rdata_pre[31:0]
    24/46: $20\iomem_rdata_pre[31:0]
    25/46: $19\iomem_rdata_pre[31:0]
    26/46: $18\iomem_rdata_pre[31:0]
    27/46: $17\iomem_rdata_pre[31:0]
    28/46: $16\iomem_rdata_pre[31:0]
    29/46: $15\iomem_rdata_pre[31:0]
    30/46: $14\iomem_rdata_pre[31:0]
    31/46: $13\iomem_rdata_pre[31:0]
    32/46: $12\iomem_rdata_pre[31:0]
    33/46: $11\iomem_rdata_pre[31:0]
    34/46: $10\iomem_rdata_pre[31:0]
    35/46: $9\iomem_rdata_pre[31:0]
    36/46: $8\iomem_rdata_pre[31:0]
    37/46: $7\iomem_rdata_pre[31:0]
    38/46: $6\iomem_rdata_pre[31:0]
    39/46: $5\iomem_rdata_pre[31:0]
    40/46: $4\iomem_rdata_pre[31:0]
    41/46: $3\j[31:0]
    42/46: $3\iomem_rdata_pre[31:0]
    43/46: $2\iomem_rdata_pre[31:0]
    44/46: $2\j[31:0]
    45/46: $1\iomem_rdata_pre[31:0]
    46/46: $1\j[31:0]
Creating decoders for process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
     1/9: $0\state[1:0]
     2/9: $0\wbm_cyc_o[0:0]
     3/9: $0\wbm_stb_o[0:0]
     4/9: $0\wbm_sel_o[3:0]
     5/9: $0\wbm_we_o[0:0]
     6/9: $0\wbm_dat_o[31:0]
     7/9: $0\wbm_adr_o[31:0]
     8/9: $0\mem_rdata[31:0]
     9/9: $0\mem_ready[0:0]
Creating decoders for process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
     1/2: $0\wb_ack_o[0:0]
     2/2: $0\wb_ack_read[0:0]
Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
     1/8: $0\value_cur[31:0] [31:24]
     2/8: $0\value_cur[31:0] [7:0]
     3/8: $0\value_cur[31:0] [15:8]
     4/8: $0\value_cur[31:0] [23:16]
     5/8: $0\lastenable[0:0]
     6/8: $0\stop_out[0:0]
     7/8: $0\strobe[0:0]
     8/8: $0\irq_out[0:0]
Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
     1/4: $0\value_reset[31:0] [15:8]
     2/4: $0\value_reset[31:0] [7:0]
     3/4: $0\value_reset[31:0] [23:16]
     4/4: $0\value_reset[31:0] [31:24]
Creating decoders for process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
     1/5: $0\chain[0:0]
     2/5: $0\irq_ena[0:0]
     3/5: $0\updown[0:0]
     4/5: $0\oneshot[0:0]
     5/5: $0\enable[0:0]
Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
     1/7: $0\value_cur[31:0] [31:24]
     2/7: $0\value_cur[31:0] [23:16]
     3/7: $0\value_cur[31:0] [7:0]
     4/7: $0\value_cur[31:0] [15:8]
     5/7: $0\lastenable[0:0]
     6/7: $0\stop_out[0:0]
     7/7: $0\irq_out[0:0]
Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
     1/4: $0\value_reset[31:0] [15:8]
     2/4: $0\value_reset[31:0] [7:0]
     3/4: $0\value_reset[31:0] [23:16]
     4/4: $0\value_reset[31:0] [31:24]
Creating decoders for process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
     1/5: $0\chain[0:0]
     2/5: $0\irq_ena[0:0]
     3/5: $0\updown[0:0]
     4/5: $0\oneshot[0:0]
     5/5: $0\enable[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
     1/3: $0\rreg[7:0]
     2/3: $0\treg[7:0]
     3/3: $0\isdo[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
     1/1: $0\isck[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
     1/2: $0\count[7:0]
     2/2: $0\hsck[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
     1/4: $0\nbit[2:0]
     2/4: $0\icsb[0:0]
     3/4: $0\done[0:0]
     4/4: $0\state[1:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
     1/4: $0\r_latched[0:0]
     2/4: $0\w_latched[0:0]
     3/4: $0\d_latched[7:0]
     4/4: $0\err_out[0:0]
Creating decoders for process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
     1/9: $0\hkconn[0:0]
     2/9: $0\mode[0:0]
     3/9: $0\stream[0:0]
     4/9: $0\irqena[0:0]
     5/9: $0\mlb[0:0]
     6/9: $0\invcsb[0:0]
     7/9: $0\invsck[0:0]
     8/9: $0\prescaler[7:0]
     9/9: $0\enable[0:0]
Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
     1/4: $0\send_divcnt[31:0]
     2/4: $0\send_dummy[0:0]
     3/4: $0\send_bitcnt[3:0]
     4/4: $0\send_pattern[9:0]
Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
     1/5: $0\recv_divcnt[31:0]
     2/5: $0\recv_buf_valid[0:0]
     3/5: $0\recv_buf_data[7:0]
     4/5: $0\recv_pattern[7:0]
     5/5: $0\recv_state[3:0]
Creating decoders for process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
     1/5: $0\cfg_divider[31:0] [31:24]
     2/5: $0\cfg_divider[31:0] [23:16]
     3/5: $0\cfg_divider[31:0] [15:8]
     4/5: $0\cfg_divider[31:0] [7:0]
     5/5: $0\enabled[0:0]
Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
     1/14: $0\last_fetch[0:0]
     2/14: $0\fetch[0:0]
     3/14: $0\xfer_tag[3:0]
     4/14: $0\xfer_rd[0:0]
     5/14: $0\xfer_qspi[0:0]
     6/14: $0\xfer_cont[0:0]
     7/14: $0\dummy_count[3:0]
     8/14: $0\count[3:0]
     9/14: $0\ibuffer[7:0]
    10/14: $0\obuffer[7:0]
    11/14: $0\xfer_ddr[0:0]
    12/14: $0\xfer_dspi[0:0]
    13/14: $0\flash_clk[0:0]
    14/14: $0\flash_csb[0:0]
Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
     1/33: $5\next_count[3:0]
     2/33: $5\next_obuffer[7:0]
     3/33: $5\next_ibuffer[7:0]
     4/33: $4\next_count[3:0]
     5/33: $4\next_obuffer[7:0]
     6/33: $4\next_ibuffer[7:0]
     7/33: $3\next_count[3:0]
     8/33: $3\next_obuffer[7:0]
     9/33: $3\next_ibuffer[7:0]
    10/33: $2\next_fetch[0:0]
    11/33: $2\next_count[3:0]
    12/33: $2\next_ibuffer[7:0]
    13/33: $2\next_obuffer[7:0]
    14/33: $2\flash_io0_do[0:0]
    15/33: $2\flash_io0_oe[0:0]
    16/33: $2\flash_io3_oe[0:0]
    17/33: $2\flash_io2_oe[0:0]
    18/33: $2\flash_io1_oe[0:0]
    19/33: $2\flash_io3_do[0:0]
    20/33: $2\flash_io2_do[0:0]
    21/33: $2\flash_io1_do[0:0]
    22/33: $1\next_fetch[0:0]
    23/33: $1\next_count[3:0]
    24/33: $1\next_ibuffer[7:0]
    25/33: $1\next_obuffer[7:0]
    26/33: $1\flash_io3_oe[0:0]
    27/33: $1\flash_io2_oe[0:0]
    28/33: $1\flash_io1_oe[0:0]
    29/33: $1\flash_io0_oe[0:0]
    30/33: $1\flash_io3_do[0:0]
    31/33: $1\flash_io2_do[0:0]
    32/33: $1\flash_io1_do[0:0]
    33/33: $1\flash_io0_do[0:0]
Creating decoders for process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'.
Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
     1/17: $0\buffer[23:0] [23:16]
     2/17: $0\buffer[23:0] [15:8]
     3/17: $0\buffer[23:0] [7:0]
     4/17: $0\xfer_resetn[0:0]
     5/17: $0\rd_inc[0:0]
     6/17: $0\rd_wait[0:0]
     7/17: $0\rd_valid[0:0]
     8/17: $0\rd_addr[23:0]
     9/17: $0\din_valid[0:0]
    10/17: $0\din_rd[0:0]
    11/17: $0\din_ddr[0:0]
    12/17: $0\din_qspi[0:0]
    13/17: $0\din_cont[0:0]
    14/17: $0\din_tag[3:0]
    15/17: $0\din_data[7:0]
    16/17: $0\rdata[31:0]
    17/17: $0\state[3:0]
Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
Creating decoders for process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
     1/10: $0\softreset[0:0]
     2/10: $0\config_do[3:0]
     3/10: $0\config_clk[0:0]
     4/10: $0\config_csb[0:0]
     5/10: $0\config_oe[3:0]
     6/10: $0\config_dummy[3:0]
     7/10: $0\config_cont[0:0]
     8/10: $0\config_qspi[0:0]
     9/10: $0\config_ddr[0:0]
    10/10: $0\config_en[0:0]
Creating decoders for process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'.
Creating decoders for process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
     1/2: $0\wb_ack_o[1:0]
     2/2: $0\wb_ack_read[1:0]
Creating decoders for process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'.
Creating decoders for process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
     1/9: $0\pcpi_rd[31:0]
     2/9: $0\pcpi_wr[0:0]
     3/9: $0\pcpi_ready[0:0]
     4/9: $0\outsign[0:0]
     5/9: $0\running[0:0]
     6/9: $0\quotient_msk[31:0]
     7/9: $0\quotient[31:0]
     8/9: $0\divisor[62:0]
     9/9: $0\dividend[31:0]
Creating decoders for process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
     1/4: $0\instr_remu[0:0]
     2/4: $0\instr_rem[0:0]
     3/4: $0\instr_divu[0:0]
     4/4: $0\instr_div[0:0]
Creating decoders for process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
     1/2: $0\syncN[2:0]
     2/2: $0\syncNp[2:0]
Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
     1/3: $0\pcpi_ready[0:0]
     2/3: $0\pcpi_wr[0:0]
     3/3: $0\pcpi_rd[31:0]
Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
     1/7: $0\mul_finish[0:0]
     2/7: $0\mul_waiting[0:0]
     3/7: $0\mul_counter[6:0]
     4/7: $0\rdx[63:0]
     5/7: $0\rd[63:0]
     6/7: $0\rs2[63:0]
     7/7: $0\rs1[63:0]
Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
Creating decoders for process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
     1/4: $0\instr_mulhu[0:0]
     2/4: $0\instr_mulhsu[0:0]
     3/4: $0\instr_mulh[0:0]
     4/4: $0\instr_mul[0:0]
Creating decoders for process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
     1/14: $1\pass_thru_user[0:0]
     2/14: $0\pre_pass_thru_user[0:0]
     3/14: $0\pre_pass_thru_mgmt[0:0]
     4/14: $0\predata[6:0]
     5/14: $0\fixed[2:0]
     6/14: $0\readmode[0:0]
     7/14: $0\writemode[0:0]
     8/14: $0\pass_thru_user_delay[0:0]
     9/14: $0\pass_thru_mgmt_delay[0:0]
    10/14: $0\rdstb[0:0]
    11/14: $0\count[2:0]
    12/14: $0\addr[7:0]
    13/14: $0\state[2:0]
    14/14: $0\pass_thru_mgmt[0:0]
Creating decoders for process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
     1/3: $0\sdoenb[0:0]
     2/3: $0\ldata[7:0]
     3/3: $0\wrstb[0:0]
Creating decoders for process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
     1/12: $0\pll_trim[25:0] [25:24]
     2/12: $0\pll_trim[25:0] [23:16]
     3/12: $0\pll_trim[25:0] [15:8]
     4/12: $0\pll_trim[25:0] [7:0]
     5/12: $0\irq[0:0]
     6/12: $0\pll_bypass[0:0]
     7/12: $0\reset_reg[0:0]
     8/12: $0\pll_ena[0:0]
     9/12: $0\pll_div[4:0]
    10/12: $0\pll90_sel[2:0]
    11/12: $0\pll_sel[2:0]
    12/12: $0\pll_dco_ena[0:0]
Creating decoders for process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'.
     1/1: $0\reset_delay[2:0]
Creating decoders for process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
     1/4: $0\ext_clk_syncd[0:0]
     2/4: $0\use_pll_second[0:0]
     3/4: $0\use_pll_first[0:0]
     4/4: $0\ext_clk_syncd_pre[0:0]
Creating decoders for process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
     1/2: $0\out_counter[0:0]
     2/2: $0\counter[2:0]
Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:146$247'.
Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'.
     1/1: $0\rst_pulse[0:0]
Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
     1/3: $0\initial_begin[2:0]
     2/3: $0\out_counter2[0:0]
     3/3: $0\counter2[2:0]
Creating decoders for process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
     1/2: $0\out_counter[0:0]
     2/2: $0\counter[2:0]
Creating decoders for process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
     1/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936
     2/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_DATA[31:0]$2935
     3/3: $0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_ADDR[4:0]$2934
Creating decoders for process `\mgmt_soc.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:333$2926'.

13.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_rs1' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_rs2' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_write' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpuregs_wrdata' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\clear_prefetched_high_word' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_0' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_ascii_state' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_opcode' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_ascii_instr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_imm' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rs1' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rs2' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_rd' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\new_ascii_instr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_add_sub' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_shl' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_shr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_eq' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_ltu' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_lts' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_wdata' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_wstrb' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_rdata_word' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_wr' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_rd' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_wait' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
No latch inferred for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_int_ready' from process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_data_arr[0]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_data_arr[1]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[0]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[1]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[2]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[3]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[4]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[5]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[6]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[7]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[8]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[9]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[10]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[11]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[12]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[13]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[14]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[15]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[16]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[17]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[18]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[19]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[20]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[21]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[22]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[23]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[24]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[25]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[26]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[27]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[28]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[29]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[30]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[31]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[32]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[33]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[34]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[35]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[36]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl_arr[37]' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6238' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6602'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6236' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6597'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6234' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6592'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6232' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6587'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6230' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6582'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6228' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6577'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6226' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6572'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6224' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6567'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6222' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6562'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6220' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6557'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6218' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6552'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6216' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6547'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6214' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6542'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6212' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6537'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6210' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6532'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6208' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6527'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6206' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6522'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6204' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6517'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6202' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6512'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6200' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6507'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6198' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6502'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6196' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6497'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6194' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6492'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6192' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6487'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6190' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6482'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6188' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6477'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6186' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6472'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6184' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6467'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6182' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6462'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6180' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6457'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6178' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6452'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6176' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6447'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6174' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6442'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6172' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6437'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6170' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6432'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6168' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6427'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6166' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6422'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6164' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6417'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:141$6160' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6412'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2bits$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:140$6159' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6410'.
No latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_rdata_pre' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'.
Latch inferred for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\j' from process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367': $auto$proc_dlatch.cc:430:proc_dlatch$14650
No latch inferred for signal `\spimemio_xfer.\flash_io0_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io1_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io2_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io3_do' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io0_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io1_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io2_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\flash_io3_oe' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\next_obuffer' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\next_ibuffer' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\next_count' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `\spimemio_xfer.\next_fetch' from process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
No latch inferred for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\wb_rw_dat_o' from process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'.
No latch inferred for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\i' from process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'.
No latch inferred for signal `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.\i' from process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'.
No latch inferred for signal `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.\wbm_dat_o' from process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'.
No latch inferred for signal `\picorv32_pcpi_mul.\i' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rs1' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rs2' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\this_rs2' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rd' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rdx' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\next_rdt' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\picorv32_pcpi_mul.\j' from process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
No latch inferred for signal `\mgmt_soc.\irq' from process `\mgmt_soc.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:333$2926'.

13.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trap' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14651' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14652' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\eoi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14653' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trace_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14654' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\trace_data' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14655' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\count_cycle' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14656' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\count_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14657' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14658' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_next_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14659' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_op1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14660' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_op2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14661' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_out' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14662' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\reg_sh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14663' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_delay' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14664' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_active' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14665' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_mask' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14666' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_pending' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14667' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\timer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14668' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wordsize' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14669' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_prefetch' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14670' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_rinst' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14671' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_rdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14672' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_do_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14673' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_trigger' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14674' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_trigger_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14675' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_pseudo_trigger' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14676' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoder_pseudo_trigger_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14677' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs1val' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14678' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs2val' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14679' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs1val_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14680' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_rs2val_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14681' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cpu_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14682' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\irq_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14683' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_rinst' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14684' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_rdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14685' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\set_mem_do_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14686' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_store' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14687' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_stalu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14688' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_branch' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14689' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_compr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14690' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_trace' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14691' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14692' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14693' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_is_lb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14694' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\latched_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14695' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\current_pc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14696' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_timeout_counter' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14697' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_timeout' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14698' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\next_irq_pending' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14699' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\do_waitirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14700' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14701' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_out_0_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14702' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_wait' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14703' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\alu_wait_2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
  created $dff cell `$procdff$14704' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\clear_prefetched_high_word_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$7327'.
  created $dff cell `$procdff$14705' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\pcpi_insn' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14706' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lui' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14707' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_auipc' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14708' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_jal' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14709' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_jalr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14710' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_beq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14711' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bne' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14712' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_blt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14713' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bge' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14714' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14715' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_bgeu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14716' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14717' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14718' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14719' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lbu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14720' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_lhu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14721' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14722' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14723' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14724' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_addi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14725' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slti' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14726' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sltiu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14727' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_xori' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14728' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_ori' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14729' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_andi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14730' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slli' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14731' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srli' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14732' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srai' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14733' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_add' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14734' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sub' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14735' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sll' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14736' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_slt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14737' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14738' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_xor' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14739' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_srl' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14740' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_sra' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14741' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_or' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14742' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_and' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14743' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdcycle' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14744' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdcycleh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14745' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdinstr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14746' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_rdinstrh' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14747' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_ecall_ebreak' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14748' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_getq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14749' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_setq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14750' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_retirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14751' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_maskirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14752' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_waitirq' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14753' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\instr_timer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14754' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14755' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14756' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14757' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14758' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\decoded_imm_j' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14759' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\compressed_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14760' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lui_auipc_jal' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14761' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lb_lh_lw_lbu_lhu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14762' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_slli_srli_srai' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14763' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_jalr_addi_slti_sltiu_xori_ori_andi' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14764' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sb_sh_sw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14765' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sll_srl_sra' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14766' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lui_auipc_jal_jalr_addi_add_sub' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14767' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_slti_blt_slt' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14768' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_sltiu_bltu_sltu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14769' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_beq_bne_blt_bge_bltu_bgeu' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14770' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_lbu_lhu_lw' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14771' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_alu_reg_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14772' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_alu_reg_reg' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14773' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\is_compare' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
  created $dff cell `$procdff$14774' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_insn_addr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14775' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_ascii_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14776' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14777' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14778' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14779' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14780' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\q_insn_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14781' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_next' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14782' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\dbg_valid_insn' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14783' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_ascii_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14784' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_imm' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14785' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14786' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rs1' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14787' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rs2' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14788' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\cached_insn_rd' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
  created $dff cell `$procdff$14789' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14790' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_instr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14791' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_addr' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14792' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wdata' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14793' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_wstrb' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14794' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_state' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14795' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_secondword' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14796' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\prefetched_high_word' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14797' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_16bit_buffer' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
  created $dff cell `$procdff$14798' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\next_insn_opcode' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
  created $dff cell `$procdff$14799' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_rdata_q' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
  created $dff cell `$procdff$14800' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\mem_la_firstword_reg' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
  created $dff cell `$procdff$14801' with positive edge clock.
Creating register for signal `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.\last_mem_valid' using process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
  created $dff cell `$procdff$14802' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\iomem_rdata' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14803' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\iomem_ready' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14804' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_0' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14805' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_1' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14806' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_2' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14807' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_data_3' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14808' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_0' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14809' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_1' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14810' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_2' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14811' with positive edge clock.
Creating register for signal `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.\la_ena_3' using process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
  created $dff cell `$procdff$14812' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\iomem_rdata' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
  created $dff cell `$procdff$14813' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\iomem_ready' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
  created $dff cell `$procdff$14814' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\clk1_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
  created $dff cell `$procdff$14815' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\clk2_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
  created $dff cell `$procdff$14816' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\trap_output_dest' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
  created $dff cell `$procdff$14817' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\irq_7_inputsrc' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
  created $dff cell `$procdff$14818' with positive edge clock.
Creating register for signal `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.\irq_8_inputsrc' using process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
  created $dff cell `$procdff$14819' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
  created $dff cell `$procdff$14820' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_oeb' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
  created $dff cell `$procdff$14821' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_pu' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
  created $dff cell `$procdff$14822' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\gpio_pd' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
  created $dff cell `$procdff$14823' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\iomem_rdata' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
  created $dff cell `$procdff$14824' with positive edge clock.
Creating register for signal `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.\iomem_ready' using process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
  created $dff cell `$procdff$14825' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[37]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
  created $dff cell `$procdff$14826' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[36]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
  created $dff cell `$procdff$14827' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[35]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
  created $dff cell `$procdff$14828' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[34]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
  created $dff cell `$procdff$14829' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[33]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
  created $dff cell `$procdff$14830' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[32]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
  created $dff cell `$procdff$14831' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[31]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
  created $dff cell `$procdff$14832' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[30]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
  created $dff cell `$procdff$14833' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[29]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
  created $dff cell `$procdff$14834' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[28]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
  created $dff cell `$procdff$14835' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[27]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
  created $dff cell `$procdff$14836' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[26]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
  created $dff cell `$procdff$14837' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[25]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
  created $dff cell `$procdff$14838' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[24]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
  created $dff cell `$procdff$14839' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[23]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
  created $dff cell `$procdff$14840' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[22]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
  created $dff cell `$procdff$14841' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[21]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
  created $dff cell `$procdff$14842' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[20]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
  created $dff cell `$procdff$14843' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[19]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
  created $dff cell `$procdff$14844' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[18]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
  created $dff cell `$procdff$14845' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[17]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
  created $dff cell `$procdff$14846' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[16]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
  created $dff cell `$procdff$14847' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[15]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
  created $dff cell `$procdff$14848' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[14]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
  created $dff cell `$procdff$14849' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[13]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
  created $dff cell `$procdff$14850' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[12]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
  created $dff cell `$procdff$14851' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[11]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
  created $dff cell `$procdff$14852' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[10]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
  created $dff cell `$procdff$14853' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[9]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
  created $dff cell `$procdff$14854' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[8]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
  created $dff cell `$procdff$14855' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[7]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
  created $dff cell `$procdff$14856' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[6]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
  created $dff cell `$procdff$14857' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[5]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
  created $dff cell `$procdff$14858' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[4]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
  created $dff cell `$procdff$14859' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[3]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
  created $dff cell `$procdff$14860' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[2]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
  created $dff cell `$procdff$14861' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[1]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
  created $dff cell `$procdff$14862' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\io_ctrl[0]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
  created $dff cell `$procdff$14863' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\mgmt_gpio_outr [37:32]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'.
  created $dff cell `$procdff$14864' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\mgmt_gpio_outr [31:0]' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'.
  created $dff cell `$procdff$14865' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_clock' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $adff cell `$procdff$14866' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_resetn' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $adff cell `$procdff$14867' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_count' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $adff cell `$procdff$14868' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\pad_count' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $adff cell `$procdff$14869' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_state' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $adff cell `$procdff$14870' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\serial_data_staging' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $dff cell `$procdff$14871' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_ADDR' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $adff cell `$procdff$14872' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
  created $adff cell `$procdff$14873' with positive edge clock and negative level reset.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\pwr_ctrl_out' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
  created $dff cell `$procdff$14874' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\xfer_ctrl' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
  created $dff cell `$procdff$14875' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_rdata' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
  created $dff cell `$procdff$14876' with positive edge clock.
Creating register for signal `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.\iomem_ready' using process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
  created $dff cell `$procdff$14877' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\mem_ready' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14878' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\mem_rdata' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14879' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_adr_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14880' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_dat_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14881' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_we_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14882' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_sel_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14883' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_stb_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14884' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\wbm_cyc_o' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14885' with positive edge clock.
Creating register for signal `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.\state' using process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
  created $dff cell `$procdff$14886' with positive edge clock.
Creating register for signal `\mem_wb.\wb_ack_o' using process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
  created $dff cell `$procdff$14887' with positive edge clock.
Creating register for signal `\mem_wb.\wb_ack_read' using process `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
  created $dff cell `$procdff$14888' with positive edge clock.
Creating register for signal `\counter_timer_low.\irq_out' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
  created $adff cell `$procdff$14889' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\strobe' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
  created $adff cell `$procdff$14890' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\stop_out' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
  created $adff cell `$procdff$14891' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\value_cur' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
  created $adff cell `$procdff$14892' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\lastenable' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
  created $adff cell `$procdff$14893' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\value_reset' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
  created $adff cell `$procdff$14894' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\enable' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
  created $adff cell `$procdff$14895' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\oneshot' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
  created $adff cell `$procdff$14896' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\updown' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
  created $adff cell `$procdff$14897' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\irq_ena' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
  created $adff cell `$procdff$14898' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_low.\chain' using process `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
  created $adff cell `$procdff$14899' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\irq_out' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
  created $adff cell `$procdff$14900' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\stop_out' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
  created $adff cell `$procdff$14901' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\value_cur' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
  created $adff cell `$procdff$14902' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\lastenable' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
  created $adff cell `$procdff$14903' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\value_reset' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
  created $adff cell `$procdff$14904' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\enable' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
  created $adff cell `$procdff$14905' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\oneshot' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
  created $adff cell `$procdff$14906' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\updown' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
  created $adff cell `$procdff$14907' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\irq_ena' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
  created $adff cell `$procdff$14908' with positive edge clock and negative level reset.
Creating register for signal `\counter_timer_high.\chain' using process `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
  created $adff cell `$procdff$14909' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\isdo' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
  created $adff cell `$procdff$14910' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\treg' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
  created $adff cell `$procdff$14911' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\rreg' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
  created $adff cell `$procdff$14912' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\isck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
  created $adff cell `$procdff$14913' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\count' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
  created $adff cell `$procdff$14914' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\hsck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
  created $adff cell `$procdff$14915' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\state' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
  created $adff cell `$procdff$14916' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\done' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
  created $adff cell `$procdff$14917' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\icsb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
  created $adff cell `$procdff$14918' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\nbit' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
  created $adff cell `$procdff$14919' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\err_out' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
  created $adff cell `$procdff$14920' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\d_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
  created $adff cell `$procdff$14921' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\w_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
  created $adff cell `$procdff$14922' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\r_latched' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
  created $adff cell `$procdff$14923' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\enable' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14924' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\prescaler' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14925' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\invsck' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14926' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\invcsb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14927' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\mlb' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14928' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\irqena' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14929' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\stream' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14930' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\mode' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14931' with positive edge clock and negative level reset.
Creating register for signal `\simple_spi_master.\hkconn' using process `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
  created $adff cell `$procdff$14932' with positive edge clock and negative level reset.
Creating register for signal `\simpleuart.\send_pattern' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
  created $dff cell `$procdff$14933' with positive edge clock.
Creating register for signal `\simpleuart.\send_bitcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
  created $dff cell `$procdff$14934' with positive edge clock.
Creating register for signal `\simpleuart.\send_divcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
  created $dff cell `$procdff$14935' with positive edge clock.
Creating register for signal `\simpleuart.\send_dummy' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
  created $dff cell `$procdff$14936' with positive edge clock.
Creating register for signal `\simpleuart.\recv_state' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
  created $dff cell `$procdff$14937' with positive edge clock.
Creating register for signal `\simpleuart.\recv_divcnt' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
  created $dff cell `$procdff$14938' with positive edge clock.
Creating register for signal `\simpleuart.\recv_pattern' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
  created $dff cell `$procdff$14939' with positive edge clock.
Creating register for signal `\simpleuart.\recv_buf_data' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
  created $dff cell `$procdff$14940' with positive edge clock.
Creating register for signal `\simpleuart.\recv_buf_valid' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
  created $dff cell `$procdff$14941' with positive edge clock.
Creating register for signal `\simpleuart.\enabled' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
  created $dff cell `$procdff$14942' with positive edge clock.
Creating register for signal `\simpleuart.\cfg_divider' using process `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
  created $dff cell `$procdff$14943' with positive edge clock.
Creating register for signal `\spimemio_xfer.\flash_csb' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14944' with positive edge clock.
Creating register for signal `\spimemio_xfer.\flash_clk' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14945' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_dspi' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14946' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_ddr' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14947' with positive edge clock.
Creating register for signal `\spimemio_xfer.\obuffer' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14948' with positive edge clock.
Creating register for signal `\spimemio_xfer.\ibuffer' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14949' with positive edge clock.
Creating register for signal `\spimemio_xfer.\count' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14950' with positive edge clock.
Creating register for signal `\spimemio_xfer.\dummy_count' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14951' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_cont' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14952' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_qspi' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14953' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_rd' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14954' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_tag' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14955' with positive edge clock.
Creating register for signal `\spimemio_xfer.\fetch' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14956' with positive edge clock.
Creating register for signal `\spimemio_xfer.\last_fetch' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
  created $dff cell `$procdff$14957' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_ddr_q' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'.
  created $dff cell `$procdff$14958' with positive edge clock.
Creating register for signal `\spimemio_xfer.\xfer_tag_q' using process `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'.
  created $dff cell `$procdff$14959' with positive edge clock.
Creating register for signal `\spimemio.\state' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14960' with positive edge clock.
Creating register for signal `\spimemio.\rdata' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14961' with positive edge clock.
Creating register for signal `\spimemio.\xfer_resetn' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14962' with positive edge clock.
Creating register for signal `\spimemio.\din_valid' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14963' with positive edge clock.
Creating register for signal `\spimemio.\din_data' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14964' with positive edge clock.
Creating register for signal `\spimemio.\din_tag' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14965' with positive edge clock.
Creating register for signal `\spimemio.\din_cont' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14966' with positive edge clock.
Creating register for signal `\spimemio.\din_qspi' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14967' with positive edge clock.
Creating register for signal `\spimemio.\din_ddr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14968' with positive edge clock.
Creating register for signal `\spimemio.\din_rd' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14969' with positive edge clock.
Creating register for signal `\spimemio.\buffer' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14970' with positive edge clock.
Creating register for signal `\spimemio.\rd_addr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14971' with positive edge clock.
Creating register for signal `\spimemio.\rd_valid' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14972' with positive edge clock.
Creating register for signal `\spimemio.\rd_wait' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14973' with positive edge clock.
Creating register for signal `\spimemio.\rd_inc' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
  created $dff cell `$procdff$14974' with positive edge clock.
Creating register for signal `\spimemio.\xfer_io0_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
  created $dff cell `$procdff$14975' with negative edge clock.
Creating register for signal `\spimemio.\xfer_io1_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
  created $dff cell `$procdff$14976' with negative edge clock.
Creating register for signal `\spimemio.\xfer_io2_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
  created $dff cell `$procdff$14977' with negative edge clock.
Creating register for signal `\spimemio.\xfer_io3_90' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
  created $dff cell `$procdff$14978' with negative edge clock.
Creating register for signal `\spimemio.\softreset' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14979' with positive edge clock.
Creating register for signal `\spimemio.\config_en' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14980' with positive edge clock.
Creating register for signal `\spimemio.\config_ddr' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14981' with positive edge clock.
Creating register for signal `\spimemio.\config_qspi' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14982' with positive edge clock.
Creating register for signal `\spimemio.\config_cont' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14983' with positive edge clock.
Creating register for signal `\spimemio.\config_dummy' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14984' with positive edge clock.
Creating register for signal `\spimemio.\config_oe' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14985' with positive edge clock.
Creating register for signal `\spimemio.\config_csb' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14986' with positive edge clock.
Creating register for signal `\spimemio.\config_clk' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14987' with positive edge clock.
Creating register for signal `\spimemio.\config_do' using process `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
  created $dff cell `$procdff$14988' with positive edge clock.
Creating register for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\wb_ack_o' using process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
  created $dff cell `$procdff$14989' with positive edge clock.
Creating register for signal `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.\wb_ack_read' using process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
  created $dff cell `$procdff$14990' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_wr' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14991' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_rd' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14992' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_ready' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14993' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\dividend' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14994' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\divisor' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14995' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\quotient' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14996' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\quotient_msk' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14997' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\running' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14998' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\outsign' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
  created $dff cell `$procdff$14999' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_wait' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
  created $dff cell `$procdff$15000' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\pcpi_wait_q' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
  created $dff cell `$procdff$15001' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\instr_div' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
  created $dff cell `$procdff$15002' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\instr_divu' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
  created $dff cell `$procdff$15003' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\instr_rem' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
  created $dff cell `$procdff$15004' with positive edge clock.
Creating register for signal `\picorv32_pcpi_div.\instr_remu' using process `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
  created $dff cell `$procdff$15005' with positive edge clock.
Creating register for signal `$paramod\clock_div\SIZE=3.\syncN' using process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
  created $adff cell `$procdff$15006' with positive edge clock and negative level reset.
Creating register for signal `$paramod\clock_div\SIZE=3.\syncNp' using process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
  created $adff cell `$procdff$15007' with positive edge clock and negative level reset.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_wr' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
  created $dff cell `$procdff$15008' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_rd' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
  created $dff cell `$procdff$15009' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_ready' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
  created $dff cell `$procdff$15010' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\rs1' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
  created $dff cell `$procdff$15011' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\rs2' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
  created $dff cell `$procdff$15012' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\rd' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
  created $dff cell `$procdff$15013' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\rdx' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
  created $dff cell `$procdff$15014' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\mul_counter' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
  created $dff cell `$procdff$15015' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\mul_waiting' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
  created $dff cell `$procdff$15016' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\mul_finish' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
  created $dff cell `$procdff$15017' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_wait' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
  created $dff cell `$procdff$15018' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\instr_mul' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
  created $dff cell `$procdff$15019' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\instr_mulh' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
  created $dff cell `$procdff$15020' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\instr_mulhsu' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
  created $dff cell `$procdff$15021' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\instr_mulhu' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
  created $dff cell `$procdff$15022' with positive edge clock.
Creating register for signal `\picorv32_pcpi_mul.\pcpi_wait_q' using process `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
  created $dff cell `$procdff$15023' with positive edge clock.
Creating register for signal `\housekeeping_spi_slave.\pass_thru_mgmt' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15024' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\state' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15025' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\addr' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15026' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\count' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15027' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\rdstb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15028' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pass_thru_mgmt_delay' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15029' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pass_thru_user' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15030' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pass_thru_user_delay' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15031' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\writemode' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15032' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\readmode' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15033' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\fixed' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15034' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\predata' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15035' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pre_pass_thru_mgmt' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15036' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\pre_pass_thru_user' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
  created $adff cell `$procdff$15037' with positive edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\sdoenb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
  created $adff cell `$procdff$15038' with negative edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\wrstb' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
  created $adff cell `$procdff$15039' with negative edge clock and positive level reset.
Creating register for signal `\housekeeping_spi_slave.\ldata' using process `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
  created $adff cell `$procdff$15040' with negative edge clock and positive level reset.
Creating register for signal `\housekeeping_spi.\pll_dco_ena' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15041' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_sel' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15042' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll90_sel' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15043' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_div' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15044' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_ena' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15045' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_trim' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15046' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\pll_bypass' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15047' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\irq' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15048' with positive edge clock and negative level reset.
Creating register for signal `\housekeeping_spi.\reset_reg' using process `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
  created $adff cell `$procdff$15049' with positive edge clock and negative level reset.
Creating register for signal `\caravel_clocking.\reset_delay' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'.
  created $adff cell `$procdff$15050' with positive edge clock and negative level reset.
Creating register for signal `\caravel_clocking.\use_pll_first' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
  created $adff cell `$procdff$15051' with positive edge clock and negative level reset.
Creating register for signal `\caravel_clocking.\use_pll_second' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
  created $adff cell `$procdff$15052' with positive edge clock and negative level reset.
Creating register for signal `\caravel_clocking.\ext_clk_syncd_pre' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
  created $dff cell `$procdff$15053' with positive edge clock.
Creating register for signal `\caravel_clocking.\ext_clk_syncd' using process `\caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
  created $adff cell `$procdff$15054' with positive edge clock and negative level reset.
Creating register for signal `\even.\counter' using process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
  created $adff cell `$procdff$15055' with positive edge clock and negative level reset.
Creating register for signal `\even.\out_counter' using process `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
  created $adff cell `$procdff$15056' with positive edge clock and negative level reset.
Creating register for signal `\odd.\old_N' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:146$247'.
  created $dff cell `$procdff$15057' with positive edge clock.
Creating register for signal `\odd.\rst_pulse' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'.
  created $adff cell `$procdff$15058' with positive edge clock and negative level reset.
Creating register for signal `\odd.\counter2' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Warning: Async reset value `\N' is not constant!
  created $dffsr cell `$procdff$15059' with negative edge clock and negative level non-const reset.
Creating register for signal `\odd.\out_counter2' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
  created $adff cell `$procdff$15066' with negative edge clock and negative level reset.
Creating register for signal `\odd.\initial_begin' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Warning: Async reset value `$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235_Y [3:1]' is not constant!
  created $dffsr cell `$procdff$15067' with negative edge clock and negative level non-const reset.
Creating register for signal `\odd.\counter' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
Warning: Async reset value `\N' is not constant!
  created $dffsr cell `$procdff$15074' with positive edge clock and negative level non-const reset.
Creating register for signal `\odd.\out_counter' using process `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
  created $adff cell `$procdff$15081' with positive edge clock and negative level reset.
Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_ADDR' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
  created $dff cell `$procdff$15082' with positive edge clock.
Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_DATA' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
  created $dff cell `$procdff$15083' with positive edge clock.
Creating register for signal `\mgmt_soc_regs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN' using process `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
  created $dff cell `$procdff$15084' with positive edge clock.

13.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 61 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1397$7361'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1382$7347'.
Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1304$7333'.
Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1290$7328'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1288$7327'.
Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1244$7305'.
Found and cleaned up 8 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1181$7293'.
Found and cleaned up 22 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:856$7033'.
Found and cleaned up 3 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:807$7031'.
Found and cleaned up 5 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:776$7027'.
Found and cleaned up 47 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:700$7026'.
Found and cleaned up 16 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:565$7002'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1234$7541'.
Found and cleaned up 19 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:430$6964'.
Found and cleaned up 3 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:401$6961'.
Found and cleaned up 2 empty switches in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:390$6956'.
Found and cleaned up 1 empty switch in `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
Removing empty process `$paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:325$6882'.
Found and cleaned up 42 empty switches in `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
Removing empty process `$paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.$proc$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:126$6855'.
Found and cleaned up 9 empty switches in `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
Removing empty process `$paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:124$5443'.
Found and cleaned up 10 empty switches in `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
Removing empty process `$paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:107$5433'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6846'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6840'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6834'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6828'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6822'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6816'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6810'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6804'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6798'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6792'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6786'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6780'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6774'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6768'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6762'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6756'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6750'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6744'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6738'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6732'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6726'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6720'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6714'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6708'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6702'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6696'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6690'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6684'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6678'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6672'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6666'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6660'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6654'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6648'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6642'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6636'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6630'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6624'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:264$6618'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6612'.
Found and cleaned up 4 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:247$6606'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6602'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6597'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6592'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6587'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6582'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6577'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6572'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6567'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6562'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6557'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6552'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6547'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6542'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6537'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6532'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6527'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6522'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6517'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6512'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6507'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6502'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6497'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6492'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6487'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6482'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6477'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6472'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6467'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6462'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6457'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6452'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6447'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6442'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6437'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6432'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6427'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6422'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6417'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6412'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:0$6410'.
Found and cleaned up 13 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:301$6382'.
Found and cleaned up 6 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:225$6375'.
Found and cleaned up 3 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:207$6369'.
Found and cleaned up 43 empty switches in `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'.
Removing empty process `$paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:184$6367'.
Found and cleaned up 4 empty switches in `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
Removing empty process `$paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2993$4757'.
Found and cleaned up 1 empty switch in `\mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
Removing empty process `mem_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:42$2156'.
Found and cleaned up 25 empty switches in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:187$1519'.
Found and cleaned up 4 empty switches in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:155$1509'.
Found and cleaned up 1 empty switch in `\counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
Removing empty process `counter_timer_low.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:133$1507'.
Found and cleaned up 26 empty switches in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:180$1458'.
Found and cleaned up 4 empty switches in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:152$1450'.
Found and cleaned up 1 empty switch in `\counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
Removing empty process `counter_timer_high.$proc$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:130$1448'.
Found and cleaned up 6 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:353$1413'.
Found and cleaned up 1 empty switch in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:340$1407'.
Found and cleaned up 2 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:321$1401'.
Found and cleaned up 6 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:285$1390'.
Found and cleaned up 9 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:241$1373'.
Found and cleaned up 2 empty switches in `\simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
Removing empty process `simple_spi_master.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:210$1371'.
Found and cleaned up 5 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:194$1326'.
Found and cleaned up 7 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:151$1316'.
Found and cleaned up 6 empty switches in `\simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
Removing empty process `simpleuart.$proc$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:138$1314'.
Found and cleaned up 4 empty switches in `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:697$1268'.
Found and cleaned up 5 empty switches in `\spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:609$1244'.
Removing empty process `spimemio_xfer.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:598$1235'.
Found and cleaned up 25 empty switches in `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:369$1214'.
Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:295$1150'.
Found and cleaned up 5 empty switches in `\spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
Removing empty process `spimemio.$proc$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:243$1146'.
Removing empty process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:84$4518'.
Found and cleaned up 1 empty switch in `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
Removing empty process `$paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.$proc$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:54$4506'.
Removing empty process `$paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.$proc$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:52$3512'.
Found and cleaned up 5 empty switches in `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
Removing empty process `picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2459$1066'.
Found and cleaned up 2 empty switches in `\picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
Removing empty process `picorv32_pcpi_div.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2433$1056'.
Removing empty process `$paramod\clock_div\SIZE=3.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:30$3045'.
Found and cleaned up 1 empty switch in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2302$1028'.
Found and cleaned up 5 empty switches in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2268$1023'.
Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2244$985'.
Found and cleaned up 2 empty switches in `\picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
Removing empty process `picorv32_pcpi_mul.$proc$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2216$979'.
Found and cleaned up 18 empty switches in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
Removing empty process `housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:399$3011'.
Found and cleaned up 6 empty switches in `\housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
Removing empty process `housekeeping_spi_slave.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:357$3001'.
Found and cleaned up 2 empty switches in `\housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
Removing empty process `housekeeping_spi.$proc$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:198$2994'.
Removing empty process `caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:85$263'.
Removing empty process `caravel_clocking.$proc$/project/openlane/mgmt_core/../../verilog/rtl/caravel_clocking.v:36$258'.
Found and cleaned up 2 empty switches in `\even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
Removing empty process `even.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:177$252'.
Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:146$247'.
Found and cleaned up 2 empty switches in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'.
Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:133$244'.
Found and cleaned up 4 empty switches in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:95$236'.
Found and cleaned up 3 empty switches in `\odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
Removing empty process `odd.$proc$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:72$230'.
Found and cleaned up 1 empty switch in `\mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
Removing empty process `mgmt_soc_regs.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:847$2933'.
Removing empty process `mgmt_soc.$proc$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:333$2926'.
Cleaned up 682 empty switches.

13.3. Executing FLATTEN pass (flatten design).
Deleting now unused module convert_gpio_sigs.
Deleting now unused module $paramod$fa337340043f3d6a6d58696d5f72948a05215c34\picorv32.
Deleting now unused module $paramod$ca62668e9890e0d911fa9cc3f09754d7750fb71c\la.
Deleting now unused module $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl.
Deleting now unused module $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio.
Deleting now unused module $paramod\soc_mem\WORDS=256\ADR_WIDTH=8.
Deleting now unused module $paramod$f3f3744fb6f7f5362ce4e5db714bf672d3a2140e\mprj_ctrl.
Deleting now unused module $paramod$5003a3824ab4fa5c9fb2ce071b508335b6ea3f1e\picorv32_wb.
Deleting now unused module $paramod\simpleuart_wb\BASE_ADR=536870912\CLK_DIV=8'00000000\DATA=8'00000100.
Deleting now unused module $paramod\simple_spi_master_wb\BASE_ADR=603979776\CONFIG=8'00000000\DATA=8'00000100.
Deleting now unused module mem_wb.
Deleting now unused module $paramod$eb38ef639d5e248b479cbbb17ad8847d62728585\counter_timer_low_wb.
Deleting now unused module counter_timer_low.
Deleting now unused module $paramod$7a40847776a6b97ca500ad187f6f606eebd9d328\counter_timer_high_wb.
Deleting now unused module counter_timer_high.
Deleting now unused module $paramod$7c0690a63bbf26fa3724bff7538cf8a1e2b60d48\gpio_wb.
Deleting now unused module simple_spi_master.
Deleting now unused module $paramod$5127b2add67e6a04802e6a42082c1f76c9942217\sysctrl_wb.
Deleting now unused module simpleuart.
Deleting now unused module $paramod$af288e7be42a852a63a02a6a87b17a79e0473fa5\la_wb.
Deleting now unused module spimemio_xfer.
Deleting now unused module spimemio.
Deleting now unused module spimemio_wb.
Deleting now unused module $paramod\mprj_ctrl_wb\BASE_ADR=637534208.
Deleting now unused module $paramod$fcceb124b12bded0f708cb8bbb5e7d95ebf1165b\storage_bridge_wb.
Deleting now unused module $paramod$28e5073159cf193af79354f9861ebc68d2c62ab9\wb_intercon.
Deleting now unused module picorv32_pcpi_div.
Deleting now unused module $paramod\clock_div\SIZE=3.
Deleting now unused module picorv32_pcpi_mul.
Deleting now unused module housekeeping_spi_slave.
Deleting now unused module housekeeping_spi.
Deleting now unused module caravel_clocking.
Deleting now unused module even.
Deleting now unused module odd.
Deleting now unused module mgmt_soc_regs.
Deleting now unused module mgmt_soc.
<suppressed ~37 debug messages>

13.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~1045 debug messages>

13.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 395 unused cells and 4411 unused wires.
<suppressed ~498 debug messages>

13.6. Executing CHECK pass (checking for obvious problems).
checking module mgmt_core..
Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.sck:
    port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6440 ($mux)
    port Y[0] of cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:193$1362 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.csb:
    port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6435 ($mux)
    port Y[0] of cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:192$1358 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.sdo:
    port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6430 ($mux)
    port Y[0] of cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:198$1364 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\housekeeping.pass_thru_user_sdi:
    port Y[0] of cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:135$2951 ($mux)
    port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6470 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\housekeeping.pass_thru_user_sck:
    port Y[0] of cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:134$2949 ($mux)
    port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6465 ($mux)
Warning: multiple conflicting drivers for mgmt_core.\housekeeping.pass_thru_user_csb:
    port Y[0] of cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:133$2947 ($mux)
    port Y[0] of cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:161$6460 ($mux)
Warning: Wire mgmt_core.\pwr_ctrl_out [3] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [2] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [1] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [0] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [31] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [30] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [29] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [28] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [27] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [26] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [25] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [24] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [23] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [22] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [21] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [20] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [19] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [18] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [17] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [16] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [15] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [14] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [13] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [12] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [11] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [10] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [9] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [8] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [7] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [6] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [5] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [4] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [3] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [2] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [1] is used but has no driver.
Warning: Wire mgmt_core.\soc.simpleuart.simpleuart_reg_cfg_do [0] is used but has no driver.
Warning: Wire mgmt_core.\soc.intercon.wbs_dat_i [387] is used but has no driver.
Warning: Wire mgmt_core.\soc.intercon.wbs_dat_i [386] is used but has no driver.
Warning: Wire mgmt_core.\soc.cpu.picorv32_core.irq [4] is used but has no driver.
found and reported 45 problems.

13.7. Executing OPT pass (performing simple optimizations).

13.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

13.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
<suppressed ~2415 debug messages>
Removed a total of 805 cells.

13.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port A of cell $flatten\housekeeping.\U1.$procmux$14195: \housekeeping.U1.pre_pass_thru_user -> 1'0
      Replacing known input bits on port A of cell $flatten\housekeeping.\U1.$procmux$14221: \housekeeping.U1.pre_pass_thru_mgmt -> 1'0
      Replacing known input bits on port A of cell $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14113: \soc.cpu.picorv32_core.pcpi_mul.mul_waiting -> 1'0
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10354.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10361.
    dead port 3/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$10387.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7556.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7566.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7568.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7574.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7581.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7583.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7589.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7598.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7618.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7624.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7627.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7640.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7647.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7650.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7663.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7675.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7678.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7687.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7690.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7698.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7700.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7703.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7717.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7719.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7721.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7724.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7737.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7739.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7742.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7754.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7757.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7764.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7766.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7769.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7792.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7794.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7796.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7799.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7821.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7823.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7826.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7845.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7847.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7850.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7869.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7871.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7874.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7895.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7898.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7912.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7915.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7917.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7919.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7922.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7932.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7937.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7940.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7963.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7966.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7968.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7970.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7973.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7985.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$7988.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8031.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8044.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8057.
    dead port 4/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8287.
    dead port 5/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8287.
    dead port 2/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8330.
    dead port 7/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8330.
    dead port 8/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8330.
    dead port 4/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8537.
    dead port 5/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8537.
    dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8605.
    dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8620.
    dead port 2/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8624.
    dead port 7/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8624.
    dead port 8/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8624.
    dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8808.
    dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8820.
    dead port 2/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8824.
    dead port 7/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8824.
    dead port 8/12 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8824.
    dead port 2/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9008.
    dead port 7/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9008.
    dead port 8/11 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9008.
    dead port 4/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9058.
    dead port 5/8 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9058.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9199.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9208.
    dead port 2/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11658.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11661.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11833.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11836.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11839.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11845.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11848.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11851.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11857.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11860.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11863.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11869.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11872.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11875.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11881.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11884.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11887.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11893.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11896.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11899.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11905.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11908.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11911.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11917.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11920.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11923.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11929.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11932.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11935.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11941.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11944.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11947.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11953.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11956.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11959.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11965.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11968.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11971.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11977.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11980.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11983.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11989.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11992.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11995.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12001.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12004.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12007.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12013.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12016.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12019.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12025.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12028.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12031.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12037.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12040.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12043.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12049.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12052.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12055.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12061.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12064.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12067.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12073.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12076.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12079.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12085.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12088.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12091.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12097.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12100.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12103.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12109.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12112.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12115.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12121.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12124.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12127.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12133.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12136.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12139.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12145.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12148.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12151.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12157.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12160.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12163.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12169.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12172.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12175.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12181.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12184.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12187.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12193.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12196.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12199.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12205.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12208.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12211.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12217.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12220.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12223.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12229.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12232.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12235.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12241.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12244.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12247.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12253.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12256.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12259.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12265.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12268.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12271.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12277.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12280.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12283.
    dead port 2/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12289.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12292.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12295.
    dead port 2/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12301.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12304.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12307.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12322.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12325.
    dead port 1/2 on $mux $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12331.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13432.
    dead port 1/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13434.
    dead port 2/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13434.
    dead port 3/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13434.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13438.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13445.
    dead port 1/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13447.
    dead port 2/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13447.
    dead port 3/4 on $pmux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13447.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13451.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13471.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13473.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13482.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13484.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13506.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13508.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13518.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13520.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13530.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13540.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13550.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13560.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13570.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13580.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13588.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13596.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13606.
    dead port 2/2 on $mux $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13632.
Removed 247 multiplexer ports.
<suppressed ~580 debug messages>

13.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    New input vector for $reduce_or cell $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:329$6890: { \soc.cpu.picorv32_core.pcpi_mul.pcpi_ready \soc.cpu.picorv32_core.pcpi_div.pcpi_ready }
    New input vector for $reduce_or cell $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:328$6886: { \soc.cpu.picorv32_core.pcpi_mul.pcpi_wait \soc.cpu.picorv32_core.pcpi_div.pcpi_wait }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10133: { $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15086 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10148: { $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15088 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10166: $auto$opt_reduce.cc:134:opt_mux$15090
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10179: $auto$opt_reduce.cc:134:opt_mux$15092
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10204: { $auto$opt_reduce.cc:134:opt_mux$15094 $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10239: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15096 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10254: { $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15098 $flatten\soc.\cpu.\picorv32_core.$procmux$10149_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10281: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $auto$opt_reduce.cc:134:opt_mux$15100 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10294: $auto$opt_reduce.cc:134:opt_mux$15102
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10320: { $auto$opt_reduce.cc:134:opt_mux$15106 $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15104 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10339: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $auto$opt_reduce.cc:134:opt_mux$15108 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$7608: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $auto$opt_reduce.cc:134:opt_mux$15110 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$7630: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $auto$opt_reduce.cc:134:opt_mux$15112 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$7653: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $auto$opt_reduce.cc:134:opt_mux$15114 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8021: { $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP $auto$opt_reduce.cc:134:opt_mux$15116 }
    New ctrl vector for $mux cell $flatten\housekeeping.\U1.$procmux$14195: { }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8034: { $auto$opt_reduce.cc:134:opt_mux$15118 $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP }
    New ctrl vector for $mux cell $flatten\housekeeping.\U1.$procmux$14221: { }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8047: { $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $auto$opt_reduce.cc:134:opt_mux$15120 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8330: $auto$opt_reduce.cc:134:opt_mux$15122
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8374: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8514: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $auto$opt_reduce.cc:134:opt_mux$15124 }
    New ctrl vector for $mux cell $flatten\housekeeping.\U1.$procmux$14360: { }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8537: { \soc.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$15126 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8624: { \soc.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$15130 $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y $auto$opt_reduce.cc:134:opt_mux$15128 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8798: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8824: { \soc.cpu.picorv32_core.instr_trap $auto$opt_reduce.cc:134:opt_mux$15134 $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y $auto$opt_reduce.cc:134:opt_mux$15132 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9008: { \soc.cpu.picorv32_core.is_lui_auipc_jal $auto$opt_reduce.cc:134:opt_mux$15136 $flatten\soc.\cpu.\picorv32_core.$procmux$8331_CTRL }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9058: { \soc.cpu.picorv32_core.is_lui_auipc_jal $auto$opt_reduce.cc:134:opt_mux$15138 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9194: $auto$opt_reduce.cc:134:opt_mux$15140
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9284: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15142 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9302: $auto$opt_reduce.cc:134:opt_mux$15144
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9370: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP $auto$opt_reduce.cc:134:opt_mux$15146 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9388: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $auto$opt_reduce.cc:134:opt_mux$15148 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9436: { $auto$opt_reduce.cc:134:opt_mux$15150 $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9457: $auto$opt_reduce.cc:134:opt_mux$15152
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9578: { $flatten\soc.\cpu.\picorv32_core.$procmux$9586_CMP $auto$opt_reduce.cc:134:opt_mux$15154 $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10143_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9590: $auto$opt_reduce.cc:134:opt_mux$15156
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9746: $auto$opt_reduce.cc:134:opt_mux$15158
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.\cpuregs.$procmux$14616:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936
      New ports: A=1'0, B=1'1, Y=$flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0]
      New connections: $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [31:1] = { $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] $flatten\soc.\cpu.\picorv32_core.\cpuregs.$0$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN[31:0]$2936 [0] }
    New ctrl vector for $pmux cell $flatten\soc.\simpleuart.\simpleuart.$procmux$13279: $auto$opt_reduce.cc:134:opt_mux$15160
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13839: { $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP $auto$opt_reduce.cc:134:opt_mux$15162 $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13421: $auto$opt_reduce.cc:134:opt_mux$15164
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13566: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$15166 }
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13576: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$15168 }
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13585: $auto$opt_reduce.cc:134:opt_mux$15170
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13593: $auto$opt_reduce.cc:134:opt_mux$15172
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13602: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$15174 }
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13628: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$15176 }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15121: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer \soc.cpu.picorv32_core.is_lui_auipc_jal \soc.cpu.picorv32_core.is_slli_srli_srai \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15125: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15127: { \soc.cpu.picorv32_core.is_lui_auipc_jal \soc.cpu.picorv32_core.is_slli_srli_srai \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15129: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15131: { \soc.cpu.picorv32_core.is_lui_auipc_jal \soc.cpu.picorv32_core.is_slli_srli_srai \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15133: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15135: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15137: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer }
  Optimizing cells in module \mgmt_core.
Performed a total of 59 changes.

13.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
<suppressed ~312 debug messages>
Removed a total of 104 cells.

13.7.6. Executing OPT_DFF pass (perform DFF optimizations).

13.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 1142 unused wires.
<suppressed ~32 debug messages>

13.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

13.7.9. Rerunning OPT passes. (Maybe there is more to do..)

13.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $flatten\soc.\cpu.\picorv32_core.$procmux$10392: { \soc.cpu.picorv32_core.pcpi_mul.pcpi_wr \soc.cpu.picorv32_core.pcpi_div.pcpi_wr } -> 2'11
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~599 debug messages>

13.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10177: { $flatten\soc.\cpu.\picorv32_core.$procmux$10165_CMP $auto$opt_reduce.cc:134:opt_mux$15178 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10392: $auto$opt_reduce.cc:134:opt_mux$15180
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$7630: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $auto$opt_reduce.cc:134:opt_mux$15182 $auto$opt_reduce.cc:134:opt_mux$15112 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8138: $auto$opt_reduce.cc:134:opt_mux$15184
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8155: { $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $auto$opt_reduce.cc:134:opt_mux$15186 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8583: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP $auto$opt_reduce.cc:134:opt_mux$15188 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9167: $auto$opt_reduce.cc:134:opt_mux$15190
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9472: $auto$opt_reduce.cc:134:opt_mux$15192
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13696: $auto$opt_reduce.cc:134:opt_mux$15194
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13746: { $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP $auto$opt_reduce.cc:134:opt_mux$15196 $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP }
  Optimizing cells in module \mgmt_core.
Performed a total of 10 changes.

13.7.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.

13.7.13. Executing OPT_DFF pass (perform DFF optimizations).

13.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 5 unused wires.
<suppressed ~1 debug messages>

13.7.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

13.7.16. Rerunning OPT passes. (Maybe there is more to do..)

13.7.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$10392.
Removed 1 multiplexer ports.
<suppressed ~599 debug messages>

13.7.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
Performed a total of 0 changes.

13.7.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

13.7.20. Executing OPT_DFF pass (perform DFF optimizations).

13.7.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

13.7.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

13.7.23. Rerunning OPT passes. (Maybe there is more to do..)

13.7.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~599 debug messages>

13.7.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
Performed a total of 0 changes.

13.7.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

13.7.27. Executing OPT_DFF pass (perform DFF optimizations).

13.7.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

13.7.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

13.7.30. Finished OPT passes. (There is nothing left to do.)

13.8. Executing FSM pass (extract and optimize FSM).

13.8.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking mgmt_core.$flatten\soc.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:848$2932_EN as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register mgmt_core.housekeeping.U1.state.
Found FSM state register mgmt_core.soc.cpu.picorv32_core.cpu_state.
Not marking mgmt_core.soc.cpu.picorv32_core.irq_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking mgmt_core.soc.cpu.picorv32_core.mem_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register mgmt_core.soc.cpu.picorv32_core.mem_wordsize.
Found FSM state register mgmt_core.soc.cpu.state.
Not marking mgmt_core.soc.mprj_ctrl.mprj_ctrl.xfer_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register mgmt_core.soc.simple_spi_master_inst.spi_master.state.
Not marking mgmt_core.soc.spimemio.spimemio.din_tag as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register mgmt_core.soc.spimemio.spimemio.state.

13.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\housekeeping.U1.state' from module `\mgmt_core'.
  found $adff cell for state register: $flatten\housekeeping.\U1.$procdff$15025
  root of input selection tree: $flatten\housekeeping.\U1.$0\state[2:0]
  found reset state: 3'000 (from async reset)
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:418$3013_Y
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:350$2997_Y
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:366$3003_Y
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:382$3006_Y
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:459$3030_Y
  found state code: 3'010
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:369$3005_Y
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:423$3016_Y
  found ctrl input: $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017_Y
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:427$3018_Y
  found ctrl input: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:429$3019_Y
  found ctrl input: \housekeeping.U1.pre_pass_thru_mgmt
  found ctrl input: \housekeeping.U1.pre_pass_thru_user
  found state code: 3'001
  found state code: 3'100
  found state code: 3'101
  found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:366$3003_Y
  found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3008_Y
  found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3009_Y
  found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:418$3013_Y
  found ctrl output: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:350$2997_Y
  ctrl inputs: { $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:459$3030_Y \housekeeping.U1.pre_pass_thru_mgmt \housekeeping.U1.pre_pass_thru_user $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:369$3005_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:382$3006_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:423$3016_Y $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:427$3018_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:429$3019_Y }
  ctrl outputs: { $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:350$2997_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:366$3003_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3008_Y $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3009_Y $flatten\housekeeping.\U1.$0\state[2:0] $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:418$3013_Y }
  transition:      3'000 9'---000000 ->      3'000 8'00000001
  transition:      3'000 9'-00010000 ->      3'001 8'00000011
  transition:      3'000 9'-01010000 ->      3'100 8'00001001
  transition:      3'000 9'-1-010000 ->      3'101 8'00001011
  transition:      3'000 9'---0-0001 ->      3'000 8'00000001
  transition:      3'000 9'---0-001- ->      3'000 8'00000001
  transition:      3'000 9'---0-01-- ->      3'000 8'00000001
  transition:      3'000 9'---0-1--- ->      3'000 8'00000001
  transition:      3'000 9'---1----- ->      3'000 8'00000001
  transition:      3'100 9'--------- ->      3'100 8'00011000
  transition:      3'010 9'----0---- ->      3'010 8'01000100
  transition:      3'010 9'0---1---- ->      3'010 8'01000100
  transition:      3'010 9'1---1---- ->      3'000 8'01000000
  transition:      3'001 9'----0---- ->      3'001 8'10000010
  transition:      3'001 9'----1---- ->      3'010 8'10000100
  transition:      3'101 9'--------- ->      3'101 8'00101010
Extracting FSM `\soc.cpu.picorv32_core.cpu_state' from module `\mgmt_core'.
  found $dff cell for state register: $flatten\soc.\cpu.\picorv32_core.$procdff$14682
  root of input selection tree: $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0]
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1933$7529_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1917$7512_Y
  found ctrl input: \soc.cpu.wb_rst_i
  found ctrl input: $auto$opt_reduce.cc:134:opt_mux$15184
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1867$7497_Y
  found state code: 8'01000000
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1826$7475_Y
  found ctrl input: \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu
  found ctrl input: \soc.cpu.picorv32_core.mem_done
  found ctrl input: \soc.cpu.picorv32_core.is_sb_sh_sw
  found ctrl input: \soc.cpu.picorv32_core.instr_trap
  found state code: 8'00001000
  found state code: 8'00000010
  found ctrl input: \soc.cpu.picorv32_core.pcpi_int_ready
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1600$7429_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1603$7433_Y
  found state code: 8'10000000
  found ctrl input: $auto$opt_reduce.cc:134:opt_mux$15128
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y
  found ctrl input: $auto$opt_reduce.cc:134:opt_mux$15126
  found state code: 8'00000001
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1533$7408_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1543$7416_Y
  found ctrl input: \soc.cpu.picorv32_core.decoder_trigger
  found ctrl input: \soc.cpu.picorv32_core.instr_jal
  found state code: 8'00100000
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7522_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7515_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1920$7519_Y
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7616_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y
  ctrl inputs: { $auto$opt_reduce.cc:134:opt_mux$15128 $auto$opt_reduce.cc:134:opt_mux$15126 $auto$opt_reduce.cc:134:opt_mux$15184 \soc.cpu.picorv32_core.pcpi_int_ready \soc.cpu.picorv32_core.mem_done \soc.cpu.picorv32_core.instr_jal \soc.cpu.picorv32_core.instr_trap \soc.cpu.picorv32_core.decoder_trigger \soc.cpu.picorv32_core.is_sb_sh_sw \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1533$7408_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1543$7416_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1600$7429_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1603$7433_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1826$7475_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1867$7497_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1917$7512_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7515_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1920$7519_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7522_Y $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1933$7529_Y \soc.cpu.wb_rst_i }
  ctrl outputs: { $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7616_CMP }
  transition: 8'10000000 24'------------------0---00 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------0---01 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------10-000 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------10-001 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------11000- -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------111000 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------111001 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------1-010- -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------101100 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------101101 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------111100 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------111101 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'--------------------0-1- -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------0-1-10 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------0-1-11 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------101010 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------101011 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------111010 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------111011 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------101110 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------101111 -> 8'01000000 16'0010000000000001
  transition: 8'10000000 24'------------------111110 -> 8'10000000 16'0100000000000001
  transition: 8'10000000 24'------------------111111 -> 8'01000000 16'0010000000000001
  transition: 8'01000000 24'-------0--00------0---00 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------0---00 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------0---00 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------0---00 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------0---00 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------0---01 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-------0--00------10-000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------10-000 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------10-000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------10-000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------10-000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------10-001 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------11000- -> 8'10000000 16'1100000000000000
  transition: 8'01000000 24'-------0--00------111000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------111000 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------111000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------111000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------111000 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------111001 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------1-010- -> 8'10000000 16'1100000000000000
  transition: 8'01000000 24'-------0--00------101100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------101100 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------101100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------101100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------101100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------101101 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-------0--00------111100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------111100 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------111100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------111100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------111100 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------111101 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'--------------------0-1- -> 8'10000000 16'1100000000000000
  transition: 8'01000000 24'-------0--00------0-1-10 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------0-1-10 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------0-1-10 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------0-1-10 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------0-1-10 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------0-1-11 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-------0--00------101010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------101010 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------101010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------101010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------101010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------101011 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-------0--00------111010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------111010 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------111010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------111010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------111010 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------111011 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-------0--00------101110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------101110 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------101110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------101110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------101110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------101111 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-------0--00------111110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'-----0-1--00------111110 -> 8'00100000 16'1001000000000000
  transition: 8'01000000 24'-----1-1--00------111110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------01------111110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'----------1-------111110 -> 8'01000000 16'1010000000000000
  transition: 8'01000000 24'------------------111111 -> 8'01000000 16'1010000000000000
  transition: 8'00100000 24'00----0-0-----0---0---00 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---0---00 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----0---00 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----0---00 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----0---00 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------0---00 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------0---00 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---0---00 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------0---00 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------0---01 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'00----0-0-----0---10-000 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---10-000 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----10-000 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----10-000 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----10-000 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------10-000 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------10-000 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---10-000 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------10-000 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------10-001 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'------------------11000- -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'00----0-0-----0---111000 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---111000 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----111000 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----111000 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----111000 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------111000 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------111000 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---111000 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------111000 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------111001 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'------------------1-010- -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'00----0-0-----0---101100 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---101100 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----101100 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----101100 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----101100 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------101100 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------101100 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---101100 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------101100 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------101101 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'00----0-0-----0---111100 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---111100 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----111100 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----111100 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----111100 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------111100 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------111100 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---111100 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------111100 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------111101 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------------0-1- -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'00----0-0-----0---0-1-10 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---0-1-10 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----0-1-10 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----0-1-10 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----0-1-10 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------0-1-10 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------0-1-10 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---0-1-10 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------0-1-10 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------0-1-11 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'00----0-0-----0---101010 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---101010 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----101010 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----101010 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----101010 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------101010 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------101010 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---101010 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------101010 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------101011 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'00----0-0-----0---111010 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---111010 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----111010 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----111010 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----111010 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------111010 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------111010 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---111010 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------111010 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------111011 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'00----0-0-----0---101110 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---101110 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----101110 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----101110 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----101110 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------101110 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------101110 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---101110 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------101110 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------101111 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'00----0-0-----0---111110 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'00------1-----0---111110 -> 8'00000010 16'0000000100000010
  transition: 8'00100000 24'---0--1-----0-----111110 -> 8'00100000 16'0001000000000010
  transition: 8'00100000 24'---0--1-----10----111110 -> 8'10000000 16'0100000000000010
  transition: 8'00100000 24'---0--1-----11----111110 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'---1--1-----------111110 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'-1----------------111110 -> 8'01000000 16'0010000000000010
  transition: 8'00100000 24'--------------1---111110 -> 8'00000001 16'0000000010000010
  transition: 8'00100000 24'1-----------------111110 -> 8'00001000 16'0000010000000010
  transition: 8'00100000 24'------------------111111 -> 8'01000000 16'0010000000000010
  transition: 8'00001000 24'---------0--------0---00 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------0---00 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------0---00 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------0---01 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'---------0--------10-000 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------10-000 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------10-000 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------10-001 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------11000- -> 8'10000000 16'0100000000001000
  transition: 8'00001000 24'---------0--------111000 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------111000 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------111000 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------111001 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------1-010- -> 8'10000000 16'0100000000001000
  transition: 8'00001000 24'---------0--------101100 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------101100 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------101100 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------101101 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'---------0--------111100 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------111100 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------111100 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------111101 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'--------------------0-1- -> 8'10000000 16'0100000000001000
  transition: 8'00001000 24'---------0--------0-1-10 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------0-1-10 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------0-1-10 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------0-1-11 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'---------0--------101010 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------101010 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------101010 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------101011 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'---------0--------111010 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------111010 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------111010 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------111011 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'---------0--------101110 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------101110 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------101110 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------101111 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'---------0--------111110 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'----0----1--------111110 -> 8'00001000 16'0000010000001000
  transition: 8'00001000 24'----1----1--------111110 -> 8'01000000 16'0010000000001000
  transition: 8'00001000 24'------------------111111 -> 8'01000000 16'0010000000001000
  transition: 8'00000010 24'----------------0-0---00 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------100---00 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------110---00 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------0---01 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'----------------0-10-000 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------1010-000 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------1110-000 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------10-001 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------11000- -> 8'10000000 16'0100000000100000
  transition: 8'00000010 24'----------------0-111000 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------10111000 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------11111000 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------111001 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------1-010- -> 8'10000000 16'0100000000100000
  transition: 8'00000010 24'----------------0-101100 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------10101100 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------11101100 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------101101 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'----------------0-111100 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------10111100 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------11111100 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------111101 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'--------------------0-1- -> 8'10000000 16'0100000000100000
  transition: 8'00000010 24'----------------0-0-1-10 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------100-1-10 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------110-1-10 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------0-1-11 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'----------------0-101010 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------10101010 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------11101010 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------101011 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'----------------0-111010 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------10111010 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------11111010 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------111011 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'----------------0-101110 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------10101110 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------11101110 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------101111 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'----------------0-111110 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------10111110 -> 8'00000010 16'0000000100100000
  transition: 8'00000010 24'----------------11111110 -> 8'01000000 16'0010000000100000
  transition: 8'00000010 24'------------------111111 -> 8'01000000 16'0010000000100000
  transition: 8'00000001 24'----------------0-0---00 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------100---00 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------110---00 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------0---01 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'----------------0-10-000 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------1010-000 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------1110-000 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------10-001 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------11000- -> 8'10000000 16'0100000001000000
  transition: 8'00000001 24'----------------0-111000 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------10111000 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------11111000 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------111001 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------1-010- -> 8'10000000 16'0100000001000000
  transition: 8'00000001 24'----------------0-101100 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------10101100 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------11101100 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------101101 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'----------------0-111100 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------10111100 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------11111100 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------111101 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'--------------------0-1- -> 8'10000000 16'0100000001000000
  transition: 8'00000001 24'----------------0-0-1-10 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------100-1-10 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------110-1-10 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------0-1-11 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'----------------0-101010 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------10101010 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------11101010 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------101011 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'----------------0-111010 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------10111010 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------11111010 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------111011 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'----------------0-101110 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------10101110 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------11101110 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------101111 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'----------------0-111110 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------10111110 -> 8'00000001 16'0000000011000000
  transition: 8'00000001 24'----------------11111110 -> 8'01000000 16'0010000001000000
  transition: 8'00000001 24'------------------111111 -> 8'01000000 16'0010000001000000
Extracting FSM `\soc.cpu.picorv32_core.mem_wordsize' from module `\mgmt_core'.
  found $dff cell for state register: $flatten\soc.\cpu.\picorv32_core.$procdff$14669
  root of input selection tree: $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0]
  found ctrl input: \soc.cpu.wb_rst_i
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y
  found ctrl input: \soc.cpu.picorv32_core.mem_do_rdata
  found ctrl input: \soc.cpu.picorv32_core.instr_lw
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1882$7502_Y
  found ctrl input: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1881$7501_Y
  found state code: 2'00
  found state code: 2'01
  found state code: 2'10
  found ctrl input: \soc.cpu.picorv32_core.mem_do_wdata
  found ctrl input: \soc.cpu.picorv32_core.instr_sw
  found ctrl input: \soc.cpu.picorv32_core.instr_sh
  found ctrl input: \soc.cpu.picorv32_core.instr_sb
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$procmux$10355_CMP
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7520_Y
  found ctrl output: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7513_Y
  ctrl inputs: { \soc.cpu.picorv32_core.mem_do_rdata \soc.cpu.picorv32_core.mem_do_wdata \soc.cpu.picorv32_core.instr_lw \soc.cpu.picorv32_core.instr_sb \soc.cpu.picorv32_core.instr_sh \soc.cpu.picorv32_core.instr_sw $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1881$7501_Y $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1882$7502_Y $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP \soc.cpu.wb_rst_i }
  ctrl outputs: { $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0] $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7513_Y $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7520_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10355_CMP }
  transition:       2'00 13'------0---000 ->       2'00 5'00100
  transition:       2'00 13'------1-----0 ->       2'00 5'00100
  transition:       2'00 13'-------0---10 ->       2'00 5'00100
  transition:       2'00 13'-0-000-1---10 -> INVALID_STATE(2'xx) 5'xx100  <ignored invalid transition!>
  transition:       2'00 13'-0-1---1---10 ->       2'10 5'10100
  transition:       2'00 13'-0--1--1---10 ->       2'01 5'01100
  transition:       2'00 13'-0---1-1---10 ->       2'00 5'00100
  transition:       2'00 13'-1-----1---10 ->       2'00 5'00100
  transition:       2'00 13'-------0--1-0 ->       2'00 5'00100
  transition:       2'00 13'0-0----1001-0 -> INVALID_STATE(2'xx) 5'xx100  <ignored invalid transition!>
  transition:       2'00 13'0------11-1-0 ->       2'10 5'10100
  transition:       2'00 13'0------1-11-0 ->       2'01 5'01100
  transition:       2'00 13'0-1----1--1-0 ->       2'00 5'00100
  transition:       2'00 13'1------1--1-0 ->       2'00 5'00100
  transition:       2'00 13'------------1 ->       2'00 5'00100
  transition:       2'10 13'------0---000 ->       2'10 5'10001
  transition:       2'10 13'------1-----0 ->       2'00 5'00001
  transition:       2'10 13'-------0---10 ->       2'10 5'10001
  transition:       2'10 13'-0-000-1---10 -> INVALID_STATE(2'xx) 5'xx001  <ignored invalid transition!>
  transition:       2'10 13'-0-1---1---10 ->       2'10 5'10001
  transition:       2'10 13'-0--1--1---10 ->       2'01 5'01001
  transition:       2'10 13'-0---1-1---10 ->       2'00 5'00001
  transition:       2'10 13'-1-----1---10 ->       2'10 5'10001
  transition:       2'10 13'-------0--1-0 ->       2'10 5'10001
  transition:       2'10 13'0-0----1001-0 -> INVALID_STATE(2'xx) 5'xx001  <ignored invalid transition!>
  transition:       2'10 13'0------11-1-0 ->       2'10 5'10001
  transition:       2'10 13'0------1-11-0 ->       2'01 5'01001
  transition:       2'10 13'0-1----1--1-0 ->       2'00 5'00001
  transition:       2'10 13'1------1--1-0 ->       2'10 5'10001
  transition:       2'10 13'------------1 ->       2'10 5'10001
  transition:       2'01 13'------0---000 ->       2'01 5'01010
  transition:       2'01 13'------1-----0 ->       2'00 5'00010
  transition:       2'01 13'-------0---10 ->       2'01 5'01010
  transition:       2'01 13'-0-000-1---10 -> INVALID_STATE(2'xx) 5'xx010  <ignored invalid transition!>
  transition:       2'01 13'-0-1---1---10 ->       2'10 5'10010
  transition:       2'01 13'-0--1--1---10 ->       2'01 5'01010
  transition:       2'01 13'-0---1-1---10 ->       2'00 5'00010
  transition:       2'01 13'-1-----1---10 ->       2'01 5'01010
  transition:       2'01 13'-------0--1-0 ->       2'01 5'01010
  transition:       2'01 13'0-0----1001-0 -> INVALID_STATE(2'xx) 5'xx010  <ignored invalid transition!>
  transition:       2'01 13'0------11-1-0 ->       2'10 5'10010
  transition:       2'01 13'0------1-11-0 ->       2'01 5'01010
  transition:       2'01 13'0-1----1--1-0 ->       2'00 5'00010
  transition:       2'01 13'1------1--1-0 ->       2'01 5'01010
  transition:       2'01 13'------------1 ->       2'01 5'01010
Extracting FSM `\soc.cpu.state' from module `\mgmt_core'.
  found $dff cell for state register: $flatten\soc.\cpu.$procdff$14886
  root of input selection tree: $flatten\soc.\cpu.$0\state[1:0]
  found reset state: 2'00 (guessed from mux tree)
  found ctrl input: \soc.cpu.wb_rst_i
  found ctrl input: $flatten\soc.\cpu.$procmux$12350_CMP
  found ctrl input: $flatten\soc.\cpu.$procmux$12354_CMP
  found state code: 2'00
  found ctrl input: \soc.cpu.wbm_ack_i
  found state code: 2'10
  found ctrl input: \soc.cpu.picorv32_core.mem_valid
  found state code: 2'01
  found ctrl output: $flatten\soc.\cpu.$procmux$12350_CMP
  found ctrl output: $flatten\soc.\cpu.$procmux$12354_CMP
  found ctrl output: $flatten\soc.\cpu.$procmux$12441_CMP
  ctrl inputs: { \soc.cpu.picorv32_core.mem_valid \soc.cpu.wbm_ack_i \soc.cpu.wb_rst_i }
  ctrl outputs: { $flatten\soc.\cpu.$procmux$12441_CMP $flatten\soc.\cpu.$procmux$12354_CMP $flatten\soc.\cpu.$procmux$12350_CMP $flatten\soc.\cpu.$0\state[1:0] }
  transition:       2'00 3'0-0 ->       2'00 5'01000
  transition:       2'00 3'1-0 ->       2'01 5'01001
  transition:       2'00 3'--1 ->       2'00 5'01000
  transition:       2'10 3'--0 ->       2'00 5'10000
  transition:       2'10 3'--1 ->       2'00 5'10000
  transition:       2'01 3'-00 ->       2'01 5'00101
  transition:       2'01 3'-10 ->       2'10 5'00110
  transition:       2'01 3'--1 ->       2'00 5'00100
Extracting FSM `\soc.simple_spi_master_inst.spi_master.state' from module `\mgmt_core'.
  found $adff cell for state register: $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14916
  root of input selection tree: $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0]
  found reset state: 2'00 (from async reset)
  found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:292$1392_Y
  found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1375_Y
  found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1376_Y
  found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:310$1399_Y
  found ctrl input: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:305$1398_Y
  found state code: 2'01
  found state code: 2'11
  found state code: 2'10
  found ctrl input: \soc.simple_spi_master_inst.spi_master.w_latched
  found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:310$1399_Y
  found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:292$1392_Y
  found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1376_Y
  found ctrl output: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1375_Y
  ctrl inputs: { \soc.simple_spi_master_inst.spi_master.w_latched $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:305$1398_Y }
  ctrl outputs: { $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1375_Y $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1376_Y $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0] $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:292$1392_Y $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:310$1399_Y }
  transition:       2'00 2'0- ->       2'00 6'000010
  transition:       2'00 2'1- ->       2'01 6'000110
  transition:       2'10 2'-0 ->       2'01 6'010100
  transition:       2'10 2'-1 ->       2'11 6'011100
  transition:       2'01 2'-- ->       2'10 6'101000
  transition:       2'11 2'-- ->       2'00 6'000001
Extracting FSM `\soc.spimemio.spimemio.state' from module `\mgmt_core'.
  found $dff cell for state register: $flatten\soc.\spimemio.\spimemio.$procdff$14960
  root of input selection tree: $flatten\soc.\spimemio.\spimemio.$0\state[3:0]
  found reset state: 4'0000 (guessed from mux tree)
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:373$1216_Y
  found ctrl input: \soc.spimemio.spimemio.jump
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13759_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13762_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13765_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13717_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13697_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13776_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13700_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$procmux$13779_CMP
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:512$1234_Y
  found ctrl input: \soc.spimemio.spimemio.xfer.din_ready
  found state code: 4'1001
  found state code: 4'1100
  found state code: 4'1011
  found state code: 4'1010
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:472$1230_Y
  found state code: 4'1000
  found state code: 4'0111
  found ctrl input: $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1137_Y
  found state code: 4'0110
  found state code: 4'0101
  found ctrl input: \soc.spimemio.spimemio.dout_valid
  found state code: 4'0100
  found state code: 4'0011
  found state code: 4'0010
  found state code: 4'0001
  found ctrl input: \soc.spimemio.spimemio.config_cont
  found state code: 4'0000
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13779_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13776_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13765_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13762_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13759_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13717_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13700_CMP
  found ctrl output: $flatten\soc.\spimemio.\spimemio.$procmux$13697_CMP
  ctrl inputs: { \soc.spimemio.spimemio.dout_valid \soc.spimemio.spimemio.jump \soc.spimemio.spimemio.config_cont $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1137_Y $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:373$1216_Y $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:472$1230_Y $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:512$1234_Y \soc.spimemio.spimemio.xfer.din_ready }
  ctrl outputs: { $flatten\soc.\spimemio.\spimemio.$0\state[3:0] $flatten\soc.\spimemio.\spimemio.$procmux$13697_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13700_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13717_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13759_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13762_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13765_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13776_CMP $flatten\soc.\spimemio.\spimemio.$procmux$13779_CMP }
  transition:     4'0000 8'-0--0--0 ->     4'0000 17'00000000000000001
  transition:     4'0000 8'-0--0--1 ->     4'0001 17'00010000000000001
  transition:     4'0000 8'-10-0--- ->     4'0100 17'01000000000000001
  transition:     4'0000 8'-11-0--- ->     4'0101 17'01010000000000001
  transition:     4'0000 8'----1--- ->     4'0000 17'00000000000000001
  transition:     4'1000 8'-0--0--0 ->     4'1000 17'10000000000100000
  transition:     4'1000 8'-0--0--1 ->     4'1001 17'10010000000100000
  transition:     4'1000 8'-10-0--- ->     4'0100 17'01000000000100000
  transition:     4'1000 8'-11-0--- ->     4'0101 17'01010000000100000
  transition:     4'1000 8'----1--- ->     4'0000 17'00000000000100000
  transition:     4'0100 8'-0--0--0 ->     4'0100 17'01000010000000000
  transition:     4'0100 8'-0--0--1 ->     4'0101 17'01010010000000000
  transition:     4'0100 8'-10-0--- ->     4'0100 17'01000010000000000
  transition:     4'0100 8'-11-0--- ->     4'0101 17'01010010000000000
  transition:     4'0100 8'----1--- ->     4'0000 17'00000010000000000
  transition:     4'1100 8'-0--0-0- ->     4'1100 17'11000001000000000
  transition:     4'1100 8'-0--0-10 ->     4'1100 17'11000001000000000
  transition:     4'1100 8'-0--0-11 ->     4'1001 17'10010001000000000
  transition:     4'1100 8'-10-0--- ->     4'0100 17'01000001000000000
  transition:     4'1100 8'-11-0--- ->     4'0101 17'01010001000000000
  transition:     4'1100 8'----1--- ->     4'0000 17'00000001000000000
  transition:     4'0010 8'-0--0--0 ->     4'0010 17'00100000000000010
  transition:     4'0010 8'-0--0--1 ->     4'0011 17'00110000000000010
  transition:     4'0010 8'-10-0--- ->     4'0100 17'01000000000000010
  transition:     4'0010 8'-11-0--- ->     4'0101 17'01010000000000010
  transition:     4'0010 8'----1--- ->     4'0000 17'00000000000000010
  transition:     4'1010 8'-0--0--0 ->     4'1010 17'10100000010000000
  transition:     4'1010 8'-0--0--1 ->     4'1011 17'10110000010000000
  transition:     4'1010 8'-10-0--- ->     4'0100 17'01000000010000000
  transition:     4'1010 8'-11-0--- ->     4'0101 17'01010000010000000
  transition:     4'1010 8'----1--- ->     4'0000 17'00000000010000000
  transition:     4'0110 8'-0--0--0 ->     4'0110 17'01100000000001000
  transition:     4'0110 8'-0--0--1 ->     4'0111 17'01110000000001000
  transition:     4'0110 8'-10-0--- ->     4'0100 17'01000000000001000
  transition:     4'0110 8'-11-0--- ->     4'0101 17'01010000000001000
  transition:     4'0110 8'----1--- ->     4'0000 17'00000000000001000
  transition:     4'0001 8'00--0--- ->     4'0001 17'00010100000000000
  transition:     4'0001 8'10--0--- ->     4'0010 17'00100100000000000
  transition:     4'0001 8'-10-0--- ->     4'0100 17'01000100000000000
  transition:     4'0001 8'-11-0--- ->     4'0101 17'01010100000000000
  transition:     4'0001 8'----1--- ->     4'0000 17'00000100000000000
  transition:     4'1001 8'-0--0--0 ->     4'1001 17'10010000001000000
  transition:     4'1001 8'-0--0--1 ->     4'1010 17'10100000001000000
  transition:     4'1001 8'-10-0--- ->     4'0100 17'01000000001000000
  transition:     4'1001 8'-11-0--- ->     4'0101 17'01010000001000000
  transition:     4'1001 8'----1--- ->     4'0000 17'00000000001000000
  transition:     4'0101 8'-0-00--- ->     4'0101 17'01010000000000100
  transition:     4'0101 8'-0-10--0 ->     4'0101 17'01010000000000100
  transition:     4'0101 8'-0-10--1 ->     4'0110 17'01100000000000100
  transition:     4'0101 8'-10-0--- ->     4'0100 17'01000000000000100
  transition:     4'0101 8'-11-0--- ->     4'0101 17'01010000000000100
  transition:     4'0101 8'----1--- ->     4'0000 17'00000000000000100
  transition:     4'0011 8'00--0--- ->     4'0011 17'00111000000000000
  transition:     4'0011 8'10--0--- ->     4'0100 17'01001000000000000
  transition:     4'0011 8'-10-0--- ->     4'0100 17'01001000000000000
  transition:     4'0011 8'-11-0--- ->     4'0101 17'01011000000000000
  transition:     4'0011 8'----1--- ->     4'0000 17'00001000000000000
  transition:     4'1011 8'-0--0--0 ->     4'1011 17'10110000100000000
  transition:     4'1011 8'-0--0--1 ->     4'1100 17'11000000100000000
  transition:     4'1011 8'-10-0--- ->     4'0100 17'01000000100000000
  transition:     4'1011 8'-11-0--- ->     4'0101 17'01010000100000000
  transition:     4'1011 8'----1--- ->     4'0000 17'00000000100000000
  transition:     4'0111 8'-0--0--0 ->     4'0111 17'01110000000010000
  transition:     4'0111 8'-0--00-1 ->     4'1001 17'10010000000010000
  transition:     4'0111 8'-0--01-1 ->     4'1000 17'10000000000010000
  transition:     4'0111 8'-10-0--- ->     4'0100 17'01000000000010000
  transition:     4'0111 8'-11-0--- ->     4'0101 17'01010000000010000
  transition:     4'0111 8'----1--- ->     4'0000 17'00000000000010000

13.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `\mgmt_core'.
Optimizing FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `\mgmt_core'.
Optimizing FSM `$fsm$\soc.cpu.state$15219' from module `\mgmt_core'.
  Merging pattern 3'--0 and 3'--1 from group (1 0 5'10000).
  Merging pattern 3'--1 and 3'--0 from group (1 0 5'10000).
Optimizing FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `\mgmt_core'.
Optimizing FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `\mgmt_core'.
  Merging pattern 24'------------------111000 and 24'------------------111010 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------101100 and 24'------------------101110 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------111100 and 24'------------------111110 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------111010 and 24'------------------111000 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------101110 and 24'------------------101100 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------111110 and 24'------------------111100 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------1110-0 and 24'------------------1111-0 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------1111-0 and 24'------------------1110-0 from group (0 0 16'0100000000000001).
  Merging pattern 24'------------------111001 and 24'------------------111011 from group (0 1 16'0010000000000001).
  Merging pattern 24'------------------101101 and 24'------------------101111 from group (0 1 16'0010000000000001).
  Merging pattern 24'------------------111101 and 24'------------------111111 from group (0 1 16'0010000000000001).
  Merging pattern 24'------------------111011 and 24'------------------111001 from group (0 1 16'0010000000000001).
  Merging pattern 24'------------------101111 and 24'------------------101101 from group (0 1 16'0010000000000001).
  Merging pattern 24'------------------111111 and 24'------------------111101 from group (0 1 16'0010000000000001).
  Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (0 1 16'0010000000000001).
  Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (0 1 16'0010000000000001).
  Merging pattern 24'-------0--00------111000 and 24'-------0--00------111010 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------111000 and 24'-----1-1--00------111010 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------111000 and 24'----------01------111010 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------111000 and 24'----------1-------111010 from group (1 1 16'1010000000000000).
  Merging pattern 24'-------0--00------101100 and 24'-------0--00------101110 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------101100 and 24'-----1-1--00------101110 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------101100 and 24'----------01------101110 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------101100 and 24'----------1-------101110 from group (1 1 16'1010000000000000).
  Merging pattern 24'-------0--00------111100 and 24'-------0--00------111110 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------111100 and 24'-----1-1--00------111110 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------111100 and 24'----------01------111110 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------111100 and 24'----------1-------111110 from group (1 1 16'1010000000000000).
  Merging pattern 24'-------0--00------111010 and 24'-------0--00------111000 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------111010 and 24'-----1-1--00------111000 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------111010 and 24'----------01------111000 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------111010 and 24'----------1-------111000 from group (1 1 16'1010000000000000).
  Merging pattern 24'-------0--00------101110 and 24'-------0--00------101100 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------101110 and 24'-----1-1--00------101100 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------101110 and 24'----------01------101100 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------101110 and 24'----------1-------101100 from group (1 1 16'1010000000000000).
  Merging pattern 24'-------0--00------111110 and 24'-------0--00------111100 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------111110 and 24'-----1-1--00------111100 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------111110 and 24'----------01------111100 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------111110 and 24'----------1-------111100 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------111001 and 24'------------------111011 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------101101 and 24'------------------101111 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------111101 and 24'------------------111111 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------111011 and 24'------------------111001 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------101111 and 24'------------------101101 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------111111 and 24'------------------111101 from group (1 1 16'1010000000000000).
  Merging pattern 24'-------0--00------1110-0 and 24'-------0--00------1111-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------1110-0 and 24'-----1-1--00------1111-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------1110-0 and 24'----------01------1111-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------1110-0 and 24'----------1-------1111-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'-------0--00------1111-0 and 24'-------0--00------1110-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----1-1--00------1111-0 and 24'-----1-1--00------1110-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------01------1111-0 and 24'----------01------1110-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'----------1-------1111-0 and 24'----------1-------1110-0 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (1 1 16'1010000000000000).
  Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (1 1 16'1010000000000000).
  Merging pattern 24'-----0-1--00------111000 and 24'-----0-1--00------111010 from group (1 2 16'1001000000000000).
  Merging pattern 24'-----0-1--00------101100 and 24'-----0-1--00------101110 from group (1 2 16'1001000000000000).
  Merging pattern 24'-----0-1--00------111100 and 24'-----0-1--00------111110 from group (1 2 16'1001000000000000).
  Merging pattern 24'-----0-1--00------111010 and 24'-----0-1--00------111000 from group (1 2 16'1001000000000000).
  Merging pattern 24'-----0-1--00------101110 and 24'-----0-1--00------101100 from group (1 2 16'1001000000000000).
  Merging pattern 24'-----0-1--00------111110 and 24'-----0-1--00------111100 from group (1 2 16'1001000000000000).
  Merging pattern 24'-----0-1--00------1110-0 and 24'-----0-1--00------1111-0 from group (1 2 16'1001000000000000).
  Merging pattern 24'-----0-1--00------1111-0 and 24'-----0-1--00------1110-0 from group (1 2 16'1001000000000000).
  Merging pattern 24'---0--1-----10----111000 and 24'---0--1-----10----111010 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----10----101100 and 24'---0--1-----10----101110 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----10----111100 and 24'---0--1-----10----111110 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----10----111010 and 24'---0--1-----10----111000 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----10----101110 and 24'---0--1-----10----101100 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----10----111110 and 24'---0--1-----10----111100 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----10----1110-0 and 24'---0--1-----10----1111-0 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----10----1111-0 and 24'---0--1-----10----1110-0 from group (2 0 16'0100000000000010).
  Merging pattern 24'---0--1-----11----111000 and 24'---0--1-----11----111010 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------111000 and 24'---1--1-----------111010 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------111000 and 24'-1----------------111010 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----11----101100 and 24'---0--1-----11----101110 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------101100 and 24'---1--1-----------101110 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------101100 and 24'-1----------------101110 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----11----111100 and 24'---0--1-----11----111110 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------111100 and 24'---1--1-----------111110 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------111100 and 24'-1----------------111110 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----11----111010 and 24'---0--1-----11----111000 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------111010 and 24'---1--1-----------111000 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------111010 and 24'-1----------------111000 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----11----101110 and 24'---0--1-----11----101100 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------101110 and 24'---1--1-----------101100 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------101110 and 24'-1----------------101100 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----11----111110 and 24'---0--1-----11----111100 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------111110 and 24'---1--1-----------111100 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------111110 and 24'-1----------------111100 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------111001 and 24'------------------111011 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------101101 and 24'------------------101111 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------111101 and 24'------------------111111 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------111011 and 24'------------------111001 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------101111 and 24'------------------101101 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------111111 and 24'------------------111101 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----11----1110-0 and 24'---0--1-----11----1111-0 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------1110-0 and 24'---1--1-----------1111-0 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------1110-0 and 24'-1----------------1111-0 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----11----1111-0 and 24'---0--1-----11----1110-0 from group (2 1 16'0010000000000010).
  Merging pattern 24'---1--1-----------1111-0 and 24'---1--1-----------1110-0 from group (2 1 16'0010000000000010).
  Merging pattern 24'-1----------------1111-0 and 24'-1----------------1110-0 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (2 1 16'0010000000000010).
  Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (2 1 16'0010000000000010).
  Merging pattern 24'---0--1-----0-----111000 and 24'---0--1-----0-----111010 from group (2 2 16'0001000000000010).
  Merging pattern 24'---0--1-----0-----101100 and 24'---0--1-----0-----101110 from group (2 2 16'0001000000000010).
  Merging pattern 24'---0--1-----0-----111100 and 24'---0--1-----0-----111110 from group (2 2 16'0001000000000010).
  Merging pattern 24'---0--1-----0-----111010 and 24'---0--1-----0-----111000 from group (2 2 16'0001000000000010).
  Merging pattern 24'---0--1-----0-----101110 and 24'---0--1-----0-----101100 from group (2 2 16'0001000000000010).
  Merging pattern 24'---0--1-----0-----111110 and 24'---0--1-----0-----111100 from group (2 2 16'0001000000000010).
  Merging pattern 24'---0--1-----0-----1110-0 and 24'---0--1-----0-----1111-0 from group (2 2 16'0001000000000010).
  Merging pattern 24'---0--1-----0-----1111-0 and 24'---0--1-----0-----1110-0 from group (2 2 16'0001000000000010).
  Merging pattern 24'00----0-0-----0---111000 and 24'00----0-0-----0---111010 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------111000 and 24'1-----------------111010 from group (2 3 16'0000010000000010).
  Merging pattern 24'00----0-0-----0---101100 and 24'00----0-0-----0---101110 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------101100 and 24'1-----------------101110 from group (2 3 16'0000010000000010).
  Merging pattern 24'00----0-0-----0---111100 and 24'00----0-0-----0---111110 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------111100 and 24'1-----------------111110 from group (2 3 16'0000010000000010).
  Merging pattern 24'00----0-0-----0---111010 and 24'00----0-0-----0---111000 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------111010 and 24'1-----------------111000 from group (2 3 16'0000010000000010).
  Merging pattern 24'00----0-0-----0---101110 and 24'00----0-0-----0---101100 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------101110 and 24'1-----------------101100 from group (2 3 16'0000010000000010).
  Merging pattern 24'00----0-0-----0---111110 and 24'00----0-0-----0---111100 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------111110 and 24'1-----------------111100 from group (2 3 16'0000010000000010).
  Merging pattern 24'00----0-0-----0---1110-0 and 24'00----0-0-----0---1111-0 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------1110-0 and 24'1-----------------1111-0 from group (2 3 16'0000010000000010).
  Merging pattern 24'00----0-0-----0---1111-0 and 24'00----0-0-----0---1110-0 from group (2 3 16'0000010000000010).
  Merging pattern 24'1-----------------1111-0 and 24'1-----------------1110-0 from group (2 3 16'0000010000000010).
  Merging pattern 24'00------1-----0---111000 and 24'00------1-----0---111010 from group (2 4 16'0000000100000010).
  Merging pattern 24'00------1-----0---101100 and 24'00------1-----0---101110 from group (2 4 16'0000000100000010).
  Merging pattern 24'00------1-----0---111100 and 24'00------1-----0---111110 from group (2 4 16'0000000100000010).
  Merging pattern 24'00------1-----0---111010 and 24'00------1-----0---111000 from group (2 4 16'0000000100000010).
  Merging pattern 24'00------1-----0---101110 and 24'00------1-----0---101100 from group (2 4 16'0000000100000010).
  Merging pattern 24'00------1-----0---111110 and 24'00------1-----0---111100 from group (2 4 16'0000000100000010).
  Merging pattern 24'00------1-----0---1110-0 and 24'00------1-----0---1111-0 from group (2 4 16'0000000100000010).
  Merging pattern 24'00------1-----0---1111-0 and 24'00------1-----0---1110-0 from group (2 4 16'0000000100000010).
  Merging pattern 24'--------------1---111000 and 24'--------------1---111010 from group (2 5 16'0000000010000010).
  Merging pattern 24'--------------1---101100 and 24'--------------1---101110 from group (2 5 16'0000000010000010).
  Merging pattern 24'--------------1---111100 and 24'--------------1---111110 from group (2 5 16'0000000010000010).
  Merging pattern 24'--------------1---111010 and 24'--------------1---111000 from group (2 5 16'0000000010000010).
  Merging pattern 24'--------------1---101110 and 24'--------------1---101100 from group (2 5 16'0000000010000010).
  Merging pattern 24'--------------1---111110 and 24'--------------1---111100 from group (2 5 16'0000000010000010).
  Merging pattern 24'--------------1---1110-0 and 24'--------------1---1111-0 from group (2 5 16'0000000010000010).
  Merging pattern 24'--------------1---1111-0 and 24'--------------1---1110-0 from group (2 5 16'0000000010000010).
  Merging pattern 24'---------0--------111000 and 24'---------0--------111010 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------111000 and 24'----1----1--------111010 from group (3 1 16'0010000000001000).
  Merging pattern 24'---------0--------101100 and 24'---------0--------101110 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------101100 and 24'----1----1--------101110 from group (3 1 16'0010000000001000).
  Merging pattern 24'---------0--------111100 and 24'---------0--------111110 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------111100 and 24'----1----1--------111110 from group (3 1 16'0010000000001000).
  Merging pattern 24'---------0--------111010 and 24'---------0--------111000 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------111010 and 24'----1----1--------111000 from group (3 1 16'0010000000001000).
  Merging pattern 24'---------0--------101110 and 24'---------0--------101100 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------101110 and 24'----1----1--------101100 from group (3 1 16'0010000000001000).
  Merging pattern 24'---------0--------111110 and 24'---------0--------111100 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------111110 and 24'----1----1--------111100 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------111001 and 24'------------------111011 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------101101 and 24'------------------101111 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------111101 and 24'------------------111111 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------111011 and 24'------------------111001 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------101111 and 24'------------------101101 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------111111 and 24'------------------111101 from group (3 1 16'0010000000001000).
  Merging pattern 24'---------0--------1110-0 and 24'---------0--------1111-0 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------1110-0 and 24'----1----1--------1111-0 from group (3 1 16'0010000000001000).
  Merging pattern 24'---------0--------1111-0 and 24'---------0--------1110-0 from group (3 1 16'0010000000001000).
  Merging pattern 24'----1----1--------1111-0 and 24'----1----1--------1110-0 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (3 1 16'0010000000001000).
  Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (3 1 16'0010000000001000).
  Merging pattern 24'----0----1--------111000 and 24'----0----1--------111010 from group (3 3 16'0000010000001000).
  Merging pattern 24'----0----1--------101100 and 24'----0----1--------101110 from group (3 3 16'0000010000001000).
  Merging pattern 24'----0----1--------111100 and 24'----0----1--------111110 from group (3 3 16'0000010000001000).
  Merging pattern 24'----0----1--------111010 and 24'----0----1--------111000 from group (3 3 16'0000010000001000).
  Merging pattern 24'----0----1--------101110 and 24'----0----1--------101100 from group (3 3 16'0000010000001000).
  Merging pattern 24'----0----1--------111110 and 24'----0----1--------111100 from group (3 3 16'0000010000001000).
  Merging pattern 24'----0----1--------1110-0 and 24'----0----1--------1111-0 from group (3 3 16'0000010000001000).
  Merging pattern 24'----0----1--------1111-0 and 24'----0----1--------1110-0 from group (3 3 16'0000010000001000).
  Merging pattern 24'----------------11111000 and 24'----------------11111010 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------11101100 and 24'----------------11101110 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------11111100 and 24'----------------11111110 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------11111010 and 24'----------------11111000 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------11101110 and 24'----------------11101100 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------11111110 and 24'----------------11111100 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------111001 and 24'------------------111011 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------101101 and 24'------------------101111 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------111101 and 24'------------------111111 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------111011 and 24'------------------111001 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------101111 and 24'------------------101101 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------111111 and 24'------------------111101 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------111110-0 and 24'----------------111111-0 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------111111-0 and 24'----------------111110-0 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (4 1 16'0010000000100000).
  Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (4 1 16'0010000000100000).
  Merging pattern 24'----------------10111000 and 24'----------------10111010 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-111000 and 24'----------------0-111010 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------10101100 and 24'----------------10101110 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-101100 and 24'----------------0-101110 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------10111100 and 24'----------------10111110 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-111100 and 24'----------------0-111110 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------10111010 and 24'----------------10111000 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-111010 and 24'----------------0-111000 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------10101110 and 24'----------------10101100 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-101110 and 24'----------------0-101100 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------10111110 and 24'----------------10111100 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-111110 and 24'----------------0-111100 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------101110-0 and 24'----------------101111-0 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-1110-0 and 24'----------------0-1111-0 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------101111-0 and 24'----------------101110-0 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------0-1111-0 and 24'----------------0-1110-0 from group (4 4 16'0000000100100000).
  Merging pattern 24'----------------11111000 and 24'----------------11111010 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------11101100 and 24'----------------11101110 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------11111100 and 24'----------------11111110 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------11111010 and 24'----------------11111000 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------11101110 and 24'----------------11101100 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------11111110 and 24'----------------11111100 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------111001 and 24'------------------111011 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------101101 and 24'------------------101111 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------111101 and 24'------------------111111 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------111011 and 24'------------------111001 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------101111 and 24'------------------101101 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------111111 and 24'------------------111101 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------111110-0 and 24'----------------111111-0 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------111111-0 and 24'----------------111110-0 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------1110-1 and 24'------------------1111-1 from group (5 1 16'0010000001000000).
  Merging pattern 24'------------------1111-1 and 24'------------------1110-1 from group (5 1 16'0010000001000000).
  Merging pattern 24'----------------10111000 and 24'----------------10111010 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-111000 and 24'----------------0-111010 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------10101100 and 24'----------------10101110 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-101100 and 24'----------------0-101110 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------10111100 and 24'----------------10111110 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-111100 and 24'----------------0-111110 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------10111010 and 24'----------------10111000 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-111010 and 24'----------------0-111000 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------10101110 and 24'----------------10101100 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-101110 and 24'----------------0-101100 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------10111110 and 24'----------------10111100 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-111110 and 24'----------------0-111100 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------101110-0 and 24'----------------101111-0 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-1110-0 and 24'----------------0-1111-0 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------101111-0 and 24'----------------101110-0 from group (5 5 16'0000000011000000).
  Merging pattern 24'----------------0-1111-0 and 24'----------------0-1110-0 from group (5 5 16'0000000011000000).
  Removing unused input signal $auto$opt_reduce.cc:134:opt_mux$15184.
  Removing unused input signal $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1826$7475_Y.
Optimizing FSM `$fsm$\housekeeping.U1.state$15197' from module `\mgmt_core'.

13.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 117 unused cells and 117 unused wires.
<suppressed ~118 debug messages>

13.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\housekeeping.U1.state$15197' from module `\mgmt_core'.
  Removing unused output signal $flatten\housekeeping.\U1.$0\state[2:0] [0].
  Removing unused output signal $flatten\housekeeping.\U1.$0\state[2:0] [1].
  Removing unused output signal $flatten\housekeeping.\U1.$0\state[2:0] [2].
Optimizing FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `\mgmt_core'.
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [0].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [1].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [2].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [3].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [4].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [5].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [6].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\cpu_state[7:0] [7].
Optimizing FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `\mgmt_core'.
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0] [0].
  Removing unused output signal $flatten\soc.\cpu.\picorv32_core.$0\mem_wordsize[1:0] [1].
Optimizing FSM `$fsm$\soc.cpu.state$15219' from module `\mgmt_core'.
  Removing unused output signal $flatten\soc.\cpu.$0\state[1:0] [0].
  Removing unused output signal $flatten\soc.\cpu.$0\state[1:0] [1].
Optimizing FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `\mgmt_core'.
  Removing unused output signal $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0] [0].
  Removing unused output signal $flatten\soc.\simple_spi_master_inst.\spi_master.$0\state[1:0] [1].
Optimizing FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `\mgmt_core'.
  Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [0].
  Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [1].
  Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [2].
  Removing unused output signal $flatten\soc.\spimemio.\spimemio.$0\state[3:0] [3].

13.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\housekeeping.U1.state$15197' from module `\mgmt_core' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ----1
  100 -> ---1-
  010 -> --1--
  001 -> -1---
  101 -> 1----
Recoding FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `\mgmt_core' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  10000000 -> -----1
  01000000 -> ----1-
  00100000 -> ---1--
  00001000 -> --1---
  00000010 -> -1----
  00000001 -> 1-----
Recoding FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `\mgmt_core' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> --1
  10 -> -1-
  01 -> 1--
Recoding FSM `$fsm$\soc.cpu.state$15219' from module `\mgmt_core' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> --1
  10 -> -1-
  01 -> 1--
Recoding FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `\mgmt_core' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> ---1
  10 -> --1-
  01 -> -1--
  11 -> 1---
Recoding FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `\mgmt_core' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  0000 -> ------------1
  1000 -> -----------1-
  0100 -> ----------1--
  1100 -> ---------1---
  0010 -> --------1----
  1010 -> -------1-----
  0110 -> ------1------
  0001 -> -----1-------
  1001 -> ----1--------
  0101 -> ---1---------
  0011 -> --1----------
  1011 -> -1-----------
  0111 -> 1------------

13.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\housekeeping.U1.state$15197' from module `mgmt_core':
-------------------------------------

  Information on FSM $fsm$\housekeeping.U1.state$15197 (\housekeeping.U1.state):

  Number of input signals:    9
  Number of output signals:   5
  Number of state bits:       5

  Input signals:
    0: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:429$3019_Y
    1: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:427$3018_Y
    2: $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017_Y
    3: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:423$3016_Y
    4: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:382$3006_Y
    5: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:369$3005_Y
    6: \housekeeping.U1.pre_pass_thru_user
    7: \housekeeping.U1.pre_pass_thru_mgmt
    8: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:459$3030_Y

  Output signals:
    0: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:418$3013_Y
    1: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3009_Y
    2: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:389$3008_Y
    3: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:366$3003_Y
    4: $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:350$2997_Y

  State encoding:
    0:    5'----1  <RESET STATE>
    1:    5'---1-
    2:    5'--1--
    3:    5'-1---
    4:    5'1----

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 9'---000000   ->     0 5'00001
      1:     0 9'---0-0001   ->     0 5'00001
      2:     0 9'---0-001-   ->     0 5'00001
      3:     0 9'---0-01--   ->     0 5'00001
      4:     0 9'---0-1---   ->     0 5'00001
      5:     0 9'---1-----   ->     0 5'00001
      6:     0 9'-01010000   ->     1 5'00001
      7:     0 9'-00010000   ->     3 5'00001
      8:     0 9'-1-010000   ->     4 5'00001
      9:     1 9'---------   ->     1 5'00010
     10:     2 9'1---1----   ->     0 5'01000
     11:     2 9'----0----   ->     2 5'01000
     12:     2 9'0---1----   ->     2 5'01000
     13:     3 9'----1----   ->     2 5'10000
     14:     3 9'----0----   ->     3 5'10000
     15:     4 9'---------   ->     4 5'00100

-------------------------------------

FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `mgmt_core':
-------------------------------------

  Information on FSM $fsm$\soc.cpu.picorv32_core.cpu_state$15204 (\soc.cpu.picorv32_core.cpu_state):

  Number of input signals:   22
  Number of output signals:   8
  Number of state bits:       6

  Input signals:
    0: \soc.cpu.wb_rst_i
    1: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1933$7529_Y
    2: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7522_Y
    3: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1920$7519_Y
    4: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7515_Y
    5: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1917$7512_Y
    6: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1867$7497_Y
    7: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y
    8: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y
    9: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1603$7433_Y
   10: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1600$7429_Y
   11: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1543$7416_Y
   12: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1533$7408_Y
   13: \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu
   14: \soc.cpu.picorv32_core.is_sb_sh_sw
   15: \soc.cpu.picorv32_core.decoder_trigger
   16: \soc.cpu.picorv32_core.instr_trap
   17: \soc.cpu.picorv32_core.instr_jal
   18: \soc.cpu.picorv32_core.mem_done
   19: \soc.cpu.picorv32_core.pcpi_int_ready
   20: $auto$opt_reduce.cc:134:opt_mux$15126
   21: $auto$opt_reduce.cc:134:opt_mux$15128

  Output signals:
    0: $flatten\soc.\cpu.\picorv32_core.$procmux$7616_CMP
    1: $flatten\soc.\cpu.\picorv32_core.$procmux$7614_CMP
    2: $flatten\soc.\cpu.\picorv32_core.$procmux$7613_CMP
    3: $flatten\soc.\cpu.\picorv32_core.$procmux$7612_CMP
    4: $flatten\soc.\cpu.\picorv32_core.$procmux$7611_CMP
    5: $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP
    6: $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP
    7: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y

  State encoding:
    0:   6'-----1
    1:   6'----1-
    2:   6'---1--
    3:   6'--1---
    4:   6'-1----
    5:   6'1-----

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 22'----------------10-000   ->     0 8'00000001
      1:     0 22'----------------0---00   ->     0 8'00000001
      2:     0 22'----------------101010   ->     0 8'00000001
      3:     0 22'----------------0-1-10   ->     0 8'00000001
      4:     0 22'----------------1011-0   ->     0 8'00000001
      5:     0 22'----------------111--0   ->     0 8'00000001
      6:     0 22'----------------11000-   ->     0 8'00000001
      7:     0 22'----------------1-010-   ->     0 8'00000001
      8:     0 22'------------------0-1-   ->     0 8'00000001
      9:     0 22'----------------10-001   ->     1 8'00000001
     10:     0 22'----------------0---01   ->     1 8'00000001
     11:     0 22'----------------101011   ->     1 8'00000001
     12:     0 22'----------------0-1-11   ->     1 8'00000001
     13:     0 22'----------------1011-1   ->     1 8'00000001
     14:     0 22'----------------111--1   ->     1 8'00000001
     15:     1 22'----------------11000-   ->     0 8'10000000
     16:     1 22'----------------1-010-   ->     0 8'10000000
     17:     1 22'------------------0-1-   ->     0 8'10000000
     18:     1 22'------0--00-----10-000   ->     1 8'10000000
     19:     1 22'----1-1--00-----10-000   ->     1 8'10000000
     20:     1 22'---------01-----10-000   ->     1 8'10000000
     21:     1 22'---------1------10-000   ->     1 8'10000000
     22:     1 22'------0--00-----0---00   ->     1 8'10000000
     23:     1 22'----1-1--00-----0---00   ->     1 8'10000000
     24:     1 22'---------01-----0---00   ->     1 8'10000000
     25:     1 22'---------1------0---00   ->     1 8'10000000
     26:     1 22'------0--00-----101010   ->     1 8'10000000
     27:     1 22'----1-1--00-----101010   ->     1 8'10000000
     28:     1 22'---------01-----101010   ->     1 8'10000000
     29:     1 22'---------1------101010   ->     1 8'10000000
     30:     1 22'------0--00-----0-1-10   ->     1 8'10000000
     31:     1 22'----1-1--00-----0-1-10   ->     1 8'10000000
     32:     1 22'---------01-----0-1-10   ->     1 8'10000000
     33:     1 22'---------1------0-1-10   ->     1 8'10000000
     34:     1 22'------0--00-----1011-0   ->     1 8'10000000
     35:     1 22'----1-1--00-----1011-0   ->     1 8'10000000
     36:     1 22'---------01-----1011-0   ->     1 8'10000000
     37:     1 22'---------1------1011-0   ->     1 8'10000000
     38:     1 22'------0--00-----111--0   ->     1 8'10000000
     39:     1 22'----1-1--00-----111--0   ->     1 8'10000000
     40:     1 22'---------01-----111--0   ->     1 8'10000000
     41:     1 22'---------1------111--0   ->     1 8'10000000
     42:     1 22'----------------10-001   ->     1 8'10000000
     43:     1 22'----------------0---01   ->     1 8'10000000
     44:     1 22'----------------101011   ->     1 8'10000000
     45:     1 22'----------------0-1-11   ->     1 8'10000000
     46:     1 22'----------------1011-1   ->     1 8'10000000
     47:     1 22'----------------111--1   ->     1 8'10000000
     48:     1 22'----0-1--00-----10-000   ->     2 8'10000000
     49:     1 22'----0-1--00-----0---00   ->     2 8'10000000
     50:     1 22'----0-1--00-----101010   ->     2 8'10000000
     51:     1 22'----0-1--00-----0-1-10   ->     2 8'10000000
     52:     1 22'----0-1--00-----1011-0   ->     2 8'10000000
     53:     1 22'----0-1--00-----111--0   ->     2 8'10000000
     54:     2 22'--0--1-----10---10-000   ->     0 8'00000010
     55:     2 22'--0--1-----10---0---00   ->     0 8'00000010
     56:     2 22'--0--1-----10---101010   ->     0 8'00000010
     57:     2 22'--0--1-----10---0-1-10   ->     0 8'00000010
     58:     2 22'--0--1-----10---1011-0   ->     0 8'00000010
     59:     2 22'--0--1-----10---111--0   ->     0 8'00000010
     60:     2 22'----------------11000-   ->     0 8'00000010
     61:     2 22'----------------1-010-   ->     0 8'00000010
     62:     2 22'------------------0-1-   ->     0 8'00000010
     63:     2 22'--0--1-----11---10-000   ->     1 8'00000010
     64:     2 22'--1--1----------10-000   ->     1 8'00000010
     65:     2 22'-1--------------10-000   ->     1 8'00000010
     66:     2 22'--0--1-----11---0---00   ->     1 8'00000010
     67:     2 22'--1--1----------0---00   ->     1 8'00000010
     68:     2 22'-1--------------0---00   ->     1 8'00000010
     69:     2 22'--0--1-----11---101010   ->     1 8'00000010
     70:     2 22'--1--1----------101010   ->     1 8'00000010
     71:     2 22'-1--------------101010   ->     1 8'00000010
     72:     2 22'--0--1-----11---0-1-10   ->     1 8'00000010
     73:     2 22'--1--1----------0-1-10   ->     1 8'00000010
     74:     2 22'-1--------------0-1-10   ->     1 8'00000010
     75:     2 22'--0--1-----11---1011-0   ->     1 8'00000010
     76:     2 22'--1--1----------1011-0   ->     1 8'00000010
     77:     2 22'-1--------------1011-0   ->     1 8'00000010
     78:     2 22'--0--1-----11---111--0   ->     1 8'00000010
     79:     2 22'--1--1----------111--0   ->     1 8'00000010
     80:     2 22'-1--------------111--0   ->     1 8'00000010
     81:     2 22'----------------10-001   ->     1 8'00000010
     82:     2 22'----------------0---01   ->     1 8'00000010
     83:     2 22'----------------101011   ->     1 8'00000010
     84:     2 22'----------------0-1-11   ->     1 8'00000010
     85:     2 22'----------------1011-1   ->     1 8'00000010
     86:     2 22'----------------111--1   ->     1 8'00000010
     87:     2 22'--0--1-----0----10-000   ->     2 8'00000010
     88:     2 22'--0--1-----0----0---00   ->     2 8'00000010
     89:     2 22'--0--1-----0----101010   ->     2 8'00000010
     90:     2 22'--0--1-----0----0-1-10   ->     2 8'00000010
     91:     2 22'--0--1-----0----1011-0   ->     2 8'00000010
     92:     2 22'--0--1-----0----111--0   ->     2 8'00000010
     93:     2 22'00---0-0-----0--10-000   ->     3 8'00000010
     94:     2 22'1---------------10-000   ->     3 8'00000010
     95:     2 22'00---0-0-----0--0---00   ->     3 8'00000010
     96:     2 22'1---------------0---00   ->     3 8'00000010
     97:     2 22'00---0-0-----0--101010   ->     3 8'00000010
     98:     2 22'1---------------101010   ->     3 8'00000010
     99:     2 22'00---0-0-----0--0-1-10   ->     3 8'00000010
    100:     2 22'1---------------0-1-10   ->     3 8'00000010
    101:     2 22'00---0-0-----0--1011-0   ->     3 8'00000010
    102:     2 22'1---------------1011-0   ->     3 8'00000010
    103:     2 22'00---0-0-----0--111--0   ->     3 8'00000010
    104:     2 22'1---------------111--0   ->     3 8'00000010
    105:     2 22'00-----1-----0--10-000   ->     4 8'00000010
    106:     2 22'00-----1-----0--0---00   ->     4 8'00000010
    107:     2 22'00-----1-----0--101010   ->     4 8'00000010
    108:     2 22'00-----1-----0--0-1-10   ->     4 8'00000010
    109:     2 22'00-----1-----0--1011-0   ->     4 8'00000010
    110:     2 22'00-----1-----0--111--0   ->     4 8'00000010
    111:     2 22'-------------1--10-000   ->     5 8'00000010
    112:     2 22'-------------1--0---00   ->     5 8'00000010
    113:     2 22'-------------1--101010   ->     5 8'00000010
    114:     2 22'-------------1--0-1-10   ->     5 8'00000010
    115:     2 22'-------------1--1011-0   ->     5 8'00000010
    116:     2 22'-------------1--111--0   ->     5 8'00000010
    117:     3 22'----------------11000-   ->     0 8'00001000
    118:     3 22'----------------1-010-   ->     0 8'00001000
    119:     3 22'------------------0-1-   ->     0 8'00001000
    120:     3 22'--------0-------10-000   ->     1 8'00001000
    121:     3 22'---1----1-------10-000   ->     1 8'00001000
    122:     3 22'--------0-------0---00   ->     1 8'00001000
    123:     3 22'---1----1-------0---00   ->     1 8'00001000
    124:     3 22'--------0-------101010   ->     1 8'00001000
    125:     3 22'---1----1-------101010   ->     1 8'00001000
    126:     3 22'--------0-------0-1-10   ->     1 8'00001000
    127:     3 22'---1----1-------0-1-10   ->     1 8'00001000
    128:     3 22'--------0-------1011-0   ->     1 8'00001000
    129:     3 22'---1----1-------1011-0   ->     1 8'00001000
    130:     3 22'--------0-------111--0   ->     1 8'00001000
    131:     3 22'---1----1-------111--0   ->     1 8'00001000
    132:     3 22'----------------10-001   ->     1 8'00001000
    133:     3 22'----------------0---01   ->     1 8'00001000
    134:     3 22'----------------101011   ->     1 8'00001000
    135:     3 22'----------------0-1-11   ->     1 8'00001000
    136:     3 22'----------------1011-1   ->     1 8'00001000
    137:     3 22'----------------111--1   ->     1 8'00001000
    138:     3 22'---0----1-------10-000   ->     3 8'00001000
    139:     3 22'---0----1-------0---00   ->     3 8'00001000
    140:     3 22'---0----1-------101010   ->     3 8'00001000
    141:     3 22'---0----1-------0-1-10   ->     3 8'00001000
    142:     3 22'---0----1-------1011-0   ->     3 8'00001000
    143:     3 22'---0----1-------111--0   ->     3 8'00001000
    144:     4 22'----------------11000-   ->     0 8'00100000
    145:     4 22'----------------1-010-   ->     0 8'00100000
    146:     4 22'------------------0-1-   ->     0 8'00100000
    147:     4 22'--------------1110-000   ->     1 8'00100000
    148:     4 22'--------------110---00   ->     1 8'00100000
    149:     4 22'--------------11101010   ->     1 8'00100000
    150:     4 22'--------------110-1-10   ->     1 8'00100000
    151:     4 22'--------------111011-0   ->     1 8'00100000
    152:     4 22'--------------11111--0   ->     1 8'00100000
    153:     4 22'----------------10-001   ->     1 8'00100000
    154:     4 22'----------------0---01   ->     1 8'00100000
    155:     4 22'----------------101011   ->     1 8'00100000
    156:     4 22'----------------0-1-11   ->     1 8'00100000
    157:     4 22'----------------1011-1   ->     1 8'00100000
    158:     4 22'----------------111--1   ->     1 8'00100000
    159:     4 22'--------------1010-000   ->     4 8'00100000
    160:     4 22'--------------0-10-000   ->     4 8'00100000
    161:     4 22'--------------100---00   ->     4 8'00100000
    162:     4 22'--------------0-0---00   ->     4 8'00100000
    163:     4 22'--------------10101010   ->     4 8'00100000
    164:     4 22'--------------0-101010   ->     4 8'00100000
    165:     4 22'--------------100-1-10   ->     4 8'00100000
    166:     4 22'--------------0-0-1-10   ->     4 8'00100000
    167:     4 22'--------------101011-0   ->     4 8'00100000
    168:     4 22'--------------0-1011-0   ->     4 8'00100000
    169:     4 22'--------------10111--0   ->     4 8'00100000
    170:     4 22'--------------0-111--0   ->     4 8'00100000
    171:     5 22'----------------11000-   ->     0 8'01000000
    172:     5 22'----------------1-010-   ->     0 8'01000000
    173:     5 22'------------------0-1-   ->     0 8'01000000
    174:     5 22'--------------1110-000   ->     1 8'01000000
    175:     5 22'--------------110---00   ->     1 8'01000000
    176:     5 22'--------------11101010   ->     1 8'01000000
    177:     5 22'--------------110-1-10   ->     1 8'01000000
    178:     5 22'--------------111011-0   ->     1 8'01000000
    179:     5 22'--------------11111--0   ->     1 8'01000000
    180:     5 22'----------------10-001   ->     1 8'01000000
    181:     5 22'----------------0---01   ->     1 8'01000000
    182:     5 22'----------------101011   ->     1 8'01000000
    183:     5 22'----------------0-1-11   ->     1 8'01000000
    184:     5 22'----------------1011-1   ->     1 8'01000000
    185:     5 22'----------------111--1   ->     1 8'01000000
    186:     5 22'--------------1010-000   ->     5 8'01000000
    187:     5 22'--------------0-10-000   ->     5 8'01000000
    188:     5 22'--------------100---00   ->     5 8'01000000
    189:     5 22'--------------0-0---00   ->     5 8'01000000
    190:     5 22'--------------10101010   ->     5 8'01000000
    191:     5 22'--------------0-101010   ->     5 8'01000000
    192:     5 22'--------------100-1-10   ->     5 8'01000000
    193:     5 22'--------------0-0-1-10   ->     5 8'01000000
    194:     5 22'--------------101011-0   ->     5 8'01000000
    195:     5 22'--------------0-1011-0   ->     5 8'01000000
    196:     5 22'--------------10111--0   ->     5 8'01000000
    197:     5 22'--------------0-111--0   ->     5 8'01000000

-------------------------------------

FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `mgmt_core':
-------------------------------------

  Information on FSM $fsm$\soc.cpu.picorv32_core.mem_wordsize$15214 (\soc.cpu.picorv32_core.mem_wordsize):

  Number of input signals:   13
  Number of output signals:   3
  Number of state bits:       3

  Input signals:
    0: \soc.cpu.wb_rst_i
    1: $flatten\soc.\cpu.\picorv32_core.$procmux$7610_CMP
    2: $flatten\soc.\cpu.\picorv32_core.$procmux$7609_CMP
    3: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1882$7502_Y
    4: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1881$7501_Y
    5: $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1852$7493_Y
    6: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1308$7334_Y
    7: \soc.cpu.picorv32_core.instr_sw
    8: \soc.cpu.picorv32_core.instr_sh
    9: \soc.cpu.picorv32_core.instr_sb
   10: \soc.cpu.picorv32_core.instr_lw
   11: \soc.cpu.picorv32_core.mem_do_wdata
   12: \soc.cpu.picorv32_core.mem_do_rdata

  Output signals:
    0: $flatten\soc.\cpu.\picorv32_core.$procmux$10355_CMP
    1: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1925$7520_Y
    2: $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1918$7513_Y

  State encoding:
    0:      3'--1
    1:      3'-1-
    2:      3'1--

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 13'------0---000   ->     0 3'100
      1:     0 13'-------0---10   ->     0 3'100
      2:     0 13'-0---1-1---10   ->     0 3'100
      3:     0 13'-1-----1---10   ->     0 3'100
      4:     0 13'-------0--1-0   ->     0 3'100
      5:     0 13'0-1----1--1-0   ->     0 3'100
      6:     0 13'1------1--1-0   ->     0 3'100
      7:     0 13'------1-----0   ->     0 3'100
      8:     0 13'------------1   ->     0 3'100
      9:     0 13'-0-1---1---10   ->     1 3'100
     10:     0 13'0------11-1-0   ->     1 3'100
     11:     0 13'-0--1--1---10   ->     2 3'100
     12:     0 13'0------1-11-0   ->     2 3'100
     13:     1 13'-0---1-1---10   ->     0 3'001
     14:     1 13'0-1----1--1-0   ->     0 3'001
     15:     1 13'------1-----0   ->     0 3'001
     16:     1 13'------0---000   ->     1 3'001
     17:     1 13'-------0---10   ->     1 3'001
     18:     1 13'-0-1---1---10   ->     1 3'001
     19:     1 13'-1-----1---10   ->     1 3'001
     20:     1 13'0------11-1-0   ->     1 3'001
     21:     1 13'-------0--1-0   ->     1 3'001
     22:     1 13'1------1--1-0   ->     1 3'001
     23:     1 13'------------1   ->     1 3'001
     24:     1 13'-0--1--1---10   ->     2 3'001
     25:     1 13'0------1-11-0   ->     2 3'001
     26:     2 13'-0---1-1---10   ->     0 3'010
     27:     2 13'0-1----1--1-0   ->     0 3'010
     28:     2 13'------1-----0   ->     0 3'010
     29:     2 13'-0-1---1---10   ->     1 3'010
     30:     2 13'0------11-1-0   ->     1 3'010
     31:     2 13'------0---000   ->     2 3'010
     32:     2 13'-------0---10   ->     2 3'010
     33:     2 13'-0--1--1---10   ->     2 3'010
     34:     2 13'-1-----1---10   ->     2 3'010
     35:     2 13'0------1-11-0   ->     2 3'010
     36:     2 13'-------0--1-0   ->     2 3'010
     37:     2 13'1------1--1-0   ->     2 3'010
     38:     2 13'------------1   ->     2 3'010

-------------------------------------

FSM `$fsm$\soc.cpu.state$15219' from module `mgmt_core':
-------------------------------------

  Information on FSM $fsm$\soc.cpu.state$15219 (\soc.cpu.state):

  Number of input signals:    3
  Number of output signals:   3
  Number of state bits:       3

  Input signals:
    0: \soc.cpu.wb_rst_i
    1: \soc.cpu.wbm_ack_i
    2: \soc.cpu.picorv32_core.mem_valid

  Output signals:
    0: $flatten\soc.\cpu.$procmux$12350_CMP
    1: $flatten\soc.\cpu.$procmux$12354_CMP
    2: $flatten\soc.\cpu.$procmux$12441_CMP

  State encoding:
    0:      3'--1  <RESET STATE>
    1:      3'-1-
    2:      3'1--

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 3'0-0   ->     0 3'010
      1:     0 3'--1   ->     0 3'010
      2:     0 3'1-0   ->     2 3'010
      3:     1 3'---   ->     0 3'100
      4:     2 3'--1   ->     0 3'001
      5:     2 3'-10   ->     1 3'001
      6:     2 3'-00   ->     2 3'001

-------------------------------------

FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `mgmt_core':
-------------------------------------

  Information on FSM $fsm$\soc.simple_spi_master_inst.spi_master.state$15224 (\soc.simple_spi_master_inst.spi_master.state):

  Number of input signals:    2
  Number of output signals:   4
  Number of state bits:       4

  Input signals:
    0: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:305$1398_Y
    1: \soc.simple_spi_master_inst.spi_master.w_latched

  Output signals:
    0: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:310$1399_Y
    1: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:292$1392_Y
    2: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1376_Y
    3: $flatten\soc.\simple_spi_master_inst.\spi_master.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:249$1375_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'0-   ->     0 4'0010
      1:     0 2'1-   ->     2 4'0010
      2:     1 2'-0   ->     2 4'0100
      3:     1 2'-1   ->     3 4'0100
      4:     2 2'--   ->     1 4'1000
      5:     3 2'--   ->     0 4'0001

-------------------------------------

FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `mgmt_core':
-------------------------------------

  Information on FSM $fsm$\soc.spimemio.spimemio.state$15230 (\soc.spimemio.spimemio.state):

  Number of input signals:    8
  Number of output signals:  13
  Number of state bits:      13

  Input signals:
    0: \soc.spimemio.spimemio.xfer.din_ready
    1: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:512$1234_Y
    2: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:472$1230_Y
    3: $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:373$1216_Y
    4: $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1137_Y
    5: \soc.spimemio.spimemio.config_cont
    6: \soc.spimemio.spimemio.jump
    7: \soc.spimemio.spimemio.dout_valid

  Output signals:
    0: $flatten\soc.\spimemio.\spimemio.$procmux$13779_CMP
    1: $flatten\soc.\spimemio.\spimemio.$procmux$13776_CMP
    2: $flatten\soc.\spimemio.\spimemio.$procmux$13770_CMP
    3: $flatten\soc.\spimemio.\spimemio.$procmux$13765_CMP
    4: $flatten\soc.\spimemio.\spimemio.$procmux$13762_CMP
    5: $flatten\soc.\spimemio.\spimemio.$procmux$13759_CMP
    6: $flatten\soc.\spimemio.\spimemio.$procmux$13756_CMP
    7: $flatten\soc.\spimemio.\spimemio.$procmux$13753_CMP
    8: $flatten\soc.\spimemio.\spimemio.$procmux$13750_CMP
    9: $flatten\soc.\spimemio.\spimemio.$procmux$13747_CMP
   10: $flatten\soc.\spimemio.\spimemio.$procmux$13717_CMP
   11: $flatten\soc.\spimemio.\spimemio.$procmux$13700_CMP
   12: $flatten\soc.\spimemio.\spimemio.$procmux$13697_CMP

  State encoding:
    0: 13'------------1  <RESET STATE>
    1: 13'-----------1-
    2: 13'----------1--
    3: 13'---------1---
    4: 13'--------1----
    5: 13'-------1-----
    6: 13'------1------
    7: 13'-----1-------
    8: 13'----1--------
    9: 13'---1---------
   10: 13'--1----------
   11: 13'-1-----------
   12: 13'1------------

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 8'-0--0--0   ->     0 13'0000000000001
      1:     0 8'----1---   ->     0 13'0000000000001
      2:     0 8'-10-0---   ->     2 13'0000000000001
      3:     0 8'-0--0--1   ->     7 13'0000000000001
      4:     0 8'-11-0---   ->     9 13'0000000000001
      5:     1 8'----1---   ->     0 13'0000000100000
      6:     1 8'-0--0--0   ->     1 13'0000000100000
      7:     1 8'-10-0---   ->     2 13'0000000100000
      8:     1 8'-0--0--1   ->     8 13'0000000100000
      9:     1 8'-11-0---   ->     9 13'0000000100000
     10:     2 8'----1---   ->     0 13'0010000000000
     11:     2 8'-0--0--0   ->     2 13'0010000000000
     12:     2 8'-10-0---   ->     2 13'0010000000000
     13:     2 8'-0--0--1   ->     9 13'0010000000000
     14:     2 8'-11-0---   ->     9 13'0010000000000
     15:     3 8'----1---   ->     0 13'0001000000000
     16:     3 8'-10-0---   ->     2 13'0001000000000
     17:     3 8'-0--0-10   ->     3 13'0001000000000
     18:     3 8'-0--0-0-   ->     3 13'0001000000000
     19:     3 8'-0--0-11   ->     8 13'0001000000000
     20:     3 8'-11-0---   ->     9 13'0001000000000
     21:     4 8'----1---   ->     0 13'0000000000010
     22:     4 8'-10-0---   ->     2 13'0000000000010
     23:     4 8'-0--0--0   ->     4 13'0000000000010
     24:     4 8'-11-0---   ->     9 13'0000000000010
     25:     4 8'-0--0--1   ->    10 13'0000000000010
     26:     5 8'----1---   ->     0 13'0000010000000
     27:     5 8'-10-0---   ->     2 13'0000010000000
     28:     5 8'-0--0--0   ->     5 13'0000010000000
     29:     5 8'-11-0---   ->     9 13'0000010000000
     30:     5 8'-0--0--1   ->    11 13'0000010000000
     31:     6 8'----1---   ->     0 13'0000000001000
     32:     6 8'-10-0---   ->     2 13'0000000001000
     33:     6 8'-0--0--0   ->     6 13'0000000001000
     34:     6 8'-11-0---   ->     9 13'0000000001000
     35:     6 8'-0--0--1   ->    12 13'0000000001000
     36:     7 8'----1---   ->     0 13'0100000000000
     37:     7 8'-10-0---   ->     2 13'0100000000000
     38:     7 8'10--0---   ->     4 13'0100000000000
     39:     7 8'00--0---   ->     7 13'0100000000000
     40:     7 8'-11-0---   ->     9 13'0100000000000
     41:     8 8'----1---   ->     0 13'0000001000000
     42:     8 8'-10-0---   ->     2 13'0000001000000
     43:     8 8'-0--0--1   ->     5 13'0000001000000
     44:     8 8'-0--0--0   ->     8 13'0000001000000
     45:     8 8'-11-0---   ->     9 13'0000001000000
     46:     9 8'----1---   ->     0 13'0000000000100
     47:     9 8'-10-0---   ->     2 13'0000000000100
     48:     9 8'-0-10--1   ->     6 13'0000000000100
     49:     9 8'-0-10--0   ->     9 13'0000000000100
     50:     9 8'-0-00---   ->     9 13'0000000000100
     51:     9 8'-11-0---   ->     9 13'0000000000100
     52:    10 8'----1---   ->     0 13'1000000000000
     53:    10 8'-10-0---   ->     2 13'1000000000000
     54:    10 8'10--0---   ->     2 13'1000000000000
     55:    10 8'-11-0---   ->     9 13'1000000000000
     56:    10 8'00--0---   ->    10 13'1000000000000
     57:    11 8'----1---   ->     0 13'0000100000000
     58:    11 8'-10-0---   ->     2 13'0000100000000
     59:    11 8'-0--0--1   ->     3 13'0000100000000
     60:    11 8'-11-0---   ->     9 13'0000100000000
     61:    11 8'-0--0--0   ->    11 13'0000100000000
     62:    12 8'----1---   ->     0 13'0000000010000
     63:    12 8'-0--01-1   ->     1 13'0000000010000
     64:    12 8'-10-0---   ->     2 13'0000000010000
     65:    12 8'-0--00-1   ->     8 13'0000000010000
     66:    12 8'-11-0---   ->     9 13'0000000010000
     67:    12 8'-0--0--0   ->    12 13'0000000010000

-------------------------------------

13.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\housekeeping.U1.state$15197' from module `\mgmt_core'.
Mapping FSM `$fsm$\soc.cpu.picorv32_core.cpu_state$15204' from module `\mgmt_core'.
Mapping FSM `$fsm$\soc.cpu.picorv32_core.mem_wordsize$15214' from module `\mgmt_core'.
Mapping FSM `$fsm$\soc.cpu.state$15219' from module `\mgmt_core'.
Mapping FSM `$fsm$\soc.simple_spi_master_inst.spi_master.state$15224' from module `\mgmt_core'.
Mapping FSM `$fsm$\soc.spimemio.spimemio.state$15230' from module `\mgmt_core'.

13.9. Executing OPT pass (performing simple optimizations).

13.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~40 debug messages>

13.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
<suppressed ~138 debug messages>
Removed a total of 46 cells.

13.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/7 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8267.
    dead port 4/7 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8267.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8270.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8270.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8280.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8280.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8321.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8321.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8324.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8324.
    dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8326.
    dead port 2/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8326.
    dead port 3/6 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8514.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8530.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8530.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8796.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$8796.
    dead port 1/5 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8798.
    dead port 2/5 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8798.
    dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8808.
    dead port 2/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8808.
    dead port 3/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$8808.
    dead port 1/3 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9005.
    dead port 3/5 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9030.
    dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9039.
    dead port 2/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9039.
    dead port 3/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9039.
    dead port 4/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9039.
    dead port 1/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9044.
    dead port 2/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9044.
    dead port 3/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9044.
    dead port 4/4 on $pmux $flatten\soc.\cpu.\picorv32_core.$procmux$9044.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9048.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9048.
    dead port 1/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9051.
    dead port 2/2 on $mux $flatten\soc.\cpu.\picorv32_core.$procmux$9051.
Removed 36 multiplexer ports.
<suppressed ~586 debug messages>

13.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15119: { \soc.cpu.picorv32_core.cpu_state [5:4] \soc.cpu.picorv32_core.cpu_state [2:0] }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15117: \soc.cpu.picorv32_core.cpu_state [4:0]
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15115: { \soc.cpu.picorv32_core.cpu_state [5] \soc.cpu.picorv32_core.cpu_state [3:0] }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15113: { \soc.cpu.picorv32_core.cpu_state [5:2] \soc.cpu.picorv32_core.cpu_state [0] }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$15111: { \soc.cpu.picorv32_core.cpu_state [5:3] \soc.cpu.picorv32_core.cpu_state [0] }
  Optimizing cells in module \mgmt_core.
Performed a total of 5 changes.

13.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

13.9.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\soc.\wb_bridge.$procdff$14990 ($dff) from module mgmt_core (D = $flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:60$4514_Y, Q = \soc.wb_bridge.wb_ack_read, rval = 2'00).
Adding SRST signal on $flatten\soc.\wb_bridge.$procdff$14989 ($dff) from module mgmt_core (D = $flatten\soc.\wb_bridge.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:59$4510_Y, Q = \soc.wb_bridge.wb_ack_o, rval = 2'00).
Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14819 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11093_Y, Q = \soc.sysctrl.sysctrl.irq_8_inputsrc, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16182 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [1], Q = \soc.sysctrl.sysctrl.irq_8_inputsrc).
Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14818 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11111_Y, Q = \soc.sysctrl.sysctrl.irq_7_inputsrc, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16192 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.sysctrl.sysctrl.irq_7_inputsrc).
Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14817 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11127_Y, Q = \soc.sysctrl.sysctrl.trap_output_dest, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16202 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.sysctrl.sysctrl.trap_output_dest).
Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14816 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11140_Y, Q = \soc.sysctrl.sysctrl.clk2_output_dest, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16210 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [1], Q = \soc.sysctrl.sysctrl.clk2_output_dest).
Adding SRST signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14815 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11153_Y, Q = \soc.sysctrl.sysctrl.clk1_output_dest, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16216 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.sysctrl.sysctrl.clk1_output_dest).
Adding EN signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14814 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11158_Y, Q = \soc.sysctrl.sysctrl.iomem_ready).
Adding EN signal on $flatten\soc.\sysctrl.\sysctrl.$procdff$14813 ($dff) from module mgmt_core (D = $flatten\soc.\sysctrl.\sysctrl.$procmux$11172_Y, Q = \soc.sysctrl.sysctrl.iomem_rdata).
Adding SRST signal on $auto$opt_dff.cc:764:run$16229 ($dffe) from module mgmt_core (D = 28'xxxxxxxxxxxxxxxxxxxxxxxxxxxx, Q = \soc.sysctrl.sysctrl.iomem_rdata [31:4], rval = 28'0000000000000000000000000000).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:702:run$16232 ($sdffce) from module mgmt_core.
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14957 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.fetch, Q = \soc.spimemio.spimemio.xfer.last_fetch, rval = 1'1).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14956 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.next_fetch, Q = \soc.spimemio.spimemio.xfer.fetch, rval = 1'1).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14955 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13333_Y, Q = \soc.spimemio.spimemio.xfer.xfer_tag, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16239 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.din_tag, Q = \soc.spimemio.spimemio.xfer.xfer_tag).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14954 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13338_Y, Q = \soc.spimemio.spimemio.xfer.xfer_rd, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16241 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.din_rd, Q = \soc.spimemio.spimemio.xfer.xfer_rd).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14953 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13343_Y, Q = \soc.spimemio.spimemio.xfer.xfer_qspi, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16243 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.din_qspi, Q = \soc.spimemio.spimemio.xfer.xfer_qspi).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14951 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13356_Y, Q = \soc.spimemio.spimemio.xfer.dummy_count, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16245 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13356_Y, Q = \soc.spimemio.spimemio.xfer.dummy_count).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14950 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13366_Y [3], Q = \soc.spimemio.spimemio.xfer.count [3], rval = 1'0).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14950 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13364_Y [2:0], Q = \soc.spimemio.spimemio.xfer.count [2:0], rval = 3'000).
Adding EN signal on $auto$opt_dff.cc:702:run$16252 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$2\next_count[3:0] [2:0], Q = \soc.spimemio.spimemio.xfer.count [2:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16249 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13366_Y [3], Q = \soc.spimemio.spimemio.xfer.count [3]).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14949 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$2\next_ibuffer[7:0], Q = \soc.spimemio.spimemio.xfer.ibuffer).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14948 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13384_Y, Q = \soc.spimemio.spimemio.xfer.obuffer).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14947 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13389_Y, Q = \soc.spimemio.spimemio.xfer.xfer_ddr, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16305 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.din_ddr, Q = \soc.spimemio.spimemio.xfer.xfer_ddr).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14946 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13394_Y, Q = \soc.spimemio.spimemio.xfer.xfer_dspi, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16307 ($sdff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.din_dspi, Q = \soc.spimemio.spimemio.xfer.xfer_dspi).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14945 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13402_Y, Q = \soc.spimemio.spimemio.xfer.flash_clk, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16311 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13402_Y, Q = \soc.spimemio.spimemio.xfer.flash_clk).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14944 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13409_Y, Q = \soc.spimemio.spimemio.xfer.flash_csb, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$16315 ($sdff) from module mgmt_core (D = 1'0, Q = \soc.spimemio.spimemio.xfer.flash_csb).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14988 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13941_Y, Q = \soc.spimemio.spimemio.config_do, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16317 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [3:0], Q = \soc.spimemio.spimemio.config_do).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14987 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13946_Y, Q = \soc.spimemio.spimemio.config_clk, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16319 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [4], Q = \soc.spimemio.spimemio.config_clk).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14986 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13951_Y, Q = \soc.spimemio.spimemio.config_csb, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16321 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [5], Q = \soc.spimemio.spimemio.config_csb).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14985 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13956_Y, Q = \soc.spimemio.spimemio.config_oe, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16323 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [11:8], Q = \soc.spimemio.spimemio.config_oe).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14984 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13961_Y, Q = \soc.spimemio.spimemio.config_dummy, rval = 4'1000).
Adding EN signal on $auto$opt_dff.cc:702:run$16325 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [19:16], Q = \soc.spimemio.spimemio.config_dummy).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14983 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13966_Y, Q = \soc.spimemio.spimemio.config_cont, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16327 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [20], Q = \soc.spimemio.spimemio.config_cont).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14982 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13971_Y, Q = \soc.spimemio.spimemio.config_qspi, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16329 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [21], Q = \soc.spimemio.spimemio.config_qspi).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14981 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13976_Y, Q = \soc.spimemio.spimemio.config_ddr, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16331 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [22], Q = \soc.spimemio.spimemio.config_ddr).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14980 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13981_Y, Q = \soc.spimemio.spimemio.config_en, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$16333 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31], Q = \soc.spimemio.spimemio.config_en).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14979 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:244$1148_Y, Q = \soc.spimemio.spimemio.softreset, rval = 1'1).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14974 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13718_Y, Q = \soc.spimemio.spimemio.rd_inc).
Adding SRST signal on $auto$opt_dff.cc:764:run$16342 ($dffe) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13706_Y, Q = \soc.spimemio.spimemio.rd_inc, rval = 1'0).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14973 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13725_Y, Q = \soc.spimemio.spimemio.rd_wait).
Adding SRST signal on $auto$opt_dff.cc:764:run$16352 ($dffe) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13723_Y, Q = \soc.spimemio.spimemio.rd_wait, rval = 1'0).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14972 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13730_Y, Q = \soc.spimemio.spimemio.rd_valid, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16356 ($sdff) from module mgmt_core (D = 1'1, Q = \soc.spimemio.spimemio.rd_valid).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14971 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:388$1227_Y [23:0], Q = \soc.spimemio.spimemio.rd_addr).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14970 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.ibuffer, Q = \soc.spimemio.spimemio.buffer [23:16]).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14970 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.ibuffer, Q = \soc.spimemio.spimemio.buffer [15:8]).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14970 ($dff) from module mgmt_core (D = \soc.spimemio.spimemio.xfer.ibuffer, Q = \soc.spimemio.spimemio.buffer [7:0]).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14969 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13789_Y, Q = \soc.spimemio.spimemio.din_rd, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16380 ($sdff) from module mgmt_core (D = 1'1, Q = \soc.spimemio.spimemio.din_rd).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14968 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13810_Y, Q = \soc.spimemio.spimemio.din_ddr, rval = 1'0).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14967 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13829_Y, Q = \soc.spimemio.spimemio.din_qspi, rval = 1'0).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14965 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13839_Y, Q = \soc.spimemio.spimemio.din_tag, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16386 ($sdff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13839_Y, Q = \soc.spimemio.spimemio.din_tag).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14964 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858_Y, Q = \soc.spimemio.spimemio.din_data).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14963 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13746_Y, Q = \soc.spimemio.spimemio.din_valid, rval = 1'0).
Adding SRST signal on $flatten\soc.\spimemio.\spimemio.$procdff$14962 ($dff) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13696_Y, Q = \soc.spimemio.spimemio.xfer_resetn, rval = 1'0).
Adding EN signal on $flatten\soc.\spimemio.\spimemio.$procdff$14961 ($dff) from module mgmt_core (D = { \soc.spimemio.spimemio.xfer.ibuffer \soc.spimemio.spimemio.buffer }, Q = \soc.spimemio.spimemio.rdata).
Adding SRST signal on $flatten\soc.\soc_mem.$procdff$14888 ($dff) from module mgmt_core (D = $flatten\soc.\soc_mem.$and$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:49$2164_Y, Q = \soc.soc_mem.wb_ack_read, rval = 1'0).
Adding SRST signal on $flatten\soc.\soc_mem.$procdff$14887 ($dff) from module mgmt_core (D = $flatten\soc.\soc_mem.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/mem_wb.v:48$2160_Y, Q = \soc.soc_mem.wb_ack_o, rval = 1'0).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14943 ($dff) from module mgmt_core (D = { $flatten\soc.\simpleuart.\simpleuart.$procmux$13302_Y $flatten\soc.\simpleuart.\simpleuart.$procmux$13307_Y $flatten\soc.\simpleuart.\simpleuart.$procmux$13312_Y $flatten\soc.\simpleuart.\simpleuart.$procmux$13317_Y }, Q = \soc.simpleuart.simpleuart.cfg_divider, rval = 1).
Adding EN signal on $auto$opt_dff.cc:702:run$16416 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.simpleuart.simpleuart.cfg_divider [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16416 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.simpleuart.simpleuart.cfg_divider [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$16416 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.simpleuart.simpleuart.cfg_divider [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$16416 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.simpleuart.simpleuart.cfg_divider [31:24]).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14942 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13322_Y, Q = \soc.simpleuart.simpleuart.enabled, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16421 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.simpleuart.simpleuart.enabled).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14941 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13263_Y, Q = \soc.simpleuart.simpleuart.recv_buf_valid, rval = 1'0).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14940 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13271_Y, Q = \soc.simpleuart.simpleuart.recv_buf_data, rval = 8'00000000).
Adding EN signal on $auto$opt_dff.cc:702:run$16424 ($sdff) from module mgmt_core (D = \soc.simpleuart.simpleuart.recv_pattern, Q = \soc.simpleuart.simpleuart.recv_buf_data).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14939 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13279_Y, Q = \soc.simpleuart.simpleuart.recv_pattern, rval = 8'00000000).
Adding EN signal on $auto$opt_dff.cc:702:run$16428 ($sdff) from module mgmt_core (D = { \mgmt_in_data [5] \soc.simpleuart.simpleuart.recv_pattern [7:1] }, Q = \soc.simpleuart.simpleuart.recv_pattern).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14938 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13249_Y, Q = \soc.simpleuart.simpleuart.recv_divcnt, rval = 0).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14937 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13291_Y, Q = \soc.simpleuart.simpleuart.recv_state, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16435 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13291_Y, Q = \soc.simpleuart.simpleuart.recv_state).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14936 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13219_Y, Q = \soc.simpleuart.simpleuart.send_dummy, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$16447 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13219_Y, Q = \soc.simpleuart.simpleuart.send_dummy).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14935 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:197$1328_Y, Q = \soc.simpleuart.simpleuart.send_divcnt, rval = 0).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14934 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13230_Y, Q = \soc.simpleuart.simpleuart.send_bitcnt, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16454 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13230_Y, Q = \soc.simpleuart.simpleuart.send_bitcnt).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14933 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13235_Y [9], Q = \soc.simpleuart.simpleuart.send_pattern [9], rval = 1'1).
Adding SRST signal on $flatten\soc.\simpleuart.\simpleuart.$procdff$14933 ($dff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13238_Y [8:0], Q = \soc.simpleuart.simpleuart.send_pattern [8:0], rval = 9'111111111).
Adding EN signal on $auto$opt_dff.cc:702:run$16463 ($sdff) from module mgmt_core (D = $flatten\soc.\simpleuart.\simpleuart.$procmux$13238_Y [8:0], Q = \soc.simpleuart.simpleuart.send_pattern [8:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16460 ($sdff) from module mgmt_core (D = 1'1, Q = \soc.simpleuart.simpleuart.send_pattern [9]).
Setting constant 1-bit at position 0 on $auto$opt_dff.cc:764:run$16467 ($sdffe) from module mgmt_core.
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14932 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15], Q = \soc.simple_spi_master_inst.spi_master.hkconn).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14931 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [11], Q = \soc.simple_spi_master_inst.spi_master.mode).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14930 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12], Q = \soc.simple_spi_master_inst.spi_master.stream).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14929 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [14], Q = \soc.simple_spi_master_inst.spi_master.irqena).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14928 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [8], Q = \soc.simple_spi_master_inst.spi_master.mlb).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14927 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [9], Q = \soc.simple_spi_master_inst.spi_master.invcsb).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14926 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [10], Q = \soc.simple_spi_master_inst.spi_master.invsck).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14925 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.simple_spi_master_inst.spi_master.prescaler).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14924 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [13], Q = \soc.simple_spi_master_inst.spi_master.enable).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14922 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\w_latched[0:0], Q = \soc.simple_spi_master_inst.spi_master.w_latched).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14921 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.simple_spi_master_inst.spi_master.d_latched).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14919 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\nbit[2:0], Q = \soc.simple_spi_master_inst.spi_master.nbit).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14918 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\icsb[0:0], Q = \soc.simple_spi_master_inst.spi_master.icsb).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14917 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\done[0:0], Q = \soc.simple_spi_master_inst.spi_master.done).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14915 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$not$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:331$1406_Y, Q = \soc.simple_spi_master_inst.spi_master.hsck).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14912 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13041_Y, Q = \soc.simple_spi_master_inst.spi_master.rreg).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14911 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\treg[7:0], Q = \soc.simple_spi_master_inst.spi_master.treg).
Adding EN signal on $flatten\soc.\simple_spi_master_inst.\spi_master.$procdff$14910 ($adff) from module mgmt_core (D = $flatten\soc.\simple_spi_master_inst.\spi_master.$0\isdo[0:0], Q = \soc.simple_spi_master_inst.spi_master.isdo).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14877 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11817_Y, Q = \soc.mprj_ctrl.mprj_ctrl.iomem_ready, rval = 1'0).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14876 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11824_Y, Q = \soc.mprj_ctrl.mprj_ctrl.iomem_rdata, rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$16533 ($sdff) from module mgmt_core (D = \soc.mprj_ctrl.mprj_ctrl.iomem_rdata_pre, Q = \soc.mprj_ctrl.mprj_ctrl.iomem_rdata).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14875 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11797_Y, Q = \soc.mprj_ctrl.mprj_ctrl.xfer_ctrl, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$16541 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.mprj_ctrl.mprj_ctrl.xfer_ctrl).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14874 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11812_Y, Q = \soc.mprj_ctrl.mprj_ctrl.pwr_ctrl_out, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$16545 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [3:0], Q = \soc.mprj_ctrl.mprj_ctrl.pwr_ctrl_out).
Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14871 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11688_Y, Q = \soc.mprj_ctrl.mprj_ctrl.serial_data_staging).
Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14870 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\xfer_state[1:0], Q = \soc.mprj_ctrl.mprj_ctrl.xfer_state).
Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14869 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\pad_count[5:0], Q = \soc.mprj_ctrl.mprj_ctrl.pad_count).
Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14868 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11744_Y, Q = \soc.mprj_ctrl.mprj_ctrl.xfer_count).
Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14867 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\serial_resetn[0:0], Q = \soc.mprj_ctrl.mprj_ctrl.serial_resetn).
Adding EN signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14866 ($adff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$0\serial_clock[0:0], Q = \soc.mprj_ctrl.mprj_ctrl.serial_clock).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14865 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11612_Y, Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [31:0], rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$16607 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o, Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [31:0]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14864 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11603_Y, Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [37:32], rval = 6'000000).
Adding EN signal on $auto$opt_dff.cc:702:run$16611 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [5:0], Q = \soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [37:32]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14863 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11594_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[0], rval = 13'1100000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16615 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[0]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14862 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11585_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[1], rval = 13'1100000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16619 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[1]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14861 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11576_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[2], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16623 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[2]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14860 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11567_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[3], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16627 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[3]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14859 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11558_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[4], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16631 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[4]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14858 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11549_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[5], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16635 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[5]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14857 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11540_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[6], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16639 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[6]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14856 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11531_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[7], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16643 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[7]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14855 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11522_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[8], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16647 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[8]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14854 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11513_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[9], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16651 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[9]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14853 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11504_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[10], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16655 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[10]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14852 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11495_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[11], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16659 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[11]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14851 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11486_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[12], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16663 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[12]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14850 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11477_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[13], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16667 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[13]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14849 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11468_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[14], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16671 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[14]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14848 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11459_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[15], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16675 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[15]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14847 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11450_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[16], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16679 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[16]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14846 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11441_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[17], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16683 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[17]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14845 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11432_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[18], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16687 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[18]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14844 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11423_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[19], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16691 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[19]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14843 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11414_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[20], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16695 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[20]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14842 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11405_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[21], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16699 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[21]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14841 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11396_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[22], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16703 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[22]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14840 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11387_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[23], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16707 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[23]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14839 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11378_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[24], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16711 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[24]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14838 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11369_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[25], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16715 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[25]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14837 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11360_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[26], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16719 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[26]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14836 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11351_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[27], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16723 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[27]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14835 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11342_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[28], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16727 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[28]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14834 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11333_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[29], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16731 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[29]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14833 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11324_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[30], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16735 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[30]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14832 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11315_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[31], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16739 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[31]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14831 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11306_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[32], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16743 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[32]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14830 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11297_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[33], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16747 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[33]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14829 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11288_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[34], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16751 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[34]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14828 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11279_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[35], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16755 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[35]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14827 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11270_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[36], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16759 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[36]).
Adding SRST signal on $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procdff$14826 ($dff) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11261_Y, Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[37], rval = 13'0010000000011).
Adding EN signal on $auto$opt_dff.cc:702:run$16763 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [12:0], Q = \soc.mprj_ctrl.mprj_ctrl.io_ctrl[37]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14812 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10420_Y $flatten\soc.\la.\la_ctrl.$procmux$10450_Y $flatten\soc.\la.\la_ctrl.$procmux$10480_Y $flatten\soc.\la.\la_ctrl.$procmux$10510_Y }, Q = \soc.la.la_ctrl.la_ena_3, rval = 32'11111111111111111111111111111111).
Adding EN signal on $auto$opt_dff.cc:702:run$16767 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_3 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16767 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_3 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$16767 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_3 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$16767 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_3 [31:24]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14811 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$11042_Y $flatten\soc.\la.\la_ctrl.$procmux$10538_Y $flatten\soc.\la.\la_ctrl.$procmux$10566_Y $flatten\soc.\la.\la_ctrl.$procmux$10594_Y }, Q = \soc.la.la_ctrl.la_ena_2, rval = 32'11111111111111111111111111111111).
Adding EN signal on $auto$opt_dff.cc:702:run$16836 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_2 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16836 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_2 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$16836 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_2 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$16836 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_2 [31:24]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14810 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10934_Y $flatten\soc.\la.\la_ctrl.$procmux$10619_Y $flatten\soc.\la.\la_ctrl.$procmux$10644_Y $flatten\soc.\la.\la_ctrl.$procmux$10669_Y }, Q = \soc.la.la_ctrl.la_ena_1, rval = 32'11111111111111111111111111111111).
Adding EN signal on $auto$opt_dff.cc:702:run$16897 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_1 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16897 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_1 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$16897 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_1 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$16897 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_1 [31:24]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14809 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10956_Y $flatten\soc.\la.\la_ctrl.$procmux$10691_Y $flatten\soc.\la.\la_ctrl.$procmux$10713_Y $flatten\soc.\la.\la_ctrl.$procmux$10735_Y }, Q = \soc.la.la_ctrl.la_ena_0, rval = 32'11111111111111111111111111111111).
Adding EN signal on $auto$opt_dff.cc:702:run$16950 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_ena_0 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16950 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_ena_0 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$16950 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_ena_0 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$16950 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_ena_0 [31:24]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14808 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10975_Y $flatten\soc.\la.\la_ctrl.$procmux$10754_Y $flatten\soc.\la.\la_ctrl.$procmux$10773_Y $flatten\soc.\la.\la_ctrl.$procmux$10792_Y }, Q = \soc.la.la_ctrl.la_data_3, rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$16995 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_3 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$16995 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_3 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$16995 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_3 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$16995 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_3 [31:24]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14807 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$10991_Y $flatten\soc.\la.\la_ctrl.$procmux$10808_Y $flatten\soc.\la.\la_ctrl.$procmux$10824_Y $flatten\soc.\la.\la_ctrl.$procmux$10840_Y }, Q = \soc.la.la_ctrl.la_data_2, rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$17032 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_2 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$17032 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_2 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$17032 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_2 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$17032 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_2 [31:24]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14806 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$11004_Y $flatten\soc.\la.\la_ctrl.$procmux$10853_Y $flatten\soc.\la.\la_ctrl.$procmux$10866_Y $flatten\soc.\la.\la_ctrl.$procmux$10879_Y }, Q = \soc.la.la_ctrl.la_data_1, rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$17061 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_1 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$17061 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_1 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$17061 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_1 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$17061 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_1 [31:24]).
Adding SRST signal on $flatten\soc.\la.\la_ctrl.$procdff$14805 ($dff) from module mgmt_core (D = { $flatten\soc.\la.\la_ctrl.$procmux$11014_Y $flatten\soc.\la.\la_ctrl.$procmux$10889_Y $flatten\soc.\la.\la_ctrl.$procmux$10899_Y $flatten\soc.\la.\la_ctrl.$procmux$10909_Y }, Q = \soc.la.la_ctrl.la_data_0, rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$17082 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.la.la_ctrl.la_data_0 [7:0]).
Adding EN signal on $auto$opt_dff.cc:702:run$17082 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.la.la_ctrl.la_data_0 [15:8]).
Adding EN signal on $auto$opt_dff.cc:702:run$17082 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.la.la_ctrl.la_data_0 [23:16]).
Adding EN signal on $auto$opt_dff.cc:702:run$17082 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.la.la_ctrl.la_data_0 [31:24]).
Adding EN signal on $flatten\soc.\la.\la_ctrl.$procdff$14804 ($dff) from module mgmt_core (D = $flatten\soc.\la.\la_ctrl.$procmux$11047_Y, Q = \soc.la.la_ctrl.iomem_ready).
Adding EN signal on $flatten\soc.\la.\la_ctrl.$procdff$14803 ($dff) from module mgmt_core (D = $flatten\soc.\la.\la_ctrl.$procmux$11073_Y, Q = \soc.la.la_ctrl.iomem_rdata).
Adding EN signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14825 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11179_Y, Q = \soc.gpio_wb.gpio_ctrl.iomem_ready).
Adding EN signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14824 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11193_Y, Q = \soc.gpio_wb.gpio_ctrl.iomem_rdata).
Adding SRST signal on $auto$opt_dff.cc:764:run$17110 ($dffe) from module mgmt_core (D = 30'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, Q = \soc.gpio_wb.gpio_ctrl.iomem_rdata [31:2], rval = 30'000000000000000000000000000000).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 24 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 25 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 26 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 27 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 28 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Setting constant 0-bit at position 29 on $auto$opt_dff.cc:702:run$17113 ($sdffce) from module mgmt_core.
Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14823 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11213_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio_pd, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17114 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio_pd).
Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14822 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11229_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio_pu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17124 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio_pu).
Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14821 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11242_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio_oeb, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$17132 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio_oeb).
Adding SRST signal on $flatten\soc.\gpio_wb.\gpio_ctrl.$procdff$14820 ($dff) from module mgmt_core (D = $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11252_Y, Q = \soc.gpio_wb.gpio_ctrl.gpio, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17138 ($sdff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.gpio_wb.gpio_ctrl.gpio).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15022 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14157_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mulhu, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15021 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14162_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mulhsu, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15020 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14168_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mulh, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15019 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14175_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.instr_mul, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15017 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14105_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.mul_finish, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15016 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14116_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.mul_waiting, rval = 1'1).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15015 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14122_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.mul_counter).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15014 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14128_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rdx).
Adding SRST signal on $auto$opt_dff.cc:764:run$17151 ($dffe) from module mgmt_core (D = { \soc.cpu.picorv32_core.pcpi_mul.next_rdx [60] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [56] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [52] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [48] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [44] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [40] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [36] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [32] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [28] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [24] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [20] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [16] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [12] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [8] \soc.cpu.picorv32_core.pcpi_mul.next_rdx [4] }, Q = { \soc.cpu.picorv32_core.pcpi_mul.rdx [60] \soc.cpu.picorv32_core.pcpi_mul.rdx [56] \soc.cpu.picorv32_core.pcpi_mul.rdx [52] \soc.cpu.picorv32_core.pcpi_mul.rdx [48] \soc.cpu.picorv32_core.pcpi_mul.rdx [44] \soc.cpu.picorv32_core.pcpi_mul.rdx [40] \soc.cpu.picorv32_core.pcpi_mul.rdx [36] \soc.cpu.picorv32_core.pcpi_mul.rdx [32] \soc.cpu.picorv32_core.pcpi_mul.rdx [28] \soc.cpu.picorv32_core.pcpi_mul.rdx [24] \soc.cpu.picorv32_core.pcpi_mul.rdx [20] \soc.cpu.picorv32_core.pcpi_mul.rdx [16] \soc.cpu.picorv32_core.pcpi_mul.rdx [12] \soc.cpu.picorv32_core.pcpi_mul.rdx [8] \soc.cpu.picorv32_core.pcpi_mul.rdx [4] }, rval = 15'000000000000000).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15013 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14134_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rd).
Adding SRST signal on $auto$opt_dff.cc:764:run$17153 ($dffe) from module mgmt_core (D = \soc.cpu.picorv32_core.pcpi_mul.next_rd, Q = \soc.cpu.picorv32_core.pcpi_mul.rd, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15012 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14143_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rs2).
Adding SRST signal on $auto$opt_dff.cc:764:run$17155 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [0], Q = \soc.cpu.picorv32_core.pcpi_mul.rs2 [0], rval = 1'0).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15011 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14152_Y, Q = \soc.cpu.picorv32_core.pcpi_mul.rs1).
Adding SRST signal on $auto$opt_dff.cc:764:run$17157 ($dffe) from module mgmt_core (D = \soc.cpu.picorv32_core.reg_op1 [31], Q = \soc.cpu.picorv32_core.pcpi_mul.rs1 [63], rval = 1'0).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procdff$15009 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2308$1031_Y [31:0], Q = \soc.cpu.picorv32_core.pcpi_mul.pcpi_rd).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$15005 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14077_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_remu, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$15004 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14082_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_rem, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$15003 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14088_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_divu, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$15002 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14095_Y, Q = \soc.cpu.picorv32_core.pcpi_div.instr_div, rval = 1'0).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14999 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2471$1084_Y, Q = \soc.cpu.picorv32_core.pcpi_div.outsign).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14998 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14032_Y, Q = \soc.cpu.picorv32_core.pcpi_div.running, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17171 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14032_Y, Q = \soc.cpu.picorv32_core.pcpi_div.running).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14997 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14041_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient_msk).
Adding SRST signal on $auto$opt_dff.cc:764:run$17181 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14038_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient_msk, rval = 32'10000000000000000000000000000000).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14996 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14052_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient).
Adding SRST signal on $auto$opt_dff.cc:764:run$17191 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14049_Y, Q = \soc.cpu.picorv32_core.pcpi_div.quotient, rval = 0).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14995 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14061_Y, Q = \soc.cpu.picorv32_core.pcpi_div.divisor).
Adding SRST signal on $auto$opt_dff.cc:764:run$17199 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14058_Y [30:0], Q = \soc.cpu.picorv32_core.pcpi_div.divisor [30:0], rval = 31'0000000000000000000000000000000).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14994 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14072_Y, Q = \soc.cpu.picorv32_core.pcpi_div.dividend).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procdff$14991 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14005_Y, Q = \soc.cpu.picorv32_core.pcpi_div.pcpi_wr, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14802 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:397$6960_Y, Q = \soc.cpu.picorv32_core.last_mem_valid, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14801 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10381_Y, Q = \soc.cpu.picorv32_core.mem_la_firstword_reg, rval = 1'0).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14800 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_rdata_latched [6:0], Q = \soc.cpu.picorv32_core.mem_rdata_q [6:0]).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14798 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10013_Y, Q = \soc.cpu.picorv32_core.mem_16bit_buffer).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14797 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10034_Y, Q = \soc.cpu.picorv32_core.prefetched_high_word, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17229 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10025_Y, Q = \soc.cpu.picorv32_core.prefetched_high_word).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14796 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10048_Y, Q = \soc.cpu.picorv32_core.mem_la_secondword, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17237 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10044_Y, Q = \soc.cpu.picorv32_core.mem_la_secondword).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14795 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$0\mem_state[1:0], Q = \soc.cpu.picorv32_core.mem_state).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14794 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10083_Y, Q = \soc.cpu.picorv32_core.mem_wstrb).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14793 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_la_wdata, Q = \soc.cpu.picorv32_core.mem_wdata).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14792 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_la_addr, Q = \soc.cpu.picorv32_core.mem_addr).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14790 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$0\mem_valid[0:0], Q = \soc.cpu.picorv32_core.mem_valid).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14774 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:862$7039_Y, Q = \soc.cpu.picorv32_core.is_compare, rval = 1'0).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14773 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9416_Y, Q = \soc.cpu.picorv32_core.is_alu_reg_reg).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14772 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9452_Y, Q = \soc.cpu.picorv32_core.is_alu_reg_imm).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14770 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9464_Y, Q = \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17287 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9462_Y, Q = \soc.cpu.picorv32_core.is_beq_bne_blt_bge_bltu_bgeu).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14767 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:858$7035_Y, Q = \soc.cpu.picorv32_core.is_lui_auipc_jal_jalr_addi_add_sub, rval = 1'0).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14765 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9477_Y, Q = \soc.cpu.picorv32_core.is_sb_sh_sw).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14764 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1098$7277_Y, Q = \soc.cpu.picorv32_core.is_jalr_addi_slti_sltiu_xori_ori_andi).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14763 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1092$7268_Y, Q = \soc.cpu.picorv32_core.is_slli_srli_srai).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14762 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9497_Y, Q = \soc.cpu.picorv32_core.is_lb_lh_lw_lbu_lhu).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14760 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9501_Y, Q = \soc.cpu.picorv32_core.compressed_instr).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14759 ($dff) from module mgmt_core (D = { $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9547_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9342_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9310_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9330_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9314_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9318_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9326_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9338_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9322_Y 1'0 }, Q = \soc.cpu.picorv32_core.decoded_imm_j).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$17295 ($dffe) from module mgmt_core.
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14758 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510_Y, Q = \soc.cpu.picorv32_core.decoded_imm).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14757 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9543_Y, Q = \soc.cpu.picorv32_core.decoded_rs2).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14756 ($dff) from module mgmt_core (D = { $flatten\soc.\cpu.\picorv32_core.$procmux$9306_Y $flatten\soc.\cpu.\picorv32_core.$procmux$9393_Y }, Q = \soc.cpu.picorv32_core.decoded_rs1).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14755 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9594_Y, Q = \soc.cpu.picorv32_core.decoded_rd).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14754 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1090$7255_Y, Q = \soc.cpu.picorv32_core.instr_timer).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14753 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:870$7053_Y, Q = \soc.cpu.picorv32_core.instr_waitirq).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14752 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1089$7251_Y, Q = \soc.cpu.picorv32_core.instr_maskirq).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14751 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:869$7049_Y, Q = \soc.cpu.picorv32_core.instr_retirq).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14750 ($dff) from module mgmt_core (D = 1'0, Q = \soc.cpu.picorv32_core.instr_setq).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$17304 ($dffe) from module mgmt_core.
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14749 ($dff) from module mgmt_core (D = 1'0, Q = \soc.cpu.picorv32_core.instr_getq).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$17305 ($dffe) from module mgmt_core.
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14748 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1084$7238_Y, Q = \soc.cpu.picorv32_core.instr_ecall_ebreak).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14747 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1082$7228_Y, Q = \soc.cpu.picorv32_core.instr_rdinstrh).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14746 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1081$7224_Y, Q = \soc.cpu.picorv32_core.instr_rdinstr).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14745 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1079$7220_Y, Q = \soc.cpu.picorv32_core.instr_rdcycleh).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14744 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1077$7212_Y, Q = \soc.cpu.picorv32_core.instr_rdcycle).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14743 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9620_Y, Q = \soc.cpu.picorv32_core.instr_and, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17311 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1075$7204_Y, Q = \soc.cpu.picorv32_core.instr_and).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14742 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9624_Y, Q = \soc.cpu.picorv32_core.instr_or, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17313 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1074$7200_Y, Q = \soc.cpu.picorv32_core.instr_or).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14741 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9628_Y, Q = \soc.cpu.picorv32_core.instr_sra, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17315 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1073$7196_Y, Q = \soc.cpu.picorv32_core.instr_sra).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14740 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9632_Y, Q = \soc.cpu.picorv32_core.instr_srl, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17317 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1072$7192_Y, Q = \soc.cpu.picorv32_core.instr_srl).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14739 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9636_Y, Q = \soc.cpu.picorv32_core.instr_xor, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17319 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1071$7188_Y, Q = \soc.cpu.picorv32_core.instr_xor).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14738 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9640_Y, Q = \soc.cpu.picorv32_core.instr_sltu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17321 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1070$7184_Y, Q = \soc.cpu.picorv32_core.instr_sltu).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14737 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9644_Y, Q = \soc.cpu.picorv32_core.instr_slt, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17323 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1069$7180_Y, Q = \soc.cpu.picorv32_core.instr_slt).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14736 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9648_Y, Q = \soc.cpu.picorv32_core.instr_sll, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17325 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1068$7176_Y, Q = \soc.cpu.picorv32_core.instr_sll).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14735 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9652_Y, Q = \soc.cpu.picorv32_core.instr_sub, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17327 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1067$7172_Y, Q = \soc.cpu.picorv32_core.instr_sub).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14734 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9656_Y, Q = \soc.cpu.picorv32_core.instr_add, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17329 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1066$7168_Y, Q = \soc.cpu.picorv32_core.instr_add).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14733 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1064$7164_Y, Q = \soc.cpu.picorv32_core.instr_srai).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14732 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1063$7160_Y, Q = \soc.cpu.picorv32_core.instr_srli).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14731 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1062$7156_Y, Q = \soc.cpu.picorv32_core.instr_slli).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14730 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9666_Y, Q = \soc.cpu.picorv32_core.instr_andi, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17334 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1060$7152_Y, Q = \soc.cpu.picorv32_core.instr_andi).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14729 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9670_Y, Q = \soc.cpu.picorv32_core.instr_ori, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17336 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1059$7150_Y, Q = \soc.cpu.picorv32_core.instr_ori).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14728 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9674_Y, Q = \soc.cpu.picorv32_core.instr_xori, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17338 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1058$7148_Y, Q = \soc.cpu.picorv32_core.instr_xori).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14727 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9678_Y, Q = \soc.cpu.picorv32_core.instr_sltiu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17340 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1057$7146_Y, Q = \soc.cpu.picorv32_core.instr_sltiu).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14726 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9682_Y, Q = \soc.cpu.picorv32_core.instr_slti, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17342 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1056$7144_Y, Q = \soc.cpu.picorv32_core.instr_slti).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14725 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9686_Y, Q = \soc.cpu.picorv32_core.instr_addi, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17344 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1055$7142_Y, Q = \soc.cpu.picorv32_core.instr_addi).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14724 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1053$7140_Y, Q = \soc.cpu.picorv32_core.instr_sw).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14723 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1052$7138_Y, Q = \soc.cpu.picorv32_core.instr_sh).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14722 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1051$7136_Y, Q = \soc.cpu.picorv32_core.instr_sb).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14721 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1049$7134_Y, Q = \soc.cpu.picorv32_core.instr_lhu).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14720 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1048$7132_Y, Q = \soc.cpu.picorv32_core.instr_lbu).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14719 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1047$7130_Y, Q = \soc.cpu.picorv32_core.instr_lw).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14718 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1046$7128_Y, Q = \soc.cpu.picorv32_core.instr_lh).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14717 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1045$7126_Y, Q = \soc.cpu.picorv32_core.instr_lb).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14716 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9706_Y, Q = \soc.cpu.picorv32_core.instr_bgeu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17354 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1043$7124_Y, Q = \soc.cpu.picorv32_core.instr_bgeu).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14715 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9710_Y, Q = \soc.cpu.picorv32_core.instr_bltu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17356 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1042$7122_Y, Q = \soc.cpu.picorv32_core.instr_bltu).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14714 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9714_Y, Q = \soc.cpu.picorv32_core.instr_bge, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17358 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1041$7120_Y, Q = \soc.cpu.picorv32_core.instr_bge).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14713 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9718_Y, Q = \soc.cpu.picorv32_core.instr_blt, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17360 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1040$7118_Y, Q = \soc.cpu.picorv32_core.instr_blt).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14712 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9722_Y, Q = \soc.cpu.picorv32_core.instr_bne, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17362 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1039$7116_Y, Q = \soc.cpu.picorv32_core.instr_bne).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14711 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9726_Y, Q = \soc.cpu.picorv32_core.instr_beq, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17364 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1038$7114_Y, Q = \soc.cpu.picorv32_core.instr_beq).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14710 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9739_Y, Q = \soc.cpu.picorv32_core.instr_jalr).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14709 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9751_Y, Q = \soc.cpu.picorv32_core.instr_jal).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14708 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:866$7042_Y, Q = \soc.cpu.picorv32_core.instr_auipc).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14707 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9771_Y, Q = \soc.cpu.picorv32_core.instr_lui).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14706 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_rdata_q, Q = \soc.cpu.picorv32_core.pcpi_insn).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14700 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8120_Y, Q = \soc.cpu.picorv32_core.do_waitirq, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14698 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_not$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1424$7367_Y, Q = \soc.cpu.picorv32_core.pcpi_timeout, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14697 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8359_Y, Q = \soc.cpu.picorv32_core.pcpi_timeout_counter, rval = 4'1111).
Adding EN signal on $auto$opt_dff.cc:702:run$17379 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$7366_Y [3:0], Q = \soc.cpu.picorv32_core.pcpi_timeout_counter).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14695 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8374_Y, Q = \soc.cpu.picorv32_core.latched_rd, rval = 5'00010).
Adding EN signal on $auto$opt_dff.cc:702:run$17381 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8374_Y, Q = \soc.cpu.picorv32_core.latched_rd).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14694 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8400_Y, Q = \soc.cpu.picorv32_core.latched_is_lb, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17389 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8400_Y, Q = \soc.cpu.picorv32_core.latched_is_lb).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14693 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8413_Y, Q = \soc.cpu.picorv32_core.latched_is_lh, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17399 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8413_Y, Q = \soc.cpu.picorv32_core.latched_is_lh).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14692 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8426_Y, Q = \soc.cpu.picorv32_core.latched_is_lu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17409 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8426_Y, Q = \soc.cpu.picorv32_core.latched_is_lu).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14690 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.compressed_instr, Q = \soc.cpu.picorv32_core.latched_compr).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14689 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8471_Y, Q = \soc.cpu.picorv32_core.latched_branch, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17426 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8471_Y, Q = \soc.cpu.picorv32_core.latched_branch).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14688 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8507_Y, Q = \soc.cpu.picorv32_core.latched_stalu, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17434 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8507_Y, Q = \soc.cpu.picorv32_core.latched_stalu).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14687 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8514_Y, Q = \soc.cpu.picorv32_core.latched_store, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$17442 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8514_Y, Q = \soc.cpu.picorv32_core.latched_store).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14683 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8572_Y, Q = \soc.cpu.picorv32_core.irq_state, rval = 2'00).
Adding EN signal on $auto$opt_dff.cc:702:run$17452 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1535$7412_Y, Q = \soc.cpu.picorv32_core.irq_state).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14676 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8134_Y, Q = \soc.cpu.picorv32_core.decoder_pseudo_trigger, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14673 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8784_Y, Q = \soc.cpu.picorv32_core.mem_do_wdata, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$17463 ($sdff) from module mgmt_core (D = 1'0, Q = \soc.cpu.picorv32_core.mem_do_wdata).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14672 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8788_Y, Q = \soc.cpu.picorv32_core.mem_do_rdata, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$17465 ($sdff) from module mgmt_core (D = 1'0, Q = \soc.cpu.picorv32_core.mem_do_rdata).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14671 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8862_Y, Q = \soc.cpu.picorv32_core.mem_do_rinst, rval = 1'1).
Adding EN signal on $auto$opt_dff.cc:702:run$17467 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8862_Y, Q = \soc.cpu.picorv32_core.mem_do_rinst).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14670 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8887_Y, Q = \soc.cpu.picorv32_core.mem_do_prefetch, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17479 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1568$7426_Y, Q = \soc.cpu.picorv32_core.mem_do_prefetch).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14668 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8933_Y, Q = \soc.cpu.picorv32_core.timer, rval = 0).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14666 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8951_Y, Q = \soc.cpu.picorv32_core.irq_mask, rval = 32'11111111111111111111111111111111).
Adding EN signal on $auto$opt_dff.cc:702:run$17492 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs_rs1, Q = \soc.cpu.picorv32_core.irq_mask).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14665 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8970_Y, Q = \soc.cpu.picorv32_core.irq_active, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17496 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8970_Y, Q = \soc.cpu.picorv32_core.irq_active).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14664 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8995_Y, Q = \soc.cpu.picorv32_core.irq_delay, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17506 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.irq_active, Q = \soc.cpu.picorv32_core.irq_delay).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14662 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8267_Y, Q = \soc.cpu.picorv32_core.reg_out, rval = 1024).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14661 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9008_Y, Q = \soc.cpu.picorv32_core.reg_op2).
Adding EN signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14660 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9030_Y, Q = \soc.cpu.picorv32_core.reg_op1).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14659 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9091_Y, Q = \soc.cpu.picorv32_core.reg_next_pc, rval = 268435456).
Adding EN signal on $auto$opt_dff.cc:702:run$17535 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9089_Y, Q = \soc.cpu.picorv32_core.reg_next_pc).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14658 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9103_Y, Q = \soc.cpu.picorv32_core.reg_pc, rval = 268435456).
Adding EN signal on $auto$opt_dff.cc:702:run$17537 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0], Q = \soc.cpu.picorv32_core.reg_pc).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14657 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9123_Y, Q = \soc.cpu.picorv32_core.count_instr, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$opt_dff.cc:702:run$17539 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$7422_Y, Q = \soc.cpu.picorv32_core.count_instr).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14656 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$7368_Y, Q = \soc.cpu.picorv32_core.count_cycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14652 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9167_Y, Q = \soc.cpu.picorv32_core.pcpi_valid, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17548 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9163_Y, Q = \soc.cpu.picorv32_core.pcpi_valid).
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14651 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$8353_Y, Q = \soc.cpu.picorv32_core.trap, rval = 1'0).
Adding SRST signal on $flatten\soc.\cpu.$procdff$14885 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12362_Y, Q = \soc.cpu.wbm_cyc_o, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17553 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12362_Y, Q = \soc.cpu.wbm_cyc_o).
Adding SRST signal on $flatten\soc.\cpu.$procdff$14884 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12375_Y, Q = \soc.cpu.wbm_stb_o, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17561 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12375_Y, Q = \soc.cpu.wbm_stb_o).
Adding SRST signal on $flatten\soc.\cpu.$procdff$14883 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12390_Y, Q = \soc.cpu.wbm_sel_o, rval = 4'0000).
Adding EN signal on $auto$opt_dff.cc:702:run$17569 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_wstrb, Q = \soc.cpu.wbm_sel_o).
Adding SRST signal on $flatten\soc.\cpu.$procdff$14882 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12399_Y, Q = \soc.cpu.wbm_we_o, rval = 1'0).
Adding EN signal on $auto$opt_dff.cc:702:run$17573 ($sdff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12399_Y, Q = \soc.cpu.wbm_we_o).
Adding SRST signal on $flatten\soc.\cpu.$procdff$14881 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12414_Y, Q = \soc.cpu.wbm_dat_o, rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$17581 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_wdata, Q = \soc.cpu.wbm_dat_o).
Adding SRST signal on $flatten\soc.\cpu.$procdff$14880 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12425_Y, Q = \soc.cpu.wbm_adr_o, rval = 0).
Adding EN signal on $auto$opt_dff.cc:702:run$17585 ($sdff) from module mgmt_core (D = \soc.cpu.picorv32_core.mem_addr, Q = \soc.cpu.wbm_adr_o).
Adding EN signal on $flatten\soc.\cpu.$procdff$14879 ($dff) from module mgmt_core (D = \soc.cpu.wbm_dat_i, Q = \soc.cpu.mem_rdata).
Adding EN signal on $flatten\soc.\cpu.$procdff$14878 ($dff) from module mgmt_core (D = $flatten\soc.\cpu.$procmux$12440_Y, Q = \soc.cpu.mem_ready).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14909 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [3], Q = \soc.counter_timer_1.counter_timer_high_inst.chain).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14908 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [4], Q = \soc.counter_timer_1.counter_timer_high_inst.irq_ena).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14907 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [2], Q = \soc.counter_timer_1.counter_timer_high_inst.updown).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14906 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [1], Q = \soc.counter_timer_1.counter_timer_high_inst.oneshot).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14905 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.counter_timer_1.counter_timer_high_inst.enable).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14904 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.counter_timer_1.counter_timer_high_inst.value_reset [7:0]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14904 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.counter_timer_1.counter_timer_high_inst.value_reset [15:8]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14904 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.counter_timer_1.counter_timer_high_inst.value_reset [23:16]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14904 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.counter_timer_1.counter_timer_high_inst.value_reset [31:24]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14902 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$0\value_cur[31:0] [7:0], Q = \soc.counter_timer_1.counter_timer_high_inst.value_cur [7:0]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14902 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$0\value_cur[31:0] [15:8], Q = \soc.counter_timer_1.counter_timer_high_inst.value_cur [15:8]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14902 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$0\value_cur[31:0] [23:16], Q = \soc.counter_timer_1.counter_timer_high_inst.value_cur [23:16]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14902 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$0\value_cur[31:0] [31:24], Q = \soc.counter_timer_1.counter_timer_high_inst.value_cur [31:24]).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14901 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$13011_Y, Q = \soc.counter_timer_1.counter_timer_high_inst.stop_out).
Adding EN signal on $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procdff$14900 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:197$1466_Y, Q = \soc.counter_timer_1.counter_timer_high_inst.irq_out).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14899 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [3], Q = \soc.counter_timer_0.counter_timer_low_inst.chain).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14898 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [4], Q = \soc.counter_timer_0.counter_timer_low_inst.irq_ena).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14897 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [2], Q = \soc.counter_timer_0.counter_timer_low_inst.updown).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14896 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [1], Q = \soc.counter_timer_0.counter_timer_low_inst.oneshot).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14895 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [0], Q = \soc.counter_timer_0.counter_timer_low_inst.enable).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14894 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [7:0], Q = \soc.counter_timer_0.counter_timer_low_inst.value_reset [7:0]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14894 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [15:8], Q = \soc.counter_timer_0.counter_timer_low_inst.value_reset [15:8]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14894 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [23:16], Q = \soc.counter_timer_0.counter_timer_low_inst.value_reset [23:16]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14894 ($adff) from module mgmt_core (D = \soc.cpu.wbm_dat_o [31:24], Q = \soc.counter_timer_0.counter_timer_low_inst.value_reset [31:24]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14892 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$0\value_cur[31:0] [7:0], Q = \soc.counter_timer_0.counter_timer_low_inst.value_cur [7:0]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14892 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$0\value_cur[31:0] [15:8], Q = \soc.counter_timer_0.counter_timer_low_inst.value_cur [15:8]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14892 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$0\value_cur[31:0] [23:16], Q = \soc.counter_timer_0.counter_timer_low_inst.value_cur [23:16]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14892 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$0\value_cur[31:0] [31:24], Q = \soc.counter_timer_0.counter_timer_low_inst.value_cur [31:24]).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14891 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12696_Y, Q = \soc.counter_timer_0.counter_timer_low_inst.stop_out).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14890 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12725_Y, Q = \soc.counter_timer_0.counter_timer_low_inst.strobe).
Adding EN signal on $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procdff$14889 ($adff) from module mgmt_core (D = $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:205$1527_Y, Q = \soc.counter_timer_0.counter_timer_low_inst.irq_out).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15040 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$procmux$14440_Y, Q = \housekeeping.U1.ldata).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15039 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$0\wrstb[0:0], Q = \housekeeping.U1.wrstb).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15037 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$procmux$14203_Y, Q = \housekeeping.U1.pre_pass_thru_user).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15036 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$procmux$14229_Y, Q = \housekeeping.U1.pre_pass_thru_mgmt).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15035 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata [5:0] \housekeeping.SDI }, Q = \housekeeping.U1.predata).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15034 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$0\fixed[2:0], Q = \housekeeping.U1.fixed).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15033 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.U1.readmode).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15032 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.U1.writemode).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15031 ($adff) from module mgmt_core (D = \housekeeping.U1.pre_pass_thru_user, Q = \housekeeping.U1.pass_thru_user_delay).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15030 ($adff) from module mgmt_core (D = 1'1, Q = \housekeeping.U1.pass_thru_user).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15029 ($adff) from module mgmt_core (D = \housekeeping.U1.pre_pass_thru_mgmt, Q = \housekeeping.U1.pass_thru_mgmt_delay).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15027 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$0\count[2:0], Q = \housekeeping.U1.count).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15026 ($adff) from module mgmt_core (D = $flatten\housekeeping.\U1.$procmux$14370_Y, Q = \housekeeping.U1.addr).
Adding EN signal on $flatten\housekeeping.\U1.$procdff$15024 ($adff) from module mgmt_core (D = 1'1, Q = \housekeeping.U1.pass_thru_mgmt).
Adding EN signal on $flatten\housekeeping.$procdff$15049 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.reset_reg).
Adding EN signal on $flatten\housekeeping.$procdff$15048 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.irq).
Adding EN signal on $flatten\housekeeping.$procdff$15047 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.pll_bypass).
Adding EN signal on $flatten\housekeeping.$procdff$15046 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata [0] \housekeeping.SDI }, Q = \housekeeping.pll_trim [25:24]).
Adding EN signal on $flatten\housekeeping.$procdff$15046 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata \housekeeping.SDI }, Q = \housekeeping.pll_trim [23:16]).
Adding EN signal on $flatten\housekeeping.$procdff$15046 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata \housekeeping.SDI }, Q = \housekeeping.pll_trim [15:8]).
Adding EN signal on $flatten\housekeeping.$procdff$15046 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata \housekeeping.SDI }, Q = \housekeeping.pll_trim [7:0]).
Adding EN signal on $flatten\housekeeping.$procdff$15045 ($adff) from module mgmt_core (D = \housekeeping.SDI, Q = \housekeeping.pll_ena).
Adding EN signal on $flatten\housekeeping.$procdff$15044 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata [3:0] \housekeeping.SDI }, Q = \housekeeping.pll_div).
Adding EN signal on $flatten\housekeeping.$procdff$15043 ($adff) from module mgmt_core (D = \housekeeping.U1.predata [4:2], Q = \housekeeping.pll90_sel).
Adding EN signal on $flatten\housekeeping.$procdff$15042 ($adff) from module mgmt_core (D = { \housekeeping.U1.predata [1:0] \housekeeping.SDI }, Q = \housekeeping.pll_sel).
Adding EN signal on $flatten\housekeeping.$procdff$15041 ($adff) from module mgmt_core (D = \housekeeping.U1.predata [0], Q = \housekeeping.pll_dco_ena).
Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$15081 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\out_counter[0:0], Q = \clocking.divider2.odd_0.out_counter).
Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$15074 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\counter[2:0], Q = \clocking.divider2.odd_0.counter).
Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$15067 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\initial_begin[2:0], Q = \clocking.divider2.odd_0.initial_begin).
Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$15066 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\out_counter2[0:0], Q = \clocking.divider2.odd_0.out_counter2).
Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$15059 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$0\counter2[2:0], Q = \clocking.divider2.odd_0.counter2).
Adding EN signal on $flatten\clocking.\divider2.\odd_0.$procdff$15058 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\odd_0.$procmux$14570_Y, Q = \clocking.divider2.odd_0.rst_pulse).
Adding EN signal on $flatten\clocking.\divider2.\even_0.$procdff$15056 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\even_0.$not$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:188$255_Y, Q = \clocking.divider2.even_0.out_counter).
Adding EN signal on $flatten\clocking.\divider2.\even_0.$procdff$15055 ($adff) from module mgmt_core (D = $flatten\clocking.\divider2.\even_0.$procmux$14565_Y, Q = \clocking.divider2.even_0.counter).
Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$15081 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\out_counter[0:0], Q = \clocking.divider.odd_0.out_counter).
Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$15074 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\counter[2:0], Q = \clocking.divider.odd_0.counter).
Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$15067 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\initial_begin[2:0], Q = \clocking.divider.odd_0.initial_begin).
Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$15066 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\out_counter2[0:0], Q = \clocking.divider.odd_0.out_counter2).
Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$15059 ($dffsr) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$0\counter2[2:0], Q = \clocking.divider.odd_0.counter2).
Adding EN signal on $flatten\clocking.\divider.\odd_0.$procdff$15058 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\odd_0.$procmux$14570_Y, Q = \clocking.divider.odd_0.rst_pulse).
Adding EN signal on $flatten\clocking.\divider.\even_0.$procdff$15056 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\even_0.$not$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:188$255_Y, Q = \clocking.divider.even_0.out_counter).
Adding EN signal on $flatten\clocking.\divider.\even_0.$procdff$15055 ($adff) from module mgmt_core (D = $flatten\clocking.\divider.\even_0.$procmux$14565_Y, Q = \clocking.divider.even_0.counter).

13.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 933 unused cells and 1005 unused wires.
<suppressed ~936 debug messages>

13.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~188 debug messages>

13.9.9. Rerunning OPT passes. (Maybe there is more to do..)

13.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~344 debug messages>

13.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
Performed a total of 0 changes.

13.9.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
<suppressed ~771 debug messages>
Removed a total of 257 cells.

13.9.13. Executing OPT_DFF pass (perform DFF optimizations).

13.9.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 372 unused wires.
<suppressed ~1 debug messages>

13.9.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

13.9.16. Rerunning OPT passes. (Maybe there is more to do..)

13.9.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~345 debug messages>

13.9.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
Performed a total of 0 changes.

13.9.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

13.9.20. Executing OPT_DFF pass (perform DFF optimizations).

13.9.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

13.9.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

13.9.23. Finished OPT passes. (There is nothing left to do.)

13.10. Executing WREDUCE pass (reducing word size of cells).
Removed top 4 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15254 ($eq).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15258 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256 ($sub).
Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256 ($sub).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider2.\even_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:184$254 ($eq).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14611 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14603 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14601 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14595 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14586 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14584 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14577 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$procmux$14574 ($mux).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:110$240 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:106$238 ($le).
Removed top 1 bits (of 4) from port A of cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235 ($add).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider2.\odd_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:80$232 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256 ($sub).
Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256 ($sub).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider.\even_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:184$254 ($eq).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14611 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14603 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14601 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14595 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14586 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14584 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14577 ($mux).
Removed cell mgmt_core.$flatten\clocking.\divider.\odd_0.$procmux$14574 ($mux).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider.\odd_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:110$240 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\clocking.\divider.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:106$238 ($le).
Removed top 1 bits (of 4) from port A of cell mgmt_core.$flatten\clocking.\divider.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235 ($add).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\clocking.\divider.\odd_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:80$232 ($eq).
Removed top 3 bits (of 5) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16571 ($ne).
Removed top 3 bits (of 5) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16567 ($ne).
Removed top 3 bits (of 6) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16565 ($ne).
Removed top 3 bits (of 7) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16563 ($ne).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16561 ($ne).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16554 ($ne).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16505 ($ne).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16480 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16443 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16441 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16439 ($ne).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16130 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16126 ($eq).
Removed top 3 bits (of 9) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16287 ($ne).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16261 ($ne).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16108 ($eq).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16154 ($eq).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16139 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15514 ($eq).
Removed top 2 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15522 ($eq).
Removed top 4 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15506 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15502 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16585 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16575 ($ne).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15262 ($eq).
Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15347 ($eq).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15343 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15339 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15355 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15266 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16073 ($eq).
Removed top 2 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15765 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15748 ($eq).
Removed top 5 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15744 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15736 ($eq).
Removed top 5 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15732 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15724 ($eq).
Removed top 6 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15720 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15712 ($eq).
Removed top 5 bits (of 11) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15708 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15700 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15688 ($eq).
Removed top 5 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15684 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15679 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$16057 ($eq).
Removed top 3 bits (of 5) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$16272 ($ne).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15983 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15981 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15975 ($eq).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15971 ($eq).
Removed top 1 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15331 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15952 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15323 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15946 ($eq).
Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15315 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15925 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15915 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15894 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15882 ($eq).
Removed top 2 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15870 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15858 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15834 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15825 ($eq).
Removed top 2 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15813 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15801 ($eq).
Removed top 2 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15789 ($eq).
Removed top 2 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15777 ($eq).
Removed top 1 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15655 ($eq).
Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15639 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15635 ($eq).
Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15651 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15663 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15659 ($eq).
Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15544 ($eq).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15606 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15598 ($eq).
Removed top 3 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15590 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15586 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15564 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15556 ($eq).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15628 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15548 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15647 ($eq).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15624 ($eq).
Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15671 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15643 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15675 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15667 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15279 ($eq).
Removed top 7 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4412 ($eq).
Removed top 6 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4414 ($eq).
Removed top 3 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4416 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17632 ($ne).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4418 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4420 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4422 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4424 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4426 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4428 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4430 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4432 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4434 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\intercon.$eq$/project/openlane/mgmt_core/../../verilog/rtl/wb_intercon.v:43$4436 ($eq).
Removed top 4 bits (of 8) from port Y of cell mgmt_core.$flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:49$4505 ($and).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:49$4505 ($and).
Removed top 3 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\wb_bridge.$eq$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:72$4654 ($eq).
Removed top 2 bits (of 7) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17617 ($ne).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12274 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12262 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12250 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12238 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12226 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12214 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12202 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12190 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12178 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12166 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12154 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12142 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12130 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12118 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12106 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12094 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12082 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12070 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12058 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12046 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12034 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12022 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$12010 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11998 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11986 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11974 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11962 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11950 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11938 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11926 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11914 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11902 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11890 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11878 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11866 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11854 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11842 ($mux).
Removed top 19 bits (of 32) from mux cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11830 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11782 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11771 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11760 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11749 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11739 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11737 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11732 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11727 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11722 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11714 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11712 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11704 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11702 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11699 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11696 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11693 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11685 ($mux).
Removed cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11683 ($mux).
Removed top 5 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11656_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11655_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11654_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11653_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11652_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11651_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11650_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11649_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11648_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11647_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11646_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11645_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11644_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11643_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11642_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11641_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11640_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11639_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11638_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11637_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11636_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11635_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11634_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11633_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11632_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11631_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11630_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11629_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11628_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11627_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11626_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6531 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6526 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6521 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6516 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6511 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6506 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6501 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6496 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6491 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6486 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6481 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6476 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6471 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6466 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6461 ($eq).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6456 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6451 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6446 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6441 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6436 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6431 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6426 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6421 ($eq).
Removed top 2 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:160$6416 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:359$6409 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:356$6408 ($eq).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:353$6407 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:337$6403 ($add).
Removed top 28 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:337$6403 ($add).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$6395 ($sub).
Removed top 26 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$6395 ($sub).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:319$6392 ($eq).
Removed top 2 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:213$6373 ($eq).
Removed cell mgmt_core.$flatten\soc.\la.\la_ctrl.$procmux$11052 ($mux).
Removed top 2 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:138$6859 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:119$6854 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:120$6853 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:121$6852 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\la.\la_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/la_wb.v:122$6851 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17621 ($ne).
Removed top 28 bits (of 32) from mux cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11172 ($mux).
Removed top 28 bits (of 32) from mux cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11169 ($mux).
Removed top 28 bits (of 32) from mux cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11166 ($mux).
Removed cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11163 ($mux).
Removed top 2 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/sysctrl.v:133$5447 ($eq).
Removed top 30 bits (of 32) from mux cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11193 ($mux).
Removed top 30 bits (of 32) from mux cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11190 ($mux).
Removed top 30 bits (of 32) from mux cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11187 ($mux).
Removed cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11184 ($mux).
Removed top 2 bits (of 24) from port B of cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:115$5437 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:105$5432 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:104$5431 ($eq).
Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$eq$/project/openlane/mgmt_core/../../verilog/rtl/gpio_wb.v:103$5430 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:39$4669 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:40$4671 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:41$4673 ($eq).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12958 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12955 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12918 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12906 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12903 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12866 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12854 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12851 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12814 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12802 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12799 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12777 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12762 ($mux).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:168$1453 ($sub).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_1.\counter_timer_high_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:167$1452 ($add).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:40$4691 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:41$4693 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:42$4695 ($eq).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12718 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12708 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12642 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12639 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12595 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12592 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12548 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12545 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12501 ($mux).
Removed cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12498 ($mux).
Removed top 30 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:262$1544 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:171$1512 ($sub).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\counter_timer_0.\counter_timer_low_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:170$1511 ($add).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:99$4713 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:100$4715 ($eq).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13156 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13153 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13151 ($mux).
Removed top 1 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15472 ($eq).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13116 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13112 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13109 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13106 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13098 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13095 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13092 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13088 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13084 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13081 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13059 ($mux).
Removed cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$procmux$13048 ($mux).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:329$1404 ($add).
Removed top 24 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:329$1404 ($add).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17475 ($ne).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:304$1397 ($add).
Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:304$1397 ($add).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:52$4731 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:53$4733 ($eq).
Removed top 2 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.$eq$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:54$4735 ($eq).
Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13296 ($mux).
Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13293 ($mux).
Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13289 ($mux).
Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13286 ($mux).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13253_CMP0 ($eq).
Removed top 1 bits (of 10) from mux cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13238 ($mux).
Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13235 ($mux).
Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13224 ($mux).
Removed cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13216 ($mux).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:217$1336 ($sub).
Removed top 28 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:217$1336 ($sub).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:197$1328 ($add).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:184$1325 ($add).
Removed top 28 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:184$1325 ($add).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:159$1318 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:633$1247 ($sub).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:653$1254 ($sub).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:686$1266 ($sub).
Removed top 28 bits (of 32) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:729$1285 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13354 ($mux).
Removed top 1 bits (of 4) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13361 ($mux).
Removed top 1 bits (of 4) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13364 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13379 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13382 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13399 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13402 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13419 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13421 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13423_CMP0 ($eq).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13425 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13430 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13443 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13460 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13462 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13469 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13480 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13494 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13496 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13504 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13516 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13534 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13544 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13554 ($mux).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17254 ($ne).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17250 ($ne).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17248 ($ne).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17246 ($ne).
Removed top 1 bits (of 4) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13638 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13644 ($mux).
Removed top 2 bits (of 4) from FF cell mgmt_core.$auto$opt_dff.cc:764:run$16318 ($sdffe).
Removed top 3 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15464 ($eq).
Removed top 1 bits (of 10) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15460 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$13873_CMP0 ($eq).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$13867 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$13847 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$13837 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$13723 ($mux).
Removed cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$procmux$13706 ($mux).
Removed top 1 bits (of 8) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:478$1232 ($mux).
Removed top 8 bits (of 32) from mux cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:388$1227 ($mux).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$eq$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:386$1223 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$eq$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:385$1221 ($eq).
Removed top 2 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$eq$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:384$1219 ($eq).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$eq$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:383$1217 ($eq).
Removed top 29 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1138 ($add).
Removed top 7 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1138 ($add).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15430 ($eq).
Removed cell mgmt_core.$flatten\soc.\cpu.$procmux$12360 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.$procmux$12442 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.$procmux$12446 ($mux).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2439$1060 ($eq).
Removed top 6 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2439$1062 ($eq).
Removed top 31 bits (of 63) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1075 ($neg).
Removed top 31 bits (of 63) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1077 ($mux).
Removed top 31 bits (of 63) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1093 ($sub).
Removed top 31 bits (of 63) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1093 ($sub).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$13996 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$13999 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14002 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14029 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14038 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14046 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14049 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14058 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14066 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14069 ($mux).
Removed top 1 bits (of 5) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1019 ($add).
Removed top 1 bits (of 5) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1019 ($add).
Removed top 26 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2286$1025 ($mux).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1027 ($sub).
Removed top 25 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1027 ($sub).
Removed top 32 bits (of 64) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2308$1031 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14128 ($mux).
Removed top 1 bits (of 64) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14152 ($mux).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14158_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14163_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14169_CMP0 ($eq).
Removed cell mgmt_core.$auto$opt_dff.cc:764:run$17151 ($dffe).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\cpuregs.$procmux$14618 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\cpuregs.$procmux$14620 ($mux).
Removed top 31 bits (of 32) from FF cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\cpuregs.$procdff$15084 ($dff).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17895 ($ne).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17900 ($ne).
Removed top 16 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10358 ($pmux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10352_CMP0 ($eq).
Removed top 24 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10349 ($pmux).
Removed top 2 bits (of 6) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10333 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17929 ($ne).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17934 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10165_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10144_CMP0 ($eq).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10127 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10121 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10118 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10111 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10072 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10066 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10063 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10061 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10057 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10053 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10018_CMP0 ($eq).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10011 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10008 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$10006 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17654 ($ne).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9586_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17676 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17683 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17690 ($ne).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17697 ($ne).
Removed top 2 bits (of 4) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9362 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9211 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17744 ($ne).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9036 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9034 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9028 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9026 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8974 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8968 ($mux).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15418 ($eq).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8860 ($mux).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17766 ($ne).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17768 ($ne).
Removed top 1 bits (of 5) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17770 ($ne).
Removed top 1 bits (of 6) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15396 ($eq).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8528 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8502 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8479 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8424 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8422 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8411 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8409 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8398 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8396 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8369 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8311 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8308 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8306 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8278 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8265 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8263 ($mux).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17827 ($ne).
Removed top 1 bits (of 4) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17829 ($ne).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8005 ($mux).
Removed cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$8002 ($mux).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15388 ($eq).
Removed top 1 bits (of 33) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sshr$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1240$7551 ($sshr).
Removed top 20 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$or$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1911$7506 ($or).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$7422 ($add).
Removed top 29 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7418 ($mux).
Removed top 29 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1541$7413 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$7410 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1438$7373 ($sub).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$7368 ($add).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$7366 ($sub).
Removed top 28 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$7366 ($sub).
Removed top 29 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$7335 ($mux).
Removed top 4 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1090$7254 ($eq).
Removed top 5 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1089$7250 ($eq).
Removed top 3 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1089$7249 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1064$7163 ($eq).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1057$7145 ($eq).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1047$7129 ($eq).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1039$7115 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17643 ($ne).
Removed top 28 bits (of 32) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$7073 ($add).
Removed top 27 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$7073 ($add).
Removed top 28 bits (of 32) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$7072 ($add).
Removed top 27 bits (of 32) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$7072 ($add).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:876$7059 ($eq).
Removed top 2 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:875$7058 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:874$7057 ($eq).
Removed top 5 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:873$7056 ($eq).
Removed top 4 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:870$7052 ($eq).
Removed top 5 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:869$7048 ($eq).
Removed top 3 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:869$7047 ($eq).
Removed top 2 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:866$7042 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:865$7041 ($eq).
Removed top 30 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:617$7022 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$opt_dff.cc:218:make_patterns_logic$17221 ($ne).
Removed top 1 bits (of 7) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:491$6978 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:488$6974 ($eq).
Removed top 1 bits (of 3) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:486$6972 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:478$6970 ($eq).
Removed top 3 bits (of 5) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:465$6968 ($eq).
Removed top 3 bits (of 4) from port A of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$shl$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:419$6963 ($shl).
Removed top 16 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:386$6955 ($mux).
Removed top 16 bits (of 32) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:388$6953 ($mux).
Removed top 31 bits (of 32) from mux cell mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:25$2911 ($mux).
Removed top 31 bits (of 32) from mux cell mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:24$2913 ($mux).
Removed top 31 bits (of 32) from mux cell mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:28$2918 ($mux).
Removed top 31 bits (of 32) from mux cell mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:27$2919 ($mux).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15288 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15297 ($eq).
Removed top 1 bits (of 7) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15480 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15380 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:420$3014 ($add).
Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:420$3014 ($add).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:423$3016 ($eq).
Removed top 2 bits (of 3) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:459$3030 ($eq).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3032 ($sub).
Removed top 29 bits (of 32) from port Y of cell mgmt_core.$flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3032 ($sub).
Removed top 31 bits (of 32) from port B of cell mgmt_core.$flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:463$3033 ($add).
Removed top 24 bits (of 32) from port Y of cell mgmt_core.$flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:463$3033 ($add).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14198 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14200 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14223 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14226 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14254 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14257 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14259 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14261 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14264 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14268 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14271 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14274 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14349 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14352 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14355 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14363 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14365 ($mux).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14367 ($mux).
Removed top 1 bits (of 9) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15376 ($eq).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$auto$fsm_map.cc:77:implement_pattern_cache$15367 ($eq).
Removed cell mgmt_core.$flatten\housekeeping.\U1.$procmux$14450 ($mux).
Removed top 3 bits (of 8) from mux cell mgmt_core.$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:193$2975 ($mux).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:193$2974 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$2973 ($eq).
Removed top 3 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$2972 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:190$2971 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:189$2970 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:188$2969 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:187$2968 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:186$2967 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:185$2966 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:184$2965 ($eq).
Removed top 4 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:183$2964 ($eq).
Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:181$2963 ($eq).
Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:180$2962 ($eq).
Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:179$2961 ($eq).
Removed top 5 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:178$2960 ($eq).
Removed top 6 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:177$2959 ($eq).
Removed top 6 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:176$2958 ($eq).
Removed top 7 bits (of 8) from port B of cell mgmt_core.$flatten\housekeeping.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:175$2957 ($eq).
Removed top 1 bits (of 2) from port Y of cell mgmt_core.$flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:48$4504 ($and).
Removed top 1 bits (of 2) from port B of cell mgmt_core.$flatten\soc.\wb_bridge.$and$/project/openlane/mgmt_core/../../verilog/rtl/storage_bridge_wb.v:48$4504 ($and).
Removed top 7 bits (of 32) from port B of cell mgmt_core.$flatten\soc.\spimemio.\spimemio.$ne$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1139 ($ne).
Removed top 31 bits (of 63) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1075 ($neg).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1004 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1006 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1008 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1010 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1012 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1014 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1016 ($add).
Removed top 3 bits (of 4) from port B of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1018 ($add).
Removed top 1 bits (of 5) from port Y of cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1018 ($add).
Removed top 1 bits (of 64) from mux cell mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14150 ($mux).
Removed top 29 bits (of 32) from wire mgmt_core.$flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256_Y.
Removed top 29 bits (of 32) from wire mgmt_core.$flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256_Y.
Removed top 3 bits (of 8) from wire mgmt_core.$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:193$2975_Y.
Removed top 31 bits (of 32) from wire mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:25$2911_Y.
Removed top 31 bits (of 32) from wire mgmt_core.$flatten\soc.\convert_gpio_bit.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/convert_gpio_sigs.v:28$2918_Y.
Removed top 16 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$2\mem_rdata_word[31:0].
Removed top 24 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$3\mem_rdata_word[31:0].
Removed top 27 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$7072_Y.
Removed top 27 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$7073_Y.
Removed top 2 bits (of 4) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$procmux$9362_Y.
Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$7366_Y.
Removed top 29 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$7335_Y.
Removed top 29 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1541$7413_Y.
Removed top 29 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7418_Y.
Removed top 1 bits (of 7) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:491$6978_Y.
Removed top 31 bits (of 63) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1075_Y.
Removed top 1 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14038_Y.
Removed top 1 bits (of 63) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_div.$procmux$14058_Y.
Removed top 1 bits (of 5) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1018_Y.
Removed top 1 bits (of 64) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14150_Y.
Removed top 1 bits (of 64) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14152_Y.
Removed top 25 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1027_Y.
Removed top 26 bits (of 32) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2286$1025_Y.
Removed top 32 bits (of 64) from wire mgmt_core.$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2308$1031_Y.
Removed top 30 bits (of 32) from wire mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11187_Y.
Removed top 30 bits (of 32) from wire mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11190_Y.
Removed top 30 bits (of 32) from wire mgmt_core.$flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11193_Y.
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$10\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$11\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$12\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$13\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$14\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$15\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$16\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$17\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$18\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$19\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$20\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$21\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$22\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$23\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$24\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$25\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$26\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$27\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$28\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$29\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$30\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$31\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$32\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$33\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$34\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$35\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$36\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$37\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$38\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$39\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$40\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$41\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$42\iomem_rdata_pre[31:0].
Removed top 19 bits (of 32) from wire mgmt_core.$flatten\soc.\mprj_ctrl.\mprj_ctrl.$43\iomem_rdata_pre[31:0].
Removed top 24 bits (of 32) from wire mgmt_core.$flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:329$1404_Y.
Removed top 2 bits (of 10) from wire mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13235_Y.
Removed top 1 bits (of 10) from wire mgmt_core.$flatten\soc.\simpleuart.\simpleuart.$procmux$13238_Y.
Removed top 7 bits (of 32) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1138_Y.
Removed top 8 bits (of 32) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:388$1227_Y.
Removed top 1 bits (of 8) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:478$1232_Y.
Removed top 3 bits (of 4) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$reduce_or$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:633$1246_Y.
Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\spimemio.\spimemio.\xfer.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:729$1285_Y.
Removed top 30 bits (of 32) from wire mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11163_Y.
Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11166_Y.
Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11169_Y.
Removed top 28 bits (of 32) from wire mgmt_core.$flatten\soc.\sysctrl.\sysctrl.$procmux$11172_Y.

13.11. Executing PEEPOPT pass (run peephole optimizers).

13.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 1 unused cells and 261 unused wires.
<suppressed ~2 debug messages>

13.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module mgmt_core:
  creating $macc model for $flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256 ($sub).
  creating $macc model for $flatten\clocking.\divider.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235 ($add).
  creating $macc model for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:114$242 ($sub).
  creating $macc model for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:117$243 ($sub).
  creating $macc model for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:84$234 ($sub).
  creating $macc model for $flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256 ($sub).
  creating $macc model for $flatten\clocking.\divider2.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235 ($add).
  creating $macc model for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:114$242 ($sub).
  creating $macc model for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:117$243 ($sub).
  creating $macc model for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:84$234 ($sub).
  creating $macc model for $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:420$3014 ($add).
  creating $macc model for $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:463$3033 ($add).
  creating $macc model for $flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3032 ($sub).
  creating $macc model for $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:170$1511 ($add).
  creating $macc model for $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:171$1512 ($sub).
  creating $macc model for $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:167$1452 ($add).
  creating $macc model for $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:168$1453 ($sub).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7543 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$7336 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$7368 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7419 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$7422 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$7423 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1801$7470 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1864$7495 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$6946 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$7072 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$7073 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7542 ($sub).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$7366 ($sub).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1438$7373 ($sub).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2469$1070 ($neg).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1075 ($neg).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2488$1088 ($neg).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2490$1090 ($neg).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1093 ($sub).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1000 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1001 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1002 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1003 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1004 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1005 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1006 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1007 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1008 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1009 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1010 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1011 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1012 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1013 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1014 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1015 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1016 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1017 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1018 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1019 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$988 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$989 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$990 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$991 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$992 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$993 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$994 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$995 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$996 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$997 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$998 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$999 ($add).
  creating $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1027 ($sub).
  creating $macc model for $flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:337$6403 ($add).
  creating $macc model for $flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$6395 ($sub).
  creating $macc model for $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:304$1397 ($add).
  creating $macc model for $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:329$1404 ($add).
  creating $macc model for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:159$1318 ($add).
  creating $macc model for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:184$1325 ($add).
  creating $macc model for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:197$1328 ($add).
  creating $macc model for $flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:217$1336 ($sub).
  creating $macc model for $flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1138 ($add).
  creating $macc model for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:633$1247 ($sub).
  creating $macc model for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:653$1254 ($sub).
  creating $macc model for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:686$1266 ($sub).
  creating $macc model for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:716$1278 ($sub).
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$998 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$999.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$996 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$997.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$994 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$995.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$992 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$993.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$990 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$991.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$988 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$989.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1018 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1019.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1016 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1017.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1014 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1015.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1012 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1013.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1010 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1011.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1008 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1009.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1006 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1007.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1004 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1005.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1002 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1003.
  merging $macc model for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1000 into $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1001.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1027.
  creating $alu model for $macc $flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:337$6403.
  creating $alu model for $macc $flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$6395.
  creating $alu model for $macc $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:304$1397.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1019.
  creating $alu model for $macc $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:329$1404.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1017.
  creating $alu model for $macc $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:159$1318.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1015.
  creating $alu model for $macc $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:184$1325.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1013.
  creating $alu model for $macc $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:197$1328.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1011.
  creating $alu model for $macc $flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:217$1336.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1009.
  creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1138.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1007.
  creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:633$1247.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1005.
  creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:653$1254.
  creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:686$1266.
  creating $alu model for $macc $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:716$1278.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1093.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2490$1090.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2488$1088.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1075.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2469$1070.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1438$7373.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$7366.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7542.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$7073.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$7072.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$6946.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1864$7495.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1801$7470.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$7423.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$7422.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7419.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$7368.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$7336.
  creating $alu model for $macc $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7543.
  creating $alu model for $macc $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:168$1453.
  creating $alu model for $macc $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:167$1452.
  creating $alu model for $macc $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:171$1512.
  creating $alu model for $macc $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:170$1511.
  creating $alu model for $macc $flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3032.
  creating $alu model for $macc $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:463$3033.
  creating $alu model for $macc $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:420$3014.
  creating $alu model for $macc $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:84$234.
  creating $alu model for $macc $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:117$243.
  creating $alu model for $macc $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:114$242.
  creating $alu model for $macc $flatten\clocking.\divider2.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235.
  creating $alu model for $macc $flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256.
  creating $alu model for $macc $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:84$234.
  creating $alu model for $macc $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:117$243.
  creating $alu model for $macc $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:114$242.
  creating $alu model for $macc $flatten\clocking.\divider.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235.
  creating $alu model for $macc $flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256.
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1003: $auto$alumacc.cc:365:replace_macc$18023
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$991: $auto$alumacc.cc:365:replace_macc$18024
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1001: $auto$alumacc.cc:365:replace_macc$18025
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$993: $auto$alumacc.cc:365:replace_macc$18026
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$989: $auto$alumacc.cc:365:replace_macc$18027
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$995: $auto$alumacc.cc:365:replace_macc$18028
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$999: $auto$alumacc.cc:365:replace_macc$18029
  creating $macc cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$997: $auto$alumacc.cc:365:replace_macc$18030
  creating $alu model for $flatten\clocking.\divider.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:106$238 ($le): new $alu
  creating $alu model for $flatten\clocking.\divider2.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:106$238 ($le): new $alu
  creating $alu model for $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017 ($lt): new $alu
  creating $alu model for $flatten\soc.\cpu.\picorv32_core.$lt$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1237$7546 ($lt): new $alu
  creating $alu model for $flatten\soc.\cpu.\picorv32_core.$lt$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1238$7547 ($lt): merged with $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7542.
  creating $alu model for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$le$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2493$1092 ($le): new $alu
  creating $alu model for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:169$1322 ($gt): new $alu
  creating $alu model for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:175$1323 ($gt): new $alu
  creating $alu model for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:215$1334 ($gt): new $alu
  creating $alu model for $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:427$3018 ($eq): merged with $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017.
  creating $alu model for $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1236$7545 ($eq): merged with $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7542.
  creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:215$1334: $auto$alumacc.cc:485:replace_alu$18039
  creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:175$1323: $auto$alumacc.cc:485:replace_alu$18050
  creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$gt$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:169$1322: $auto$alumacc.cc:485:replace_alu$18055
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$le$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2493$1092: $auto$alumacc.cc:485:replace_alu$18060
  creating $alu cell for $flatten\housekeeping.\U1.$lt$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:425$3017, $flatten\housekeeping.\U1.$eq$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:427$3018: $auto$alumacc.cc:485:replace_alu$18073
  creating $alu cell for $flatten\clocking.\divider2.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:106$238: $auto$alumacc.cc:485:replace_alu$18080
  creating $alu cell for $flatten\clocking.\divider.\odd_0.$le$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:106$238: $auto$alumacc.cc:485:replace_alu$18093
  creating $alu cell for $flatten\clocking.\divider.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256: $auto$alumacc.cc:485:replace_alu$18106
  creating $alu cell for $flatten\clocking.\divider.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235: $auto$alumacc.cc:485:replace_alu$18109
  creating $alu cell for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:114$242: $auto$alumacc.cc:485:replace_alu$18112
  creating $alu cell for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:117$243: $auto$alumacc.cc:485:replace_alu$18115
  creating $alu cell for $flatten\clocking.\divider.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:84$234: $auto$alumacc.cc:485:replace_alu$18118
  creating $alu cell for $flatten\clocking.\divider2.\even_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:191$256: $auto$alumacc.cc:485:replace_alu$18121
  creating $alu cell for $flatten\clocking.\divider2.\odd_0.$add$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:91$235: $auto$alumacc.cc:485:replace_alu$18124
  creating $alu cell for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:114$242: $auto$alumacc.cc:485:replace_alu$18127
  creating $alu cell for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:117$243: $auto$alumacc.cc:485:replace_alu$18130
  creating $alu cell for $flatten\clocking.\divider2.\odd_0.$sub$/project/openlane/mgmt_core/../../verilog/rtl/clock_div.v:84$234: $auto$alumacc.cc:485:replace_alu$18133
  creating $alu cell for $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:420$3014: $auto$alumacc.cc:485:replace_alu$18136
  creating $alu cell for $flatten\housekeeping.\U1.$add$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:463$3033: $auto$alumacc.cc:485:replace_alu$18139
  creating $alu cell for $flatten\housekeeping.\U1.$sub$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:462$3032: $auto$alumacc.cc:485:replace_alu$18142
  creating $alu cell for $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:170$1511: $auto$alumacc.cc:485:replace_alu$18145
  creating $alu cell for $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:171$1512: $auto$alumacc.cc:485:replace_alu$18148
  creating $alu cell for $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$add$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:167$1452: $auto$alumacc.cc:485:replace_alu$18151
  creating $alu cell for $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$sub$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_high.v:168$1453: $auto$alumacc.cc:485:replace_alu$18154
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$7336: $auto$alumacc.cc:485:replace_alu$18157
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1428$7368: $auto$alumacc.cc:485:replace_alu$18160
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7419: $auto$alumacc.cc:485:replace_alu$18163
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1559$7422: $auto$alumacc.cc:485:replace_alu$18166
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$7423: $auto$alumacc.cc:485:replace_alu$18169
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1801$7470: $auto$alumacc.cc:485:replace_alu$18172
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1864$7495: $auto$alumacc.cc:485:replace_alu$18175
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$6946: $auto$alumacc.cc:485:replace_alu$18178
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:906$7072: $auto$alumacc.cc:485:replace_alu$18181
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:910$7073: $auto$alumacc.cc:485:replace_alu$18184
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$lt$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1237$7546: $auto$alumacc.cc:485:replace_alu$18187
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7543: $auto$alumacc.cc:485:replace_alu$18194
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1235$7542, $flatten\soc.\cpu.\picorv32_core.$lt$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1238$7547, $flatten\soc.\cpu.\picorv32_core.$eq$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1236$7545: $auto$alumacc.cc:485:replace_alu$18197
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1421$7366: $auto$alumacc.cc:485:replace_alu$18204
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1438$7373: $auto$alumacc.cc:485:replace_alu$18207
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2469$1070: $auto$alumacc.cc:485:replace_alu$18210
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1075: $auto$alumacc.cc:485:replace_alu$18213
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2488$1088: $auto$alumacc.cc:485:replace_alu$18216
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$neg$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2490$1090: $auto$alumacc.cc:485:replace_alu$18219
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2494$1093: $auto$alumacc.cc:485:replace_alu$18222
  creating $alu cell for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:716$1278: $auto$alumacc.cc:485:replace_alu$18225
  creating $alu cell for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:686$1266: $auto$alumacc.cc:485:replace_alu$18228
  creating $alu cell for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:653$1254: $auto$alumacc.cc:485:replace_alu$18231
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1005: $auto$alumacc.cc:485:replace_alu$18234
  creating $alu cell for $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:633$1247: $auto$alumacc.cc:485:replace_alu$18237
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1007: $auto$alumacc.cc:485:replace_alu$18240
  creating $alu cell for $flatten\soc.\spimemio.\spimemio.$add$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:216$1138: $auto$alumacc.cc:485:replace_alu$18243
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1009: $auto$alumacc.cc:485:replace_alu$18246
  creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$sub$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:217$1336: $auto$alumacc.cc:485:replace_alu$18249
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1011: $auto$alumacc.cc:485:replace_alu$18252
  creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:197$1328: $auto$alumacc.cc:485:replace_alu$18255
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1013: $auto$alumacc.cc:485:replace_alu$18258
  creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:184$1325: $auto$alumacc.cc:485:replace_alu$18261
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1015: $auto$alumacc.cc:485:replace_alu$18264
  creating $alu cell for $flatten\soc.\simpleuart.\simpleuart.$add$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:159$1318: $auto$alumacc.cc:485:replace_alu$18267
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1017: $auto$alumacc.cc:485:replace_alu$18270
  creating $alu cell for $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:329$1404: $auto$alumacc.cc:485:replace_alu$18273
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2260$1019: $auto$alumacc.cc:485:replace_alu$18276
  creating $alu cell for $flatten\soc.\simple_spi_master_inst.\spi_master.$add$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:304$1397: $auto$alumacc.cc:485:replace_alu$18279
  creating $alu cell for $flatten\soc.\mprj_ctrl.\mprj_ctrl.$sub$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:323$6395: $auto$alumacc.cc:485:replace_alu$18282
  creating $alu cell for $flatten\soc.\mprj_ctrl.\mprj_ctrl.$add$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:337$6403: $auto$alumacc.cc:485:replace_alu$18285
  creating $alu cell for $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$sub$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2294$1027: $auto$alumacc.cc:485:replace_alu$18288
  created 66 $alu and 8 $macc cells.

13.14. Executing SHARE pass (SAT-based resource sharing).
Found 4 cells in module mgmt_core that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:851$2938 ($memrd):
    Found 1 activation_patterns using ctrl signal { $auto$opt_reduce.cc:134:opt_mux$15136 \soc.cpu.picorv32_core.is_lui_auipc_jal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1386$7350_Y $flatten\soc.\cpu.\picorv32_core.$procmux$8331_CTRL }.
    Found 1 candidates: $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:850$2937
    Analyzing resource sharing with $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:850$2937 ($memrd):
      Found 1 activation_patterns using ctrl signal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1385$7348_Y.
      Activation pattern for cell $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:851$2938: { $auto$opt_reduce.cc:134:opt_mux$15136 \soc.cpu.picorv32_core.is_lui_auipc_jal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1386$7350_Y $flatten\soc.\cpu.\picorv32_core.$procmux$8331_CTRL } = 4'0010
      Activation pattern for cell $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:850$2937: $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1385$7348_Y = 1'1
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_timer vs. \soc.cpu.picorv32_core.instr_maskirq
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_timer vs. \soc.cpu.picorv32_core.instr_retirq
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_maskirq vs. \soc.cpu.picorv32_core.instr_retirq
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_trap vs. \soc.cpu.picorv32_core.instr_timer
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_trap vs. \soc.cpu.picorv32_core.instr_maskirq
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_trap vs. \soc.cpu.picorv32_core.instr_retirq
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstrh vs. \soc.cpu.picorv32_core.instr_rdinstr
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstrh vs. \soc.cpu.picorv32_core.instr_rdcycleh
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstrh vs. \soc.cpu.picorv32_core.instr_rdcycle
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstr vs. \soc.cpu.picorv32_core.instr_rdcycleh
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdinstr vs. \soc.cpu.picorv32_core.instr_rdcycle
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_rdcycleh vs. \soc.cpu.picorv32_core.instr_rdcycle
      Adding exclusive control bits: $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1691$7447_Y vs. \soc.cpu.picorv32_core.instr_trap
      Adding exclusive control bits: $flatten\soc.\cpu.\picorv32_core.$procmux$8331_CTRL vs. $auto$opt_reduce.cc:134:opt_mux$15136
      Adding exclusive control bits: $flatten\soc.\cpu.\picorv32_core.$procmux$8331_CTRL vs. \soc.cpu.picorv32_core.is_lui_auipc_jal
      Adding exclusive control bits: \soc.cpu.picorv32_core.is_lui_auipc_jal vs. $auto$opt_reduce.cc:134:opt_mux$15136
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bgeu vs. \soc.cpu.picorv32_core.instr_bge
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bgeu vs. \soc.cpu.picorv32_core.instr_bne
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bgeu vs. \soc.cpu.picorv32_core.instr_beq
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bge vs. \soc.cpu.picorv32_core.instr_bne
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bge vs. \soc.cpu.picorv32_core.instr_beq
      Adding exclusive control bits: \soc.cpu.picorv32_core.instr_bne vs. \soc.cpu.picorv32_core.instr_beq
      Size of SAT problem: 7 cells, 133 variables, 287 clauses
      According to the SAT solver this pair of cells can not be shared.
      Model from SAT solver: { $auto$opt_reduce.cc:134:opt_mux$15136 \soc.cpu.picorv32_core.is_lui_auipc_jal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1385$7348_Y $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1386$7350_Y $flatten\soc.\cpu.\picorv32_core.$procmux$8331_CTRL } = 5'00110
  Analyzing resource sharing options for $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:850$2937 ($memrd):
    Found 1 activation_patterns using ctrl signal $flatten\soc.\cpu.\picorv32_core.$reduce_bool$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1385$7348_Y.
    No candidates found.
  Analyzing resource sharing options for $flatten\soc.\cpu.\picorv32_core.$sshr$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1240$7551 ($sshr):
    Found 1 activation_patterns using ctrl signal $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1277$7326_Y.
    No candidates found.
  Analyzing resource sharing options for $flatten\soc.\cpu.\picorv32_core.$shl$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1239$7548 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\soc.\cpu.\picorv32_core.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1275$7322_Y.
    No candidates found.

13.15. Executing OPT pass (performing simple optimizations).

13.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~9 debug messages>

13.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

13.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~332 debug messages>

13.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    New ctrl vector for $pmux cell $flatten\soc.\cpu.$procmux$12440: { \soc.cpu.state [2] $auto$opt_reduce.cc:134:opt_mux$18292 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10055: { $flatten\soc.\cpu.\picorv32_core.$logic_not$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:379$6926_Y $flatten\soc.\cpu.\picorv32_core.$procmux$10018_CMP $auto$opt_reduce.cc:134:opt_mux$18294 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8537: $auto$opt_reduce.cc:134:opt_mux$18296
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8824: { $auto$opt_reduce.cc:134:opt_mux$15126 $auto$opt_reduce.cc:134:opt_mux$18298 $auto$opt_reduce.cc:134:opt_mux$15128 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9030: { \soc.cpu.picorv32_core.cpu_state [2] $auto$opt_reduce.cc:134:opt_mux$18300 }
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13839: { $auto$opt_reduce.cc:134:opt_mux$18302 \soc.spimemio.spimemio.state [8] \soc.spimemio.spimemio.state [5] \soc.spimemio.spimemio.state [11] \soc.spimemio.spimemio.state [3] }
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13546: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$18304 }
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13556: { $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13424_CMP $auto$opt_reduce.cc:134:opt_mux$18306 }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$18295: { \soc.cpu.picorv32_core.instr_rdcycle \soc.cpu.picorv32_core.instr_rdcycleh \soc.cpu.picorv32_core.instr_rdinstr \soc.cpu.picorv32_core.instr_rdinstrh \soc.cpu.picorv32_core.instr_retirq \soc.cpu.picorv32_core.instr_maskirq \soc.cpu.picorv32_core.instr_timer \soc.cpu.picorv32_core.instr_trap }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$18301: { \soc.spimemio.spimemio.state [12] \soc.spimemio.spimemio.state [9] \soc.spimemio.spimemio.state [6] \soc.spimemio.spimemio.state [4] \soc.spimemio.spimemio.state [2:0] }
  Optimizing cells in module \mgmt_core.
Performed a total of 10 changes.

13.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

13.15.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$opt_dff.cc:764:run$17281 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10113_Y, Q = \soc.cpu.picorv32_core.mem_valid, rval = 1'0).
Adding SRST signal on $auto$opt_dff.cc:764:run$17257 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$10055_Y, Q = \soc.cpu.picorv32_core.mem_state, rval = 2'00).
Adding SRST signal on $auto$opt_dff.cc:764:run$17199 ($dffe) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.\pcpi_div.$shl$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2470$1078_Y [62], Q = \soc.cpu.picorv32_core.pcpi_div.divisor [62], rval = 1'0).
Adding SRST signal on $auto$opt_dff.cc:764:run$17150 ($dffe) from module mgmt_core (D = $auto$wreduce.cc:454:run$17971 [6], Q = \soc.cpu.picorv32_core.pcpi_mul.mul_counter [6], rval = 1'0).
Adding SRST signal on $auto$opt_dff.cc:764:run$16559 ($dffe) from module mgmt_core (D = $flatten\soc.\mprj_ctrl.\mprj_ctrl.$4$mem2reg_rd$\io_ctrl$/project/openlane/mgmt_core/../../verilog/rtl/mprj_ctrl.v:325$6359_DATA[12:0]$6397 [0], Q = \soc.mprj_ctrl.mprj_ctrl.serial_data_staging [0], rval = 1'0).

13.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 17 unused cells and 38 unused wires.
<suppressed ~19 debug messages>

13.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

13.15.9. Rerunning OPT passes. (Maybe there is more to do..)

13.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~334 debug messages>

13.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
Performed a total of 0 changes.

13.15.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

13.15.13. Executing OPT_DFF pass (perform DFF optimizations).

13.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

13.15.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

13.15.16. Finished OPT passes. (There is nothing left to do.)

13.16. Executing MEMORY pass.

13.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

13.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
Checking cell `$flatten\soc.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:0$2939' in module `\mgmt_core': merged $dff to cell.
Checking cell `$flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:850$2937' in module `\mgmt_core': merged address $dff to cell.
Checking cell `$flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:851$2938' in module `\mgmt_core': merged address $dff to cell.

13.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 3 unused cells and 3 unused wires.
<suppressed ~4 debug messages>

13.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

13.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

13.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).
Collecting $memrd, $memwr and $meminit for memory `\soc.cpu.picorv32_core.cpuregs.regs' in module `\mgmt_core':
  $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memwr$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:0$2939 ($memwr)
  $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:851$2938 ($memrd)
  $flatten\soc.\cpu.\picorv32_core.\cpuregs.$memrd$\regs$/project/openlane/mgmt_core/../../verilog/rtl/mgmt_soc.v:850$2937 ($memrd)

13.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

13.18. Executing OPT pass (performing simple optimizations).

13.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~370 debug messages>

13.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

13.18.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $auto$opt_dff.cc:764:run$16362 ($dffe) from module mgmt_core (D = $auto$wreduce.cc:454:run$18015 [1:0], Q = \soc.spimemio.spimemio.rd_addr [1:0]).

13.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 19 unused cells and 111 unused wires.
<suppressed ~23 debug messages>

13.18.5. Rerunning OPT passes. (Removed registers in this run.)

13.18.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~2 debug messages>

13.18.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

13.18.8. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 1-bit at position 4 on $flatten\soc.\cpu.\picorv32_core.$procdff$14667 ($dff) from module mgmt_core.
Adding SRST signal on $flatten\soc.\cpu.\picorv32_core.$procdff$14667 ($dff) from module mgmt_core (D = { $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [31:12] $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [8] $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [5] $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [3] $flatten\soc.\cpu.\picorv32_core.$2\next_irq_pending[31:0] [1] }, Q = { \soc.cpu.picorv32_core.irq_pending [31:12] \soc.cpu.picorv32_core.irq_pending [8] \soc.cpu.picorv32_core.irq_pending [5] \soc.cpu.picorv32_core.irq_pending [3] \soc.cpu.picorv32_core.irq_pending [1] }, rval = 24'000000000000000000000000).

13.18.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

13.18.10. Rerunning OPT passes. (Removed registers in this run.)

13.18.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~21 debug messages>

13.18.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

13.18.13. Executing OPT_DFF pass (perform DFF optimizations).

13.18.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 11 unused wires.
<suppressed ~1 debug messages>

13.18.15. Finished fast OPT passes.

13.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
Mapping memory cell \soc.cpu.picorv32_core.cpuregs.regs in module \mgmt_core:
  created 32 $dff cells and 0 static cells of width 32.
  read interface: 2 $dff and 62 $mux cells.
  write interface: 32 write mux blocks.

13.20. Executing OPT pass (performing simple optimizations).

13.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~11 debug messages>

13.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

13.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~282 debug messages>

13.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    New input vector for $reduce_and cell $auto$opt_dff.cc:243:make_patterns_logic$18374: { $auto$opt_dff.cc:217:make_patterns_logic$18371 $flatten\soc.\spimemio.\spimemio.$logic_and$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:386$1224_Y $auto$rtlil.cc:2121:Not$16339 }
    Consolidated identical input bits for $mux cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$2976:
      Old ports: A={ 3'000 $auto$wreduce.cc:454:run$17952 [4:0] }, B={ 2'00 \housekeeping.pll90_sel \housekeeping.pll_sel }, Y=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$2976_Y
      New ports: A={ 1'0 $auto$wreduce.cc:454:run$17952 [4:0] }, B={ \housekeeping.pll90_sel \housekeeping.pll_sel }, Y=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$2976_Y [5:0]
      New connections: $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$2976_Y [7:6] = 2'00
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10207:
      Old ports: A={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, B={ \soc.cpu.picorv32_core.mem_rdata_latched [6] 4'0000 }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10207_Y
      New ports: A={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, B={ \soc.cpu.picorv32_core.mem_rdata_latched [6] 1'0 }, Y={ $flatten\soc.\cpu.\picorv32_core.$procmux$10207_Y [4] $flatten\soc.\cpu.\picorv32_core.$procmux$10207_Y [0] }
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10207_Y [3:1] = { $flatten\soc.\cpu.\picorv32_core.$procmux$10207_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$10207_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$10207_Y [0] }
    Consolidated identical input bits for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$10374:
      Old ports: A=\soc.cpu.picorv32_core.reg_op2, B={ \soc.cpu.picorv32_core.reg_op2 [15:0] \soc.cpu.picorv32_core.reg_op2 [15:0] \soc.cpu.picorv32_core.reg_op2 [7:0] \soc.cpu.picorv32_core.reg_op2 [7:0] \soc.cpu.picorv32_core.reg_op2 [7:0] \soc.cpu.picorv32_core.reg_op2 [7:0] }, Y=\soc.cpu.picorv32_core.mem_la_wdata
      New ports: A=\soc.cpu.picorv32_core.reg_op2 [31:8], B={ \soc.cpu.picorv32_core.reg_op2 [15:0] \soc.cpu.picorv32_core.reg_op2 [15:0] \soc.cpu.picorv32_core.reg_op2 [7:0] \soc.cpu.picorv32_core.reg_op2 [7:0] }, Y=\soc.cpu.picorv32_core.mem_la_wdata [31:8]
      New connections: \soc.cpu.picorv32_core.mem_la_wdata [7:0] = \soc.cpu.picorv32_core.reg_op2 [7:0]
    Consolidated identical input bits for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8259:
      Old ports: A=\soc.cpu.picorv32_core.mem_rdata_word, B={ \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15:0] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7:0] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$8259_Y
      New ports: A=\soc.cpu.picorv32_core.mem_rdata_word [31:8], B={ \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15] \soc.cpu.picorv32_core.mem_rdata_word [15:7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] \soc.cpu.picorv32_core.mem_rdata_word [7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$8259_Y [31:8]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$8259_Y [7:0] = \soc.cpu.picorv32_core.mem_rdata_word [7:0]
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$8514: { \soc.cpu.picorv32_core.cpu_state [3] $auto$opt_reduce.cc:134:opt_mux$18885 }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9282: { $flatten\soc.\cpu.\picorv32_core.$procmux$10165_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10147_CMP }
    New ctrl vector for $pmux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9284: { $flatten\soc.\cpu.\picorv32_core.$procmux$10145_CMP $flatten\soc.\cpu.\picorv32_core.$procmux$10162_CMP }
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9334:
      Old ports: A={ \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] \soc.cpu.picorv32_core.mem_rdata_latched [31] }, B={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y
      New ports: A=\soc.cpu.picorv32_core.mem_rdata_latched [31], B=\soc.cpu.picorv32_core.mem_rdata_latched [12], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [11:1] = { $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] $flatten\soc.\cpu.\picorv32_core.$procmux$9334_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9362:
      Old ports: A=2'00, B=2'10, Y=$auto$wreduce.cc:454:run$17959 [1:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$17959 [1]
      New connections: $auto$wreduce.cc:454:run$17959 [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9540:
      Old ports: A=5'00000, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9540_Y
      New ports: A=4'0000, B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9540_Y [3:0]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9540_Y [4] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9547:
      Old ports: A=\soc.cpu.picorv32_core.mem_rdata_latched [19:12], B={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9547_Y
      New ports: A=\soc.cpu.picorv32_core.mem_rdata_latched [19:13], B={ \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] \soc.cpu.picorv32_core.mem_rdata_latched [12] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9547_Y [7:1]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9547_Y [0] = \soc.cpu.picorv32_core.mem_rdata_latched [12]
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9572:
      Old ports: A=5'00000, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9572_Y
      New ports: A=4'0000, B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9572_Y [3:0]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9572_Y [4] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9590:
      Old ports: A=5'00000, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9590_Y
      New ports: A=4'0000, B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [4:2] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9590_Y [3:0]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9590_Y [4] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1312$7335:
      Old ports: A=3'100, B=3'010, Y=$auto$wreduce.cc:454:run$17961 [2:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:454:run$17961 [2:1]
      New connections: $auto$wreduce.cc:454:run$17961 [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$7411:
      Old ports: A=2'00, B=2'10, Y=$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$7411_Y
      New ports: A=1'0, B=1'1, Y=$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$7411_Y [1]
      New connections: $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1536$7411_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1541$7413:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:454:run$17962 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:454:run$17962 [2] $auto$wreduce.cc:454:run$17962 [0] }
      New connections: $auto$wreduce.cc:454:run$17962 [1] = $auto$wreduce.cc:454:run$17962 [0]
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7418:
      Old ports: A=3'100, B=3'010, Y=$auto$wreduce.cc:454:run$17963 [2:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:454:run$17963 [2:1]
      New connections: $auto$wreduce.cc:454:run$17963 [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$6947:
      Old ports: A={ \soc.cpu.picorv32_core.reg_op1 [31:2] 2'00 }, B={ $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$6946_Y 2'00 }, Y=\soc.cpu.picorv32_core.mem_la_addr
      New ports: A=\soc.cpu.picorv32_core.reg_op1 [31:2], B=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:382$6946_Y, Y=\soc.cpu.picorv32_core.mem_la_addr [31:2]
      New connections: \soc.cpu.picorv32_core.mem_la_addr [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962:
      Old ports: A=4'0011, B=4'1100, Y=$flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962_Y
      New ports: A=2'01, B=2'10, Y={ $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962_Y [2] $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962_Y [0] }
      New connections: { $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962_Y [3] $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962_Y [1] } = { $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962_Y [2] $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:411$6962_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:491$6978:
      Old ports: A=6'000000, B=6'100000, Y=$auto$wreduce.cc:454:run$17964 [5:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$17964 [5]
      New connections: $auto$wreduce.cc:454:run$17964 [4:0] = 5'00000
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:617$7022:
      Old ports: A=2'11, B=2'00, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10061_Y
      New ports: A=1'1, B=1'0, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$10061_Y [0]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$10061_Y [1] = $flatten\soc.\cpu.\picorv32_core.$procmux$10061_Y [0]
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141:
      Old ports: A={ 32'00000000000000000000000000000000 \soc.cpu.picorv32_core.reg_op2 }, B={ \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 [31] \soc.cpu.picorv32_core.reg_op2 }, Y=$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y
      New ports: A=1'0, B=\soc.cpu.picorv32_core.reg_op2 [31], Y=$flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32]
      New connections: { $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [63:33] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [31:0] } = { $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14141_Y [32] \soc.cpu.picorv32_core.reg_op2 }
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$procmux$14150:
      Old ports: A={ 31'0000000000000000000000000000000 \soc.cpu.picorv32_core.reg_op1 }, B={ \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 [31] \soc.cpu.picorv32_core.reg_op1 }, Y=$auto$wreduce.cc:454:run$17969 [62:0]
      New ports: A=1'0, B=\soc.cpu.picorv32_core.reg_op1 [31], Y=$auto$wreduce.cc:454:run$17969 [32]
      New connections: { $auto$wreduce.cc:454:run$17969 [62:33] $auto$wreduce.cc:454:run$17969 [31:0] } = { $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] $auto$wreduce.cc:454:run$17969 [32] \soc.cpu.picorv32_core.reg_op1 }
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.\pcpi_mul.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:2286$1025:
      Old ports: A=6'011110, B=6'111110, Y=$auto$wreduce.cc:454:run$17972 [5:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$17972 [5]
      New connections: $auto$wreduce.cc:454:run$17972 [4:0] = 5'11110
    Consolidated identical input bits for $mux cell $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11187:
      Old ports: A={ 1'0 \soc.gpio_wb.gpio_ctrl.gpio_pd }, B={ 1'0 \soc.gpio_wb.gpio_ctrl.gpio_pu }, Y=$auto$wreduce.cc:454:run$17974 [1:0]
      New ports: A=\soc.gpio_wb.gpio_ctrl.gpio_pd, B=\soc.gpio_wb.gpio_ctrl.gpio_pu, Y=$auto$wreduce.cc:454:run$17974 [0]
      New connections: $auto$wreduce.cc:454:run$17974 [1] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11710:
      Old ports: A=2'01, B=2'11, Y=$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11710_Y
      New ports: A=1'0, B=1'1, Y=$flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11710_Y [1]
      New connections: $flatten\soc.\mprj_ctrl.\mprj_ctrl.$procmux$11710_Y [0] = 1'1
    Consolidated identical input bits for $mux cell $flatten\soc.\simple_spi_master_inst.\spi_master.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:207$1370:
      Old ports: A=32'11111111111111111111111111111111, B={ 24'000000000000000000000000 \soc.simple_spi_master_inst.spi_master.rreg }, Y=\soc.simple_spi_master_inst.simple_spi_master_reg_dat_do
      New ports: A=9'111111111, B={ 1'0 \soc.simple_spi_master_inst.spi_master.rreg }, Y=\soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8:0]
      New connections: \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [31:9] = { \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] }
    Consolidated identical input bits for $mux cell $flatten\soc.\simpleuart.\simpleuart.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simpleuart.v:136$1313:
      Old ports: A=32'11111111111111111111111111111111, B={ 24'000000000000000000000000 \soc.simpleuart.simpleuart.recv_buf_data }, Y=\soc.simpleuart.simpleuart_reg_dat_do
      New ports: A=9'111111111, B={ 1'0 \soc.simpleuart.simpleuart.recv_buf_data }, Y=\soc.simpleuart.simpleuart_reg_dat_do [8:0]
      New connections: \soc.simpleuart.simpleuart_reg_dat_do [31:9] = { \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] \soc.simpleuart.simpleuart_reg_dat_do [8] }
    Consolidated identical input bits for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13839:
      Old ports: A=4'0000, B=16'0001001000110100, Y=$flatten\soc.\spimemio.\spimemio.$procmux$13839_Y
      New ports: A=3'000, B=12'001010011100, Y=$flatten\soc.\spimemio.\spimemio.$procmux$13839_Y [2:0]
      New connections: $flatten\soc.\spimemio.\spimemio.$procmux$13839_Y [3] = 1'0
    Consolidated identical input bits for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13870:
      Old ports: A=8'11101101, B=24'111010111011101100000011, Y=$flatten\soc.\spimemio.\spimemio.$procmux$13870_Y
      New ports: A=5'10110, B=15'101010110100001, Y={ $flatten\soc.\spimemio.\spimemio.$procmux$13870_Y [6] $flatten\soc.\spimemio.\spimemio.$procmux$13870_Y [4:1] }
      New connections: { $flatten\soc.\spimemio.\spimemio.$procmux$13870_Y [7] $flatten\soc.\spimemio.\spimemio.$procmux$13870_Y [5] $flatten\soc.\spimemio.\spimemio.$procmux$13870_Y [0] } = { $flatten\soc.\spimemio.\spimemio.$procmux$13870_Y [3] $flatten\soc.\spimemio.\spimemio.$procmux$13870_Y [3] 1'1 }
    Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:478$1232:
      Old ports: A=7'1111111, B=7'0100101, Y=$auto$wreduce.cc:454:run$18016 [6:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:454:run$18016 [1]
      New connections: { $auto$wreduce.cc:454:run$18016 [6:2] $auto$wreduce.cc:454:run$18016 [0] } = { $auto$wreduce.cc:454:run$18016 [1] 1'1 $auto$wreduce.cc:454:run$18016 [1] $auto$wreduce.cc:454:run$18016 [1] 2'11 }
    Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13417:
      Old ports: A=\soc.spimemio.spimemio.xfer.count, B={ $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:686$1266_Y [3:1] \soc.spimemio.spimemio.xfer.count [0] }, Y=$flatten\soc.\spimemio.\spimemio.\xfer.$5\next_count[3:0]
      New ports: A=\soc.spimemio.spimemio.xfer.count [3:1], B=$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:686$1266_Y [3:1], Y=$flatten\soc.\spimemio.\spimemio.\xfer.$5\next_count[3:0] [3:1]
      New connections: $flatten\soc.\spimemio.\spimemio.\xfer.$5\next_count[3:0] [0] = \soc.spimemio.spimemio.xfer.count [0]
    Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13458:
      Old ports: A=\soc.spimemio.spimemio.xfer.count, B={ $flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:653$1254_Y [3:2] \soc.spimemio.spimemio.xfer.count [1:0] }, Y=$flatten\soc.\spimemio.\spimemio.\xfer.$4\next_count[3:0]
      New ports: A=\soc.spimemio.spimemio.xfer.count [3:2], B=$flatten\soc.\spimemio.\spimemio.\xfer.$sub$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:653$1254_Y [3:2], Y=$flatten\soc.\spimemio.\spimemio.\xfer.$4\next_count[3:0] [3:2]
      New connections: $flatten\soc.\spimemio.\spimemio.\xfer.$4\next_count[3:0] [1:0] = \soc.spimemio.spimemio.xfer.count [1:0]
    Consolidated identical input bits for $pmux cell $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13556:
      Old ports: A={ \soc.spimemio.spimemio.xfer.obuffer [5:0] 2'00 }, B={ \soc.spimemio.spimemio.xfer.obuffer [6:0] 1'0 \soc.spimemio.spimemio.xfer.obuffer [3:0] 4'0000 }, Y=\soc.spimemio.spimemio.xfer.next_obuffer
      New ports: A={ \soc.spimemio.spimemio.xfer.obuffer [5:0] 1'0 }, B={ \soc.spimemio.spimemio.xfer.obuffer [6:0] \soc.spimemio.spimemio.xfer.obuffer [3:0] 3'000 }, Y=\soc.spimemio.spimemio.xfer.next_obuffer [7:1]
      New connections: \soc.spimemio.spimemio.xfer.next_obuffer [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\sysctrl.\sysctrl.$procmux$11166:
      Old ports: A={ 2'00 \soc.sysctrl.sysctrl.irq_8_inputsrc \soc.sysctrl.sysctrl.irq_7_inputsrc }, B={ 3'000 \soc.sysctrl.sysctrl.trap_output_dest }, Y=$auto$wreduce.cc:454:run$18020 [3:0]
      New ports: A={ \soc.sysctrl.sysctrl.irq_8_inputsrc \soc.sysctrl.sysctrl.irq_7_inputsrc }, B={ 1'0 \soc.sysctrl.sysctrl.trap_output_dest }, Y=$auto$wreduce.cc:454:run$18020 [1:0]
      New connections: $auto$wreduce.cc:454:run$18020 [3:2] = 2'00
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$2977:
      Old ports: A=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$2976_Y, B={ 6'000000 \housekeeping.pll_trim [25:24] }, Y=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$2977_Y
      New ports: A=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:192$2976_Y [5:0], B={ 4'0000 \housekeeping.pll_trim [25:24] }, Y=$flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$2977_Y [5:0]
      New connections: $flatten\housekeeping.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/housekeeping_spi.v:191$2977_Y [7:6] = 2'00
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9574:
      Old ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9572_Y, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9574_Y
      New ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9572_Y [3:0], B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9574_Y [3:0]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9574_Y [4] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\gpio_wb.\gpio_ctrl.$procmux$11190:
      Old ports: A=$auto$wreduce.cc:454:run$17974 [1:0], B={ 1'0 \soc.gpio_wb.gpio_ctrl.gpio_oeb }, Y=$auto$wreduce.cc:454:run$17975 [1:0]
      New ports: A=$auto$wreduce.cc:454:run$17974 [0], B=\soc.gpio_wb.gpio_ctrl.gpio_oeb, Y=$auto$wreduce.cc:454:run$17975 [0]
      New connections: $auto$wreduce.cc:454:run$17975 [1] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc.\simple_spi_master_inst.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/simple_spi_master.v:110$4725:
      Old ports: A=\soc.simple_spi_master_inst.simple_spi_master_reg_dat_do, B={ 16'0000000000000000 \soc.simple_spi_master_inst.spi_master.hkconn \soc.simple_spi_master_inst.spi_master.irqena \soc.simple_spi_master_inst.spi_master.enable \soc.simple_spi_master_inst.spi_master.stream \soc.simple_spi_master_inst.spi_master.mode \soc.simple_spi_master_inst.spi_master.invsck \soc.simple_spi_master_inst.spi_master.invcsb \soc.simple_spi_master_inst.spi_master.mlb \soc.simple_spi_master_inst.spi_master.prescaler }, Y=\soc.simple_spi_master_inst.wb_dat_o
      New ports: A={ \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8] \soc.simple_spi_master_inst.simple_spi_master_reg_dat_do [8:0] }, B={ 1'0 \soc.simple_spi_master_inst.spi_master.hkconn \soc.simple_spi_master_inst.spi_master.irqena \soc.simple_spi_master_inst.spi_master.enable \soc.simple_spi_master_inst.spi_master.stream \soc.simple_spi_master_inst.spi_master.mode \soc.simple_spi_master_inst.spi_master.invsck \soc.simple_spi_master_inst.spi_master.invcsb \soc.simple_spi_master_inst.spi_master.mlb \soc.simple_spi_master_inst.spi_master.prescaler }, Y=\soc.simple_spi_master_inst.wb_dat_o [16:0]
      New connections: \soc.simple_spi_master_inst.wb_dat_o [31:17] = { \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] \soc.simple_spi_master_inst.wb_dat_o [16] }
    Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.$procmux$13860:
      Old ports: A={ 1'1 $auto$wreduce.cc:454:run$18016 [6:0] }, B={ 4'0000 \soc.spimemio.spimemio.config_dummy }, Y=$flatten\soc.\spimemio.\spimemio.$procmux$13860_Y
      New ports: A={ 1'1 $auto$wreduce.cc:454:run$18016 [1] $auto$wreduce.cc:454:run$18016 [1] 1'1 $auto$wreduce.cc:454:run$18016 [1] 1'1 }, B={ 2'00 \soc.spimemio.spimemio.config_dummy }, Y=$flatten\soc.\spimemio.\spimemio.$procmux$13860_Y [5:0]
      New connections: $flatten\soc.\spimemio.\spimemio.$procmux$13860_Y [7:6] = $flatten\soc.\spimemio.\spimemio.$procmux$13860_Y [5:4]
    Consolidated identical input bits for $mux cell $flatten\soc.\sysctrl.\sysctrl.$procmux$11169:
      Old ports: A=$auto$wreduce.cc:454:run$18020 [3:0], B={ 2'00 \soc.sysctrl.sysctrl.clk2_output_dest \soc.sysctrl.sysctrl.clk1_output_dest }, Y=$auto$wreduce.cc:454:run$18021 [3:0]
      New ports: A=$auto$wreduce.cc:454:run$18020 [1:0], B={ \soc.sysctrl.sysctrl.clk2_output_dest \soc.sysctrl.sysctrl.clk1_output_dest }, Y=$auto$wreduce.cc:454:run$18021 [1:0]
      New connections: $auto$wreduce.cc:454:run$18021 [3:2] = 2'00
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9576:
      Old ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9574_Y, B={ 2'01 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9576_Y
      New ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9574_Y [3:0], B={ 1'1 \soc.cpu.picorv32_core.mem_rdata_latched [9:7] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9576_Y [3:0]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9576_Y [4] = 1'0
  Optimizing cells in module \mgmt_core.
Performed a total of 43 changes.

13.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
<suppressed ~54 debug messages>
Removed a total of 18 cells.

13.20.6. Executing OPT_SHARE pass.
    Found cells that share an operand and can be merged by moving the $mux $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12696 in front of them:
        $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12694
        $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12669

    Found cells that share an operand and can be merged by moving the $mux $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12723 in front of them:
        $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12721
        $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$procmux$12711

    Found cells that share an operand and can be merged by moving the $mux $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$13009 in front of them:
        $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$13007
        $flatten\soc.\counter_timer_1.\counter_timer_high_inst.$procmux$12983

    Found cells that share an operand and can be merged by moving the $pmux $flatten\soc.\spimemio.\spimemio.$procmux$13746 in front of them:
        $flatten\soc.\spimemio.\spimemio.$procmux$13744
        $flatten\soc.\spimemio.\spimemio.$procmux$13768

13.20.7. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$opt_dff.cc:764:run$17150 ($dffe) from module mgmt_core (D = $auto$wreduce.cc:454:run$17971 [4:0], Q = \soc.cpu.picorv32_core.pcpi_mul.mul_counter [4:0], rval = 5'11110).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$17377 ($sdff) from module mgmt_core.

13.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 2 unused cells and 129 unused wires.
<suppressed ~3 debug messages>

13.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~18 debug messages>

13.20.10. Rerunning OPT passes. (Maybe there is more to do..)

13.20.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~280 debug messages>

13.20.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9078:
      Old ports: A=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7419_Y, B={ $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$7423_Y [31:1] $auto$alumacc.cc:501:replace_alu$18170 [0] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9078_Y
      New ports: A=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7419_Y [31:1], B=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1564$7423_Y [31:1], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9078_Y [31:1]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9078_Y [0] = $auto$alumacc.cc:501:replace_alu$18170 [0]
    New ctrl vector for $pmux cell $flatten\soc.\spimemio.\spimemio.$procmux$13746: { $auto$opt_reduce.cc:134:opt_mux$15196 $auto$opt_reduce.cc:134:opt_mux$18900 }
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9080:
      Old ports: A={ $flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$18170 [0] }, B=$flatten\soc.\cpu.\picorv32_core.$procmux$9078_Y, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9080_Y
      New ports: A=$flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], B=$flatten\soc.\cpu.\picorv32_core.$procmux$9078_Y [31:1], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9080_Y [31:1]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9080_Y [0] = $auto$alumacc.cc:501:replace_alu$18170 [0]
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9086:
      Old ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9080_Y, B={ $flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7419_Y [31:1] $auto$alumacc.cc:501:replace_alu$18170 [0] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9086_Y
      New ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9080_Y [31:1], B=$flatten\soc.\cpu.\picorv32_core.$add$/project/openlane/mgmt_core/../../verilog/rtl/picorv32.v:1547$7419_Y [31:1], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9086_Y [31:1]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9086_Y [0] = $auto$alumacc.cc:501:replace_alu$18170 [0]
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $flatten\soc.\cpu.\picorv32_core.$procmux$9089:
      Old ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9086_Y, B={ $flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1] $auto$alumacc.cc:501:replace_alu$18170 [0] }, Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9089_Y
      New ports: A=$flatten\soc.\cpu.\picorv32_core.$procmux$9086_Y [31:1], B=$flatten\soc.\cpu.\picorv32_core.$3\current_pc[31:0] [31:1], Y=$flatten\soc.\cpu.\picorv32_core.$procmux$9089_Y [31:1]
      New connections: $flatten\soc.\cpu.\picorv32_core.$procmux$9089_Y [0] = $auto$alumacc.cc:501:replace_alu$18170 [0]
  Optimizing cells in module \mgmt_core.
Performed a total of 5 changes.

13.20.13. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

13.20.14. Executing OPT_SHARE pass.
    Found cells that share an operand and can be merged by moving the $mux $auto$opt_share.cc:241:merge_operators$18890 in front of them:
        $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:214$1531
        $flatten\soc.\counter_timer_0.\counter_timer_low_inst.$eq$/project/openlane/mgmt_core/../../verilog/rtl/counter_timer_low.v:262$1544

13.20.15. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[9]$18404 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[9]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[8]$18402 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[8]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[7]$18400 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[7]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[6]$18398 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[6]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[5]$18396 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[5]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[4]$18394 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[4]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[3]$18392 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[3]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[31]$18448 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[31]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[30]$18446 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[30]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[2]$18390 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[2]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[29]$18444 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[29]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[28]$18442 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[28]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[27]$18440 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[27]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[26]$18438 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[26]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[25]$18436 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[25]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[24]$18434 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[24]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[23]$18432 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[23]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[22]$18430 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[22]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[21]$18428 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[21]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[20]$18426 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[20]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[1]$18388 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[1]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[19]$18424 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[19]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[18]$18422 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[18]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[17]$18420 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[17]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[16]$18418 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[16]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[15]$18416 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[15]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[14]$18414 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[14]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[13]$18412 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[13]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[12]$18410 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[12]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[11]$18408 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[11]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[10]$18406 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[10]).
Adding EN signal on $memory\soc.cpu.picorv32_core.cpuregs.regs[0]$18386 ($dff) from module mgmt_core (D = \soc.cpu.picorv32_core.cpuregs.wdata, Q = \soc.cpu.picorv32_core.cpuregs.regs[0]).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$17268 ($dffe) from module mgmt_core.
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$17268 ($dffe) from module mgmt_core.
Adding SRST signal on $auto$opt_dff.cc:764:run$17110 ($dffe) from module mgmt_core (D = \soc.gpio_wb.gpio_ctrl.gpio, Q = \soc.gpio_wb.gpio_ctrl.iomem_rdata [1], rval = 1'0).
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$16395 ($sdffe) from module mgmt_core.
Adding SRST signal on $auto$opt_dff.cc:764:run$16304 ($dffe) from module mgmt_core (D = \soc.spimemio.spimemio.din_data [0], Q = \soc.spimemio.spimemio.xfer.obuffer [0], rval = 1'0).
Adding SRST signal on $auto$opt_dff.cc:764:run$16229 ($dffe) from module mgmt_core (D = { \mprj2_vdd_pwrgood \mprj_vdd_pwrgood }, Q = \soc.sysctrl.sysctrl.iomem_rdata [3:2], rval = 2'00).

13.20.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 32 unused cells and 45 unused wires.
<suppressed ~33 debug messages>

13.20.17. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~1 debug messages>

13.20.18. Rerunning OPT passes. (Maybe there is more to do..)

13.20.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~248 debug messages>

13.20.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $auto$opt_share.cc:241:merge_operators$18902:
      Old ports: A=2, B=32'11111111111111111111111111111111, Y=$auto$rtlil.cc:2218:Mux$18903
      New ports: A=1'0, B=1'1, Y=$auto$rtlil.cc:2218:Mux$18903 [0]
      New connections: $auto$rtlil.cc:2218:Mux$18903 [31:1] = { $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] $auto$rtlil.cc:2218:Mux$18903 [0] 1'1 }
  Optimizing cells in module \mgmt_core.
Performed a total of 1 changes.

13.20.21. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

13.20.22. Executing OPT_SHARE pass.

13.20.23. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$17588 ($sdffe) from module mgmt_core.
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$17588 ($sdffe) from module mgmt_core.
Setting constant 0-bit at position 3 on $auto$opt_dff.cc:764:run$16240 ($sdffe) from module mgmt_core.

13.20.24. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

13.20.25. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~2 debug messages>

13.20.26. Rerunning OPT passes. (Maybe there is more to do..)

13.20.27. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~247 debug messages>

13.20.28. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
    Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.$procmux$13863:
      Old ports: A={ \soc.cpu.wbm_adr_o [7:2] 2'00 }, B=8'00000000, Y=$flatten\soc.\spimemio.\spimemio.$procmux$13863_Y
      New ports: A=\soc.cpu.wbm_adr_o [7:2], B=6'000000, Y=$flatten\soc.\spimemio.\spimemio.$procmux$13863_Y [7:2]
      New connections: $flatten\soc.\spimemio.\spimemio.$procmux$13863_Y [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\soc.\spimemio.\spimemio.$ternary$/project/openlane/mgmt_core/../../verilog/rtl/spimemio.v:388$1227:
      Old ports: A={ \soc.cpu.wbm_adr_o [23:2] 2'00 }, B={ $auto$wreduce.cc:454:run$18014 [23:2] 2'xx }, Y=$auto$wreduce.cc:454:run$18015 [23:0]
      New ports: A={ \soc.cpu.wbm_adr_o [23:2] 1'0 }, B={ $auto$wreduce.cc:454:run$18014 [23:2] 1'x }, Y={ $auto$wreduce.cc:454:run$18015 [23:2] $auto$wreduce.cc:454:run$18015 [0] }
      New connections: $auto$wreduce.cc:454:run$18015 [1] = $auto$wreduce.cc:454:run$18015 [0]
  Optimizing cells in module \mgmt_core.
Performed a total of 2 changes.

13.20.29. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

13.20.30. Executing OPT_SHARE pass.

13.20.31. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 3 on $flatten\soc.\spimemio.\spimemio.\xfer.$procdff$14959 ($dff) from module mgmt_core.

13.20.32. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

13.20.33. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

13.20.34. Rerunning OPT passes. (Maybe there is more to do..)

13.20.35. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~247 debug messages>

13.20.36. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
Performed a total of 0 changes.

13.20.37. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

13.20.38. Executing OPT_SHARE pass.

13.20.39. Executing OPT_DFF pass (perform DFF optimizations).

13.20.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

13.20.41. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

13.20.42. Finished OPT passes. (There is nothing left to do.)

13.21. Executing TECHMAP pass (map to technology primitives).

13.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

13.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $ne.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $adff.
Using extmapper simplemap for cells of type $adffe.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=3\Y_WIDTH=4 for cells of type $alu.
Using extmapper simplemap for cells of type $dff.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=0\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $sdffce.
Using extmapper maccmap for cells of type $macc.
  add \soc.cpu.picorv32_core.pcpi_mul.rd [31:28] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [31:28] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rdx [28] (1 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
Using template $paramod\_90_pmux\WIDTH=13\S_WIDTH=37 for cells of type $pmux.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=1\Y_WIDTH=7 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=31\B_WIDTH=31\Y_WIDTH=31 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=1\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=1\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=63\Y_WIDTH=63 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=7\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=5\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=7 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=0\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu.
  add \soc.cpu.picorv32_core.pcpi_mul.rd [15:12] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [15:12] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rdx [12] (1 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
  add \soc.cpu.picorv32_core.pcpi_mul.rd [27:24] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [27:24] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rdx [24] (1 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
  add \soc.cpu.picorv32_core.pcpi_mul.rd [3:0] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [3:0] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rd [23:20] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [23:20] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rdx [20] (1 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
  add \soc.cpu.picorv32_core.pcpi_mul.rd [19:16] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [19:16] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rdx [16] (1 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
  add \soc.cpu.picorv32_core.pcpi_mul.rd [11:8] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [11:8] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rdx [8] (1 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
  add \soc.cpu.picorv32_core.pcpi_mul.rd [7:4] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.this_rs2 [7:4] (4 bits, unsigned)
  add \soc.cpu.picorv32_core.pcpi_mul.rdx [4] (1 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=22\Y_WIDTH=23 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux.
Using template $paramod$constmap:66d421c313e4e958be776b99540ac2de3b59fdbc$paramod$9b74a473ccd678a23e1df4cc12019cbbece20051\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=2 for cells of type $pmux.
Using extmapper simplemap for cells of type $dffsre.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=6\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=6\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=6\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=5\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=5\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=5 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=5 for cells of type $pmux.
Using template $paramod$constmap:87f69c0bea22f84de4bcd0314b57cb19e61b5eb7$paramod$88abf4b792300efa328894e6936be740fdc22f6d\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$887c9fe2c55be14c90171bd2ff359c086a0858d7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=6 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=64\Y_WIDTH=64 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=8 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=31 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=3 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=64 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=4 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=23 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=5 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=63 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=30 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=6 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=7 for cells of type $lcu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
No more expansions possible.
<suppressed ~13220 debug messages>

13.22. Executing OPT pass (performing simple optimizations).

13.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~9480 debug messages>

13.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
<suppressed ~11547 debug messages>
Removed a total of 3849 cells.

13.22.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$39409 ($_DFFE_PP_) from module mgmt_core (D = 1'x, Q = \soc.spimemio.spimemio.rd_addr [0], rval = 1'0).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$66014 ($_SDFFCE_PN0P_) from module mgmt_core.

13.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 972 unused cells and 9378 unused wires.
<suppressed ~973 debug messages>

13.22.5. Rerunning OPT passes. (Removed registers in this run.)

13.22.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~4 debug messages>

13.22.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

13.22.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$38143 ($_SDFFE_PP0P_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$7999.B_AND_S [32], Q = \soc.cpu.picorv32_core.reg_pc [0]).
Adding EN signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$20331 ($_SDFFE_PP0P_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.\xfer.$procmux$13536.Y_B [0], Q = \soc.spimemio.spimemio.xfer.count [0]).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35611 ($_SDFF_PP0_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13746.Y_B, Q = \soc.spimemio.spimemio.din_valid, rval = 1'0).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34763 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [30], Q = \soc.cpu.picorv32_core.irq_pending [31]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34762 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [29], Q = \soc.cpu.picorv32_core.irq_pending [30]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34761 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [28], Q = \soc.cpu.picorv32_core.irq_pending [29]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34760 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [27], Q = \soc.cpu.picorv32_core.irq_pending [28]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34759 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [26], Q = \soc.cpu.picorv32_core.irq_pending [27]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34758 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [25], Q = \soc.cpu.picorv32_core.irq_pending [26]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34757 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [24], Q = \soc.cpu.picorv32_core.irq_pending [25]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34756 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [23], Q = \soc.cpu.picorv32_core.irq_pending [24]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34755 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [22], Q = \soc.cpu.picorv32_core.irq_pending [23]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34754 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [21], Q = \soc.cpu.picorv32_core.irq_pending [22]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34753 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [20], Q = \soc.cpu.picorv32_core.irq_pending [21]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34752 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [19], Q = \soc.cpu.picorv32_core.irq_pending [20]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34751 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [18], Q = \soc.cpu.picorv32_core.irq_pending [19]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34750 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [17], Q = \soc.cpu.picorv32_core.irq_pending [18]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34749 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [16], Q = \soc.cpu.picorv32_core.irq_pending [17]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34748 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [15], Q = \soc.cpu.picorv32_core.irq_pending [16]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34747 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [14], Q = \soc.cpu.picorv32_core.irq_pending [15]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34746 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [13], Q = \soc.cpu.picorv32_core.irq_pending [14]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34745 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [12], Q = \soc.cpu.picorv32_core.irq_pending [13]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34744 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [11], Q = \soc.cpu.picorv32_core.irq_pending [12]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34743 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [7], Q = \soc.cpu.picorv32_core.irq_pending [8]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34742 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [4], Q = \soc.cpu.picorv32_core.irq_pending [5]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34741 ($_SDFF_PP0_) from module mgmt_core (D = $auto$opt_expr.cc:205:group_cell_inputs$18383 [3], Q = \soc.cpu.picorv32_core.irq_pending [3]).
Adding EN signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34740 ($_SDFF_PP0_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$7630.Y, Q = \soc.cpu.picorv32_core.irq_pending [1]).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37838 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [31], Q = \soc.cpu.picorv32_core.decoded_imm [31], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37837 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [30], Q = \soc.cpu.picorv32_core.decoded_imm [30], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37836 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [29], Q = \soc.cpu.picorv32_core.decoded_imm [29], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37835 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [28], Q = \soc.cpu.picorv32_core.decoded_imm [28], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37834 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [27], Q = \soc.cpu.picorv32_core.decoded_imm [27], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37833 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [26], Q = \soc.cpu.picorv32_core.decoded_imm [26], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37832 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [25], Q = \soc.cpu.picorv32_core.decoded_imm [25], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37831 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [24], Q = \soc.cpu.picorv32_core.decoded_imm [24], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37830 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [23], Q = \soc.cpu.picorv32_core.decoded_imm [23], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37829 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [22], Q = \soc.cpu.picorv32_core.decoded_imm [22], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37828 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [21], Q = \soc.cpu.picorv32_core.decoded_imm [21], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37827 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [20], Q = \soc.cpu.picorv32_core.decoded_imm [20], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37826 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [19], Q = \soc.cpu.picorv32_core.decoded_imm [19], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37825 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [18], Q = \soc.cpu.picorv32_core.decoded_imm [18], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37824 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [17], Q = \soc.cpu.picorv32_core.decoded_imm [17], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37823 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [16], Q = \soc.cpu.picorv32_core.decoded_imm [16], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37822 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [15], Q = \soc.cpu.picorv32_core.decoded_imm [15], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37821 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [14], Q = \soc.cpu.picorv32_core.decoded_imm [14], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37820 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [13], Q = \soc.cpu.picorv32_core.decoded_imm [13], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37819 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [12], Q = \soc.cpu.picorv32_core.decoded_imm [12], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37818 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [11], Q = \soc.cpu.picorv32_core.decoded_imm [11], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37817 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [10], Q = \soc.cpu.picorv32_core.decoded_imm [10], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37816 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [9], Q = \soc.cpu.picorv32_core.decoded_imm [9], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37815 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [8], Q = \soc.cpu.picorv32_core.decoded_imm [8], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37814 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [7], Q = \soc.cpu.picorv32_core.decoded_imm [7], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37813 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [6], Q = \soc.cpu.picorv32_core.decoded_imm [6], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37812 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [5], Q = \soc.cpu.picorv32_core.decoded_imm [5], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37811 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [4], Q = \soc.cpu.picorv32_core.decoded_imm [4], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37810 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [3], Q = \soc.cpu.picorv32_core.decoded_imm [3], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37809 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [2], Q = \soc.cpu.picorv32_core.decoded_imm [2], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$37808 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\cpu.\picorv32_core.$procmux$9510.Y_B [1], Q = \soc.cpu.picorv32_core.decoded_imm [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19989 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [7], Q = \soc.spimemio.spimemio.din_data [7], rval = 1'1).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19988 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [6], Q = \soc.spimemio.spimemio.din_data [6], rval = 1'1).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19987 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [5], Q = \soc.spimemio.spimemio.din_data [5], rval = 1'1).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19986 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [4], Q = \soc.spimemio.spimemio.din_data [4], rval = 1'1).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19985 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [3], Q = \soc.spimemio.spimemio.din_data [3], rval = 1'1).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19984 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [2], Q = \soc.spimemio.spimemio.din_data [2], rval = 1'1).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19983 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [1], Q = \soc.spimemio.spimemio.din_data [1], rval = 1'1).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$19982 ($_DFFE_PP_) from module mgmt_core (D = $flatten\soc.\spimemio.\spimemio.$procmux$13858.Y_B [0], Q = \soc.spimemio.spimemio.din_data [0], rval = 1'1).

13.22.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 88 unused cells and 30 unused wires.
<suppressed ~89 debug messages>

13.22.10. Rerunning OPT passes. (Removed registers in this run.)

13.22.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~2 debug messages>

13.22.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
<suppressed ~132 debug messages>
Removed a total of 44 cells.

13.22.13. Executing OPT_DFF pass (perform DFF optimizations).

13.22.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 45 unused wires.
<suppressed ~1 debug messages>

13.22.15. Finished fast OPT passes.

13.23. Executing ABC pass (technology mapping using ABC).

13.23.1. Extracting gate netlist of module `\mgmt_core' to `<abc-temp-dir>/input.blif'..
Extracted 20080 gates and 24166 wires to a netlist network with 4083 inputs and 1936 outputs.

13.23.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + map 
ABC: + write_blif <abc-temp-dir>/output.blif 

13.23.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:      971
ABC RESULTS:            ANDNOT cells:     4247
ABC RESULTS:               MUX cells:     5751
ABC RESULTS:              NAND cells:      771
ABC RESULTS:               NOR cells:      824
ABC RESULTS:               NOT cells:     1114
ABC RESULTS:                OR cells:     4001
ABC RESULTS:             ORNOT cells:      558
ABC RESULTS:              XNOR cells:      282
ABC RESULTS:               XOR cells:     1160
ABC RESULTS:        internal signals:    18147
ABC RESULTS:           input signals:     4083
ABC RESULTS:          output signals:     1936
Removing temp directory.

13.24. Executing OPT pass (performing simple optimizations).

13.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.
<suppressed ~3918 debug messages>

13.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
<suppressed ~228 debug messages>
Removed a total of 76 cells.

13.24.3. Executing OPT_DFF pass (perform DFF optimizations).

13.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 27 unused cells and 11570 unused wires.
<suppressed ~222 debug messages>

13.24.5. Finished fast OPT passes.

13.25. Executing HIERARCHY pass (managing design hierarchy).

13.25.1. Analyzing design hierarchy..
Top module:  \mgmt_core

13.25.2. Analyzing design hierarchy..
Top module:  \mgmt_core
Removed 0 unused modules.

13.26. Printing statistics.

=== mgmt_core ===

   Number of wires:              20026
   Number of wire bits:          33346
   Number of public wires:        1160
   Number of public wire bits:   13867
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              23444
     $_ANDNOT_                    4240
     $_AND_                        971
     $_DFFE_NN0P_                   12
     $_DFFE_NN1P_                   32
     $_DFFE_NP0N_                    3
     $_DFFE_NP0P_                   26
     $_DFFE_PN0N_                    7
     $_DFFE_PN0P_                  182
     $_DFFE_PN1N_                    5
     $_DFFE_PN1P_                   23
     $_DFFE_PN_                      7
     $_DFFE_PP0P_                    9
     $_DFFE_PP_                   1654
     $_DFFSRE_NPPP_                 12
     $_DFFSRE_PPPP_                  6
     $_DFF_NP0_                      4
     $_DFF_NP1_                      1
     $_DFF_N_                        2
     $_DFF_PN0_                     25
     $_DFF_PN1_                      8
     $_DFF_PP1_                      1
     $_DFF_P_                      152
     $_MUX_                       5744
     $_NAND_                       767
     $_NOR_                        773
     $_NOT_                       1087
     $_ORNOT_                      556
     $_OR_                        3998
     $_SDFFCE_PN0P_                 42
     $_SDFFCE_PN1P_                  8
     $_SDFFCE_PP0P_                177
     $_SDFFCE_PP1P_                  5
     $_SDFFE_PN0N_                   1
     $_SDFFE_PN0P_                 916
     $_SDFFE_PN1N_                   4
     $_SDFFE_PN1P_                 285
     $_SDFFE_PP0P_                  20
     $_SDFFE_PP1N_                   2
     $_SDFFE_PP1P_                  11
     $_SDFF_PN0_                   181
     $_SDFF_PN1_                     3
     $_SDFF_PP0_                    38
     $_SDFF_PP1_                     2
     $_XNOR_                       281
     $_XOR_                       1159
     DFFRAM                          1
     digital_pll                     1

13.27. Executing CHECK pass (checking for obvious problems).
checking module mgmt_core..
Warning: multiple conflicting drivers for mgmt_core.\soc.simple_spi_master_inst.spi_master.isdo:
    port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$19703 ($_DFFE_PN0P_)
    port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$22058 ($_SDFFE_PN0P_)
Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [9]:
    port Y[0] of cell $abc$66242$auto$blifparse.cc:377:parse_blif$85027 ($_ANDNOT_)
    port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$22065 ($_SDFFE_PN0P_)
Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [10]:
    port Y[0] of cell $abc$66242$auto$blifparse.cc:377:parse_blif$85026 ($_AND_)
    port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$22066 ($_SDFFE_PN0P_)
Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [8]:
    port Y[0] of cell $abc$66242$auto$blifparse.cc:377:parse_blif$83360 ($_NOT_)
    port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$22064 ($_SDFFE_PN0P_)
Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [3]:
    port Y[0] of cell $abc$66242$auto$blifparse.cc:377:parse_blif$70033 ($_XOR_)
    port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$22059 ($_SDFFE_PN0P_)
Warning: multiple conflicting drivers for mgmt_core.\soc.mprj_ctrl.mprj_ctrl.mgmt_gpio_outr [4]:
    port Y[0] of cell $abc$66242$auto$blifparse.cc:377:parse_blif$70029 ($_NOT_)
    port Q[0] of cell $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$22060 ($_SDFFE_PN0P_)
found and reported 6 problems.

14. Executing SHARE pass (SAT-based resource sharing).

15. Executing OPT pass (performing simple optimizations).

15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \mgmt_core..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \mgmt_core.
Performed a total of 0 changes.

15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\mgmt_core'.
Removed a total of 0 cells.

15.6. Executing OPT_DFF pass (perform DFF optimizations).

15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..

15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module mgmt_core.

15.9. Finished OPT passes. (There is nothing left to do.)

16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 0 unused cells and 665 unused wires.
<suppressed ~665 debug messages>

17. Printing statistics.

=== mgmt_core ===

   Number of wires:              19361
   Number of wire bits:          24892
   Number of public wires:         495
   Number of public wire bits:    5413
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              23444
     $_ANDNOT_                    4240
     $_AND_                        971
     $_DFFE_NN0P_                   12
     $_DFFE_NN1P_                   32
     $_DFFE_NP0N_                    3
     $_DFFE_NP0P_                   26
     $_DFFE_PN0N_                    7
     $_DFFE_PN0P_                  182
     $_DFFE_PN1N_                    5
     $_DFFE_PN1P_                   23
     $_DFFE_PN_                      7
     $_DFFE_PP0P_                    9
     $_DFFE_PP_                   1654
     $_DFFSRE_NPPP_                 12
     $_DFFSRE_PPPP_                  6
     $_DFF_NP0_                      4
     $_DFF_NP1_                      1
     $_DFF_N_                        2
     $_DFF_PN0_                     25
     $_DFF_PN1_                      8
     $_DFF_PP1_                      1
     $_DFF_P_                      152
     $_MUX_                       5744
     $_NAND_                       767
     $_NOR_                        773
     $_NOT_                       1087
     $_ORNOT_                      556
     $_OR_                        3998
     $_SDFFCE_PN0P_                 42
     $_SDFFCE_PN1P_                  8
     $_SDFFCE_PP0P_                177
     $_SDFFCE_PP1P_                  5
     $_SDFFE_PN0N_                   1
     $_SDFFE_PN0P_                 916
     $_SDFFE_PN1N_                   4
     $_SDFFE_PN1P_                 285
     $_SDFFE_PP0P_                  20
     $_SDFFE_PP1N_                   2
     $_SDFFE_PP1P_                  11
     $_SDFF_PN0_                   181
     $_SDFF_PN1_                     3
     $_SDFF_PP0_                    38
     $_SDFF_PP1_                     2
     $_XNOR_                       281
     $_XOR_                       1159
     DFFRAM                          1
     digital_pll                     1

18. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

18.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\mgmt_core':
  mapped 18 $_DFFSR_NNN_ cells to \sky130_fd_sc_hd__dfbbn_2 cells.
  mapped 268 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_4 cells.
  mapped 70 $_DFF_PN1_ cells to \sky130_fd_sc_hd__dfstp_4 cells.
  mapped 3510 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_4 cells.

19. Printing statistics.

=== mgmt_core ===

   Number of wires:              24695
   Number of wire bits:          30226
   Number of public wires:         495
   Number of public wire bits:    5413
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              28754
     $_ANDNOT_                    4240
     $_AND_                        971
     $_MUX_                      10888
     $_NAND_                       767
     $_NOR_                        773
     $_NOT_                       1253
     $_ORNOT_                      556
     $_OR_                        3998
     $_XNOR_                       281
     $_XOR_                       1159
     DFFRAM                          1
     digital_pll                     1
     sky130_fd_sc_hd__dfbbn_2       18
     sky130_fd_sc_hd__dfrtp_4      268
     sky130_fd_sc_hd__dfstp_4       70
     sky130_fd_sc_hd__dfxtp_4     3510

20. Executing ABC pass (technology mapping using ABC).

20.1. Extracting gate netlist of module `\mgmt_core' to `/tmp/yosys-abc-BEDAcD/input.blif'..
Extracted 24886 gates and 29115 wires to a netlist network with 4227 inputs and 4046 outputs.

20.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-BEDAcD/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-BEDAcD/abc.script".
ABC: 
ABC: + read_blif /tmp/yosys-abc-BEDAcD/input.blif 
ABC: + read_lib -w /project/openlane/mgmt_core/runs/mgmt_core/tmp/trimmed.lib 
ABC: Parsing finished successfully.  Parsing time =     0.02 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/mgmt_core/runs/mgmt_core/tmp/trimmed.lib" has 43 cells (6 skipped: 6 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.03 sec
ABC: Memory =    1.82 MB. Time =     0.03 sec
ABC: + read_constr -v /project/openlane/mgmt_core/runs/mgmt_core/tmp/synthesis/yosys.sdc 
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
ABC: Setting output load to be 17.650000.
ABC: + read_constr /project/openlane/mgmt_core/runs/mgmt_core/tmp/synthesis/yosys.sdc 
ABC: + fx 
ABC: + mfs 
ABC: + strash 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + retime -D -D 50000 -M 5 
ABC: + scleanup 
ABC: Error: The network is combinational.
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 
ABC: + retime -D -D 50000 
ABC: + buffer -N 4 -S 5000.0 
ABC: Node 10289 has dup fanin 10285.
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ABC: Node 10947 has dup fanin 263.
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ABC: Node 10953 has dup fanin 280.
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ABC: Node 11202 has dup fanin 253.
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ABC: Node 11253 has dup fanin 257.
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ABC: Node 11586 has dup fanin 319.
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ABC: Node 12870 has dup fanin 12869.
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ABC: Node 22736 has dup fanin 22570.
ABC: Node 22736 has dup fanin 22570.
ABC: Node 22742 has dup fanin 22570.
ABC: Node 22742 has dup fanin 22570.
ABC: Node 22748 has dup fanin 22570.
ABC: Node 22748 has dup fanin 22570.
ABC: Node 22754 has dup fanin 22570.
ABC: Node 22754 has dup fanin 22570.
ABC: Node 22760 has dup fanin 22570.
ABC: Node 22760 has dup fanin 22570.
ABC: Node 22766 has dup fanin 22570.
ABC: Node 22766 has dup fanin 22570.
ABC: Node 22772 has dup fanin 22570.
ABC: Node 22772 has dup fanin 22570.
ABC: Node 22778 has dup fanin 22570.
ABC: Node 22778 has dup fanin 22570.
ABC: Node 22784 has dup fanin 22570.
ABC: Node 22784 has dup fanin 22570.
ABC: Node 22790 has dup fanin 22570.
ABC: Node 22790 has dup fanin 22570.
ABC: Node 22798 has dup fanin 22570.
ABC: Node 22798 has dup fanin 22570.
ABC: Node 22800 has dup fanin 22799.
ABC: Node 22800 has dup fanin 22799.
ABC: Node 22801 has dup fanin 22799.
ABC: Node 22801 has dup fanin 22799.
ABC: Node 22802 has dup fanin 22799.
ABC: Node 22802 has dup fanin 22799.
ABC: Node 22803 has dup fanin 22799.
ABC: Node 22803 has dup fanin 22799.
ABC: Node 22804 has dup fanin 22799.
ABC: Node 22804 has dup fanin 22799.
ABC: Node 22805 has dup fanin 22799.
ABC: Node 22805 has dup fanin 22799.
ABC: Node 22806 has dup fanin 22799.
ABC: Node 22806 has dup fanin 22799.
ABC: Node 22807 has dup fanin 22799.
ABC: Node 22807 has dup fanin 22799.
ABC: Node 22808 has dup fanin 22799.
ABC: Node 22808 has dup fanin 22799.
ABC: Node 22809 has dup fanin 22799.
ABC: Node 22809 has dup fanin 22799.
ABC: Node 22810 has dup fanin 22799.
ABC: Node 22810 has dup fanin 22799.
ABC: Node 22811 has dup fanin 22799.
ABC: Node 22811 has dup fanin 22799.
ABC: Node 22812 has dup fanin 22799.
ABC: Node 22812 has dup fanin 22799.
ABC: Node 22813 has dup fanin 22799.
ABC: Node 22813 has dup fanin 22799.
ABC: Node 22814 has dup fanin 22799.
ABC: Node 22814 has dup fanin 22799.
ABC: Node 22815 has dup fanin 22799.
ABC: Node 22815 has dup fanin 22799.
ABC: Node 22816 has dup fanin 22799.
ABC: Node 22816 has dup fanin 22799.
ABC: Node 22817 has dup fanin 22799.
ABC: Node 22817 has dup fanin 22799.
ABC: Node 22818 has dup fanin 22799.
ABC: Node 22818 has dup fanin 22799.
ABC: Node 22819 has dup fanin 22799.
ABC: Node 22819 has dup fanin 22799.
ABC: Node 22820 has dup fanin 22799.
ABC: Node 22820 has dup fanin 22799.
ABC: Node 22821 has dup fanin 22799.
ABC: Node 22821 has dup fanin 22799.
ABC: Node 22822 has dup fanin 22799.
ABC: Node 22822 has dup fanin 22799.
ABC: Node 22823 has dup fanin 22799.
ABC: Node 22823 has dup fanin 22799.
ABC: Node 22824 has dup fanin 22799.
ABC: Node 22824 has dup fanin 22799.
ABC: Node 22825 has dup fanin 22799.
ABC: Node 22825 has dup fanin 22799.
ABC: Node 22826 has dup fanin 22799.
ABC: Node 22826 has dup fanin 22799.
ABC: Node 22827 has dup fanin 22799.
ABC: Node 22827 has dup fanin 22799.
ABC: Node 22828 has dup fanin 22799.
ABC: Node 22828 has dup fanin 22799.
ABC: Node 22829 has dup fanin 22799.
ABC: Node 22829 has dup fanin 22799.
ABC: Node 22830 has dup fanin 22799.
ABC: Node 22830 has dup fanin 22799.
ABC: Node 22831 has dup fanin 22799.
ABC: Node 22831 has dup fanin 22799.
ABC: Node 22833 has dup fanin 22832.
ABC: Node 22833 has dup fanin 22832.
ABC: Node 22834 has dup fanin 22832.
ABC: Node 22834 has dup fanin 22832.
ABC: Node 22835 has dup fanin 22832.
ABC: Node 22835 has dup fanin 22832.
ABC: Node 22836 has dup fanin 22832.
ABC: Node 22836 has dup fanin 22832.
ABC: Node 22837 has dup fanin 22832.
ABC: Node 22837 has dup fanin 22832.
ABC: Node 22838 has dup fanin 22832.
ABC: Node 22838 has dup fanin 22832.
ABC: Node 22839 has dup fanin 22832.
ABC: Node 22839 has dup fanin 22832.
ABC: Node 22840 has dup fanin 22832.
ABC: Node 22840 has dup fanin 22832.
ABC: Node 22841 has dup fanin 22832.
ABC: Node 22841 has dup fanin 22832.
ABC: Node 22842 has dup fanin 22832.
ABC: Node 22842 has dup fanin 22832.
ABC: Node 22843 has dup fanin 22832.
ABC: Node 22843 has dup fanin 22832.
ABC: Node 22844 has dup fanin 22832.
ABC: Node 22844 has dup fanin 22832.
ABC: Node 22845 has dup fanin 22832.
ABC: Node 22845 has dup fanin 22832.
ABC: Node 22846 has dup fanin 22832.
ABC: Node 22846 has dup fanin 22832.
ABC: Node 22847 has dup fanin 22832.
ABC: Node 22847 has dup fanin 22832.
ABC: Node 22848 has dup fanin 22832.
ABC: Node 22848 has dup fanin 22832.
ABC: Node 22849 has dup fanin 22832.
ABC: Node 22849 has dup fanin 22832.
ABC: Node 22850 has dup fanin 22832.
ABC: Node 22850 has dup fanin 22832.
ABC: Node 22851 has dup fanin 22832.
ABC: Node 22851 has dup fanin 22832.
ABC: Node 22852 has dup fanin 22832.
ABC: Node 22852 has dup fanin 22832.
ABC: Node 22853 has dup fanin 22832.
ABC: Node 22853 has dup fanin 22832.
ABC: Node 22854 has dup fanin 22832.
ABC: Node 22854 has dup fanin 22832.
ABC: Node 22855 has dup fanin 22832.
ABC: Node 22855 has dup fanin 22832.
ABC: Node 22856 has dup fanin 22832.
ABC: Node 22856 has dup fanin 22832.
ABC: Node 22857 has dup fanin 22832.
ABC: Node 22857 has dup fanin 22832.
ABC: Node 22858 has dup fanin 22832.
ABC: Node 22858 has dup fanin 22832.
ABC: Node 22859 has dup fanin 22832.
ABC: Node 22859 has dup fanin 22832.
ABC: Node 22860 has dup fanin 22832.
ABC: Node 22860 has dup fanin 22832.
ABC: Node 22861 has dup fanin 22832.
ABC: Node 22861 has dup fanin 22832.
ABC: Node 22862 has dup fanin 22832.
ABC: Node 22862 has dup fanin 22832.
ABC: Node 22863 has dup fanin 22832.
ABC: Node 22863 has dup fanin 22832.
ABC: Node 22864 has dup fanin 22832.
ABC: Node 22864 has dup fanin 22832.
ABC: Node 22867 has dup fanin 22866.
ABC: Node 22867 has dup fanin 22866.
ABC: Node 22868 has dup fanin 22866.
ABC: Node 22868 has dup fanin 22866.
ABC: Node 22869 has dup fanin 22866.
ABC: Node 22869 has dup fanin 22866.
ABC: Node 22870 has dup fanin 22866.
ABC: Node 22870 has dup fanin 22866.
ABC: Node 22871 has dup fanin 22866.
ABC: Node 22871 has dup fanin 22866.
ABC: Node 22872 has dup fanin 22866.
ABC: Node 22872 has dup fanin 22866.
ABC: Node 22873 has dup fanin 22866.
ABC: Node 22873 has dup fanin 22866.
ABC: Node 22874 has dup fanin 22866.
ABC: Node 22874 has dup fanin 22866.
ABC: Node 22875 has dup fanin 22866.
ABC: Node 22875 has dup fanin 22866.
ABC: Node 22876 has dup fanin 22866.
ABC: Node 22876 has dup fanin 22866.
ABC: Node 22877 has dup fanin 22866.
ABC: Node 22877 has dup fanin 22866.
ABC: Node 22878 has dup fanin 22866.
ABC: Node 22878 has dup fanin 22866.
ABC: Node 22879 has dup fanin 22866.
ABC: Node 22879 has dup fanin 22866.
ABC: Node 22880 has dup fanin 22866.
ABC: Node 22880 has dup fanin 22866.
ABC: Node 22881 has dup fanin 22866.
ABC: Node 22881 has dup fanin 22866.
ABC: Node 22882 has dup fanin 22866.
ABC: Node 22882 has dup fanin 22866.
ABC: Node 22883 has dup fanin 22866.
ABC: Node 22883 has dup fanin 22866.
ABC: Node 22884 has dup fanin 22866.
ABC: Node 22884 has dup fanin 22866.
ABC: Node 22885 has dup fanin 22866.
ABC: Node 22885 has dup fanin 22866.
ABC: Node 22886 has dup fanin 22866.
ABC: Node 22886 has dup fanin 22866.
ABC: Node 22887 has dup fanin 22866.
ABC: Node 22887 has dup fanin 22866.
ABC: Node 22888 has dup fanin 22866.
ABC: Node 22888 has dup fanin 22866.
ABC: Node 22889 has dup fanin 22866.
ABC: Node 22889 has dup fanin 22866.
ABC: Node 22890 has dup fanin 22866.
ABC: Node 22890 has dup fanin 22866.
ABC: Node 22891 has dup fanin 22866.
ABC: Node 22891 has dup fanin 22866.
ABC: Node 22892 has dup fanin 22866.
ABC: Node 22892 has dup fanin 22866.
ABC: Node 22893 has dup fanin 22866.
ABC: Node 22893 has dup fanin 22866.
ABC: Node 22894 has dup fanin 22866.
ABC: Node 22894 has dup fanin 22866.
ABC: Node 22895 has dup fanin 22866.
ABC: Node 22895 has dup fanin 22866.
ABC: Node 22896 has dup fanin 22866.
ABC: Node 22896 has dup fanin 22866.
ABC: Node 22897 has dup fanin 22866.
ABC: Node 22897 has dup fanin 22866.
ABC: Node 22898 has dup fanin 22866.
ABC: Node 22898 has dup fanin 22866.
ABC: Node 22901 has dup fanin 22900.
ABC: Node 22901 has dup fanin 22900.
ABC: Node 22902 has dup fanin 22900.
ABC: Node 22902 has dup fanin 22900.
ABC: Node 22903 has dup fanin 22900.
ABC: Node 22903 has dup fanin 22900.
ABC: Node 22904 has dup fanin 22900.
ABC: Node 22904 has dup fanin 22900.
ABC: Node 22905 has dup fanin 22900.
ABC: Node 22905 has dup fanin 22900.
ABC: Node 22906 has dup fanin 22900.
ABC: Node 22906 has dup fanin 22900.
ABC: Node 22907 has dup fanin 22900.
ABC: Node 22907 has dup fanin 22900.
ABC: Node 22908 has dup fanin 22900.
ABC: Node 22908 has dup fanin 22900.
ABC: Node 22909 has dup fanin 22900.
ABC: Node 22909 has dup fanin 22900.
ABC: Node 22910 has dup fanin 22900.
ABC: Node 22910 has dup fanin 22900.
ABC: Node 22911 has dup fanin 22900.
ABC: Node 22911 has dup fanin 22900.
ABC: Node 22912 has dup fanin 22900.
ABC: Node 22912 has dup fanin 22900.
ABC: Node 22913 has dup fanin 22900.
ABC: Node 22913 has dup fanin 22900.
ABC: Node 22914 has dup fanin 22900.
ABC: Node 22914 has dup fanin 22900.
ABC: Node 22915 has dup fanin 22900.
ABC: Node 22915 has dup fanin 22900.
ABC: Node 22916 has dup fanin 22900.
ABC: Node 22916 has dup fanin 22900.
ABC: Node 22917 has dup fanin 22900.
ABC: Node 22917 has dup fanin 22900.
ABC: Node 22918 has dup fanin 22900.
ABC: Node 22918 has dup fanin 22900.
ABC: Node 22919 has dup fanin 22900.
ABC: Node 22919 has dup fanin 22900.
ABC: Node 22920 has dup fanin 22900.
ABC: Node 22920 has dup fanin 22900.
ABC: Node 22921 has dup fanin 22900.
ABC: Node 22921 has dup fanin 22900.
ABC: Node 22922 has dup fanin 22900.
ABC: Node 22922 has dup fanin 22900.
ABC: Node 22923 has dup fanin 22900.
ABC: Node 22923 has dup fanin 22900.
ABC: Node 22924 has dup fanin 22900.
ABC: Node 22924 has dup fanin 22900.
ABC: Node 22925 has dup fanin 22900.
ABC: Node 22925 has dup fanin 22900.
ABC: Node 22926 has dup fanin 22900.
ABC: Node 22926 has dup fanin 22900.
ABC: Node 22927 has dup fanin 22900.
ABC: Node 22927 has dup fanin 22900.
ABC: Node 22928 has dup fanin 22900.
ABC: Node 22928 has dup fanin 22900.
ABC: Node 22929 has dup fanin 22900.
ABC: Node 22929 has dup fanin 22900.
ABC: Node 22930 has dup fanin 22900.
ABC: Node 22930 has dup fanin 22900.
ABC: Node 22931 has dup fanin 22900.
ABC: Node 22931 has dup fanin 22900.
ABC: Node 22932 has dup fanin 22900.
ABC: Node 22932 has dup fanin 22900.
ABC: Node 22937 has dup fanin 22936.
ABC: Node 22937 has dup fanin 22936.
ABC: Node 22938 has dup fanin 22936.
ABC: Node 22938 has dup fanin 22936.
ABC: Node 22939 has dup fanin 22936.
ABC: Node 22939 has dup fanin 22936.
ABC: Node 22940 has dup fanin 22936.
ABC: Node 22940 has dup fanin 22936.
ABC: Node 22941 has dup fanin 22936.
ABC: Node 22941 has dup fanin 22936.
ABC: Node 22942 has dup fanin 22936.
ABC: Node 22942 has dup fanin 22936.
ABC: Node 22943 has dup fanin 22936.
ABC: Node 22943 has dup fanin 22936.
ABC: Node 22944 has dup fanin 22936.
ABC: Node 22944 has dup fanin 22936.
ABC: Node 22945 has dup fanin 22936.
ABC: Node 22945 has dup fanin 22936.
ABC: Node 22946 has dup fanin 22936.
ABC: Node 22946 has dup fanin 22936.
ABC: Node 22947 has dup fanin 22936.
ABC: Node 22947 has dup fanin 22936.
ABC: Node 22948 has dup fanin 22936.
ABC: Node 22948 has dup fanin 22936.
ABC: Node 22949 has dup fanin 22936.
ABC: Node 22949 has dup fanin 22936.
ABC: Node 22950 has dup fanin 22936.
ABC: Node 22950 has dup fanin 22936.
ABC: Node 22951 has dup fanin 22936.
ABC: Node 22951 has dup fanin 22936.
ABC: Node 22952 has dup fanin 22936.
ABC: Node 22952 has dup fanin 22936.
ABC: Node 22953 has dup fanin 12742.
ABC: Node 22953 has dup fanin 12742.
ABC: Node 22954 has dup fanin 12742.
ABC: Node 22954 has dup fanin 12742.
ABC: Node 22955 has dup fanin 12742.
ABC: Node 22955 has dup fanin 12742.
ABC: Node 22956 has dup fanin 12742.
ABC: Node 22956 has dup fanin 12742.
ABC: Node 22957 has dup fanin 12742.
ABC: Node 22957 has dup fanin 12742.
ABC: Node 22958 has dup fanin 12742.
ABC: Node 22958 has dup fanin 12742.
ABC: Node 22959 has dup fanin 12742.
ABC: Node 22959 has dup fanin 12742.
ABC: Node 22960 has dup fanin 12742.
ABC: Node 22960 has dup fanin 12742.
ABC: Node 22961 has dup fanin 12742.
ABC: Node 22961 has dup fanin 12742.
ABC: Node 22962 has dup fanin 12742.
ABC: Node 22962 has dup fanin 12742.
ABC: Node 22963 has dup fanin 12742.
ABC: Node 22963 has dup fanin 12742.
ABC: Node 22964 has dup fanin 12742.
ABC: Node 22964 has dup fanin 12742.
ABC: Node 22965 has dup fanin 12742.
ABC: Node 22965 has dup fanin 12742.
ABC: Node 22966 has dup fanin 12742.
ABC: Node 22966 has dup fanin 12742.
ABC: Node 22967 has dup fanin 12742.
ABC: Node 22967 has dup fanin 12742.
ABC: Node 22968 has dup fanin 12742.
ABC: Node 22968 has dup fanin 12742.
ABC: Node 22969 has dup fanin 12742.
ABC: Node 22969 has dup fanin 12742.
ABC: Node 23012 has dup fanin 12693.
ABC: Node 23012 has dup fanin 12693.
ABC: Node 23193 has dup fanin 12812.
ABC: Node 23193 has dup fanin 12812.
ABC: Node 23203 has dup fanin 12812.
ABC: Node 23203 has dup fanin 12812.
ABC: Node 23221 has dup fanin 12812.
ABC: Node 23221 has dup fanin 12812.
ABC: Node 23232 has dup fanin 12812.
ABC: Node 23232 has dup fanin 12812.
ABC: Node 23248 has dup fanin 12812.
ABC: Node 23248 has dup fanin 12812.
ABC: Node 23272 has dup fanin 12812.
ABC: Node 23272 has dup fanin 12812.
ABC: Node 23304 has dup fanin 12813.
ABC: Node 23304 has dup fanin 12813.
ABC: Node 23332 has dup fanin 12813.
ABC: Node 23332 has dup fanin 12813.
ABC: Node 23357 has dup fanin 12812.
ABC: Node 23357 has dup fanin 12812.
ABC: Node 23378 has dup fanin 12693.
ABC: Node 23378 has dup fanin 12693.
ABC: Node 23379 has dup fanin 12693.
ABC: Node 23379 has dup fanin 12693.
ABC: Node 23380 has dup fanin 12693.
ABC: Node 23380 has dup fanin 12693.
ABC: Node 23381 has dup fanin 12693.
ABC: Node 23381 has dup fanin 12693.
ABC: Node 23382 has dup fanin 12693.
ABC: Node 23382 has dup fanin 12693.
ABC: Node 23383 has dup fanin 12693.
ABC: Node 23383 has dup fanin 12693.
ABC: Node 23384 has dup fanin 12693.
ABC: Node 23384 has dup fanin 12693.
ABC: Node 23387 has dup fanin 23386.
ABC: Node 23387 has dup fanin 23386.
ABC: Node 23388 has dup fanin 23386.
ABC: Node 23388 has dup fanin 23386.
ABC: Node 23389 has dup fanin 23386.
ABC: Node 23389 has dup fanin 23386.
ABC: Node 23390 has dup fanin 23386.
ABC: Node 23390 has dup fanin 23386.
ABC: Node 23391 has dup fanin 23386.
ABC: Node 23391 has dup fanin 23386.
ABC: Node 23392 has dup fanin 23386.
ABC: Node 23392 has dup fanin 23386.
ABC: Node 23393 has dup fanin 23386.
ABC: Node 23393 has dup fanin 23386.
ABC: Node 23394 has dup fanin 23386.
ABC: Node 23394 has dup fanin 23386.
ABC: Node 23395 has dup fanin 23386.
ABC: Node 23395 has dup fanin 23386.
ABC: Node 23396 has dup fanin 23386.
ABC: Node 23396 has dup fanin 23386.
ABC: Node 23397 has dup fanin 23386.
ABC: Node 23397 has dup fanin 23386.
ABC: Node 23398 has dup fanin 23386.
ABC: Node 23398 has dup fanin 23386.
ABC: Node 23399 has dup fanin 23386.
ABC: Node 23399 has dup fanin 23386.
ABC: Node 23400 has dup fanin 23386.
ABC: Node 23400 has dup fanin 23386.
ABC: Node 23401 has dup fanin 23386.
ABC: Node 23401 has dup fanin 23386.
ABC: Node 23402 has dup fanin 23386.
ABC: Node 23402 has dup fanin 23386.
ABC: Node 23403 has dup fanin 23386.
ABC: Node 23403 has dup fanin 23386.
ABC: Node 23404 has dup fanin 23386.
ABC: Node 23404 has dup fanin 23386.
ABC: Node 23405 has dup fanin 23386.
ABC: Node 23405 has dup fanin 23386.
ABC: Node 23406 has dup fanin 23386.
ABC: Node 23406 has dup fanin 23386.
ABC: Node 23407 has dup fanin 23386.
ABC: Node 23407 has dup fanin 23386.
ABC: Node 23408 has dup fanin 23386.
ABC: Node 23408 has dup fanin 23386.
ABC: Node 23409 has dup fanin 23386.
ABC: Node 23409 has dup fanin 23386.
ABC: Node 23410 has dup fanin 23386.
ABC: Node 23410 has dup fanin 23386.
ABC: Node 23411 has dup fanin 23386.
ABC: Node 23411 has dup fanin 23386.
ABC: Node 23412 has dup fanin 23386.
ABC: Node 23412 has dup fanin 23386.
ABC: Node 23413 has dup fanin 23386.
ABC: Node 23413 has dup fanin 23386.
ABC: Node 23414 has dup fanin 23386.
ABC: Node 23414 has dup fanin 23386.
ABC: Node 23415 has dup fanin 23386.
ABC: Node 23415 has dup fanin 23386.
ABC: Node 23416 has dup fanin 23386.
ABC: Node 23416 has dup fanin 23386.
ABC: Node 23417 has dup fanin 23386.
ABC: Node 23417 has dup fanin 23386.
ABC: Node 23418 has dup fanin 23386.
ABC: Node 23418 has dup fanin 23386.
ABC: Node 23420 has dup fanin 23419.
ABC: Node 23420 has dup fanin 23419.
ABC: Node 23421 has dup fanin 23419.
ABC: Node 23421 has dup fanin 23419.
ABC: Node 23422 has dup fanin 23419.
ABC: Node 23422 has dup fanin 23419.
ABC: Node 23423 has dup fanin 23419.
ABC: Node 23423 has dup fanin 23419.
ABC: Node 23424 has dup fanin 23419.
ABC: Node 23424 has dup fanin 23419.
ABC: Node 23425 has dup fanin 23419.
ABC: Node 23425 has dup fanin 23419.
ABC: Node 23426 has dup fanin 23419.
ABC: Node 23426 has dup fanin 23419.
ABC: Node 23427 has dup fanin 23419.
ABC: Node 23427 has dup fanin 23419.
ABC: Node 23428 has dup fanin 23419.
ABC: Node 23428 has dup fanin 23419.
ABC: Node 23429 has dup fanin 23419.
ABC: Node 23429 has dup fanin 23419.
ABC: Node 23430 has dup fanin 23419.
ABC: Node 23430 has dup fanin 23419.
ABC: Node 23431 has dup fanin 23419.
ABC: Node 23431 has dup fanin 23419.
ABC: Node 23432 has dup fanin 23419.
ABC: Node 23432 has dup fanin 23419.
ABC: Node 23433 has dup fanin 23419.
ABC: Node 23433 has dup fanin 23419.
ABC: Node 23434 has dup fanin 23419.
ABC: Node 23434 has dup fanin 23419.
ABC: Node 23435 has dup fanin 23419.
ABC: Node 23435 has dup fanin 23419.
ABC: Node 23436 has dup fanin 23419.
ABC: Node 23436 has dup fanin 23419.
ABC: Node 23437 has dup fanin 23419.
ABC: Node 23437 has dup fanin 23419.
ABC: Node 23438 has dup fanin 23419.
ABC: Node 23438 has dup fanin 23419.
ABC: Node 23439 has dup fanin 23419.
ABC: Node 23439 has dup fanin 23419.
ABC: Node 23440 has dup fanin 23419.
ABC: Node 23440 has dup fanin 23419.
ABC: Node 23441 has dup fanin 23419.
ABC: Node 23441 has dup fanin 23419.
ABC: Node 23442 has dup fanin 23419.
ABC: Node 23442 has dup fanin 23419.
ABC: Node 23443 has dup fanin 23419.
ABC: Node 23443 has dup fanin 23419.
ABC: Node 23444 has dup fanin 23419.
ABC: Node 23444 has dup fanin 23419.
ABC: Node 23445 has dup fanin 23419.
ABC: Node 23445 has dup fanin 23419.
ABC: Node 23446 has dup fanin 23419.
ABC: Node 23446 has dup fanin 23419.
ABC: Node 23447 has dup fanin 23419.
ABC: Node 23447 has dup fanin 23419.
ABC: Node 23448 has dup fanin 23419.
ABC: Node 23448 has dup fanin 23419.
ABC: Node 23449 has dup fanin 23419.
ABC: Node 23449 has dup fanin 23419.
ABC: Node 23450 has dup fanin 23419.
ABC: Node 23450 has dup fanin 23419.
ABC: Node 23451 has dup fanin 23419.
ABC: Node 23451 has dup fanin 23419.
ABC: Node 23454 has dup fanin 23453.
ABC: Node 23454 has dup fanin 23453.
ABC: Node 23455 has dup fanin 23453.
ABC: Node 23455 has dup fanin 23453.
ABC: Node 23456 has dup fanin 23453.
ABC: Node 23456 has dup fanin 23453.
ABC: Node 23457 has dup fanin 23453.
ABC: Node 23457 has dup fanin 23453.
ABC: Node 23458 has dup fanin 23453.
ABC: Node 23458 has dup fanin 23453.
ABC: Node 23459 has dup fanin 23453.
ABC: Node 23459 has dup fanin 23453.
ABC: Node 23460 has dup fanin 23453.
ABC: Node 23460 has dup fanin 23453.
ABC: Node 23461 has dup fanin 23453.
ABC: Node 23461 has dup fanin 23453.
ABC: Node 23462 has dup fanin 23453.
ABC: Node 23462 has dup fanin 23453.
ABC: Node 23463 has dup fanin 23453.
ABC: Node 23463 has dup fanin 23453.
ABC: Node 23464 has dup fanin 23453.
ABC: Node 23464 has dup fanin 23453.
ABC: Node 23465 has dup fanin 23453.
ABC: Node 23465 has dup fanin 23453.
ABC: Node 23466 has dup fanin 23453.
ABC: Node 23466 has dup fanin 23453.
ABC: Node 23467 has dup fanin 23453.
ABC: Node 23467 has dup fanin 23453.
ABC: Node 23468 has dup fanin 23453.
ABC: Node 23468 has dup fanin 23453.
ABC: Node 23469 has dup fanin 23453.
ABC: Node 23469 has dup fanin 23453.
ABC: Node 23470 has dup fanin 23453.
ABC: Node 23470 has dup fanin 23453.
ABC: Node 23471 has dup fanin 23453.
ABC: Node 23471 has dup fanin 23453.
ABC: Node 23472 has dup fanin 23453.
ABC: Node 23472 has dup fanin 23453.
ABC: Node 23473 has dup fanin 23453.
ABC: Node 23473 has dup fanin 23453.
ABC: Node 23474 has dup fanin 23453.
ABC: Node 23474 has dup fanin 23453.
ABC: Node 23475 has dup fanin 23453.
ABC: Node 23475 has dup fanin 23453.
ABC: Node 23476 has dup fanin 23453.
ABC: Node 23476 has dup fanin 23453.
ABC: Node 23477 has dup fanin 23453.
ABC: Node 23477 has dup fanin 23453.
ABC: Node 23478 has dup fanin 23453.
ABC: Node 23478 has dup fanin 23453.
ABC: Node 23479 has dup fanin 23453.
ABC: Node 23479 has dup fanin 23453.
ABC: Node 23480 has dup fanin 23453.
ABC: Node 23480 has dup fanin 23453.
ABC: Node 23481 has dup fanin 23453.
ABC: Node 23481 has dup fanin 23453.
ABC: Node 23482 has dup fanin 23453.
ABC: Node 23482 has dup fanin 23453.
ABC: Node 23483 has dup fanin 23453.
ABC: Node 23483 has dup fanin 23453.
ABC: Node 23484 has dup fanin 23453.
ABC: Node 23484 has dup fanin 23453.
ABC: Node 23485 has dup fanin 23453.
ABC: Node 23485 has dup fanin 23453.
ABC: Node 23491 has dup fanin 23490.
ABC: Node 23491 has dup fanin 23490.
ABC: Node 23492 has dup fanin 23490.
ABC: Node 23492 has dup fanin 23490.
ABC: Node 23493 has dup fanin 23490.
ABC: Node 23493 has dup fanin 23490.
ABC: Node 23494 has dup fanin 23490.
ABC: Node 23494 has dup fanin 23490.
ABC: Node 23495 has dup fanin 23490.
ABC: Node 23495 has dup fanin 23490.
ABC: Node 23496 has dup fanin 23490.
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ABC: Node 27910 has dup fanin 27901.
ABC: Node 27910 has dup fanin 27901.
ABC: Node 27911 has dup fanin 27901.
ABC: Node 27911 has dup fanin 27901.
ABC: Node 27912 has dup fanin 27901.
ABC: Node 27912 has dup fanin 27901.
ABC: Node 27913 has dup fanin 27901.
ABC: Node 27913 has dup fanin 27901.
ABC: Node 27914 has dup fanin 27901.
ABC: Node 27914 has dup fanin 27901.
ABC: Node 27915 has dup fanin 27901.
ABC: Node 27915 has dup fanin 27901.
ABC: Node 27916 has dup fanin 27901.
ABC: Node 27916 has dup fanin 27901.
ABC: Node 27917 has dup fanin 27901.
ABC: Node 27917 has dup fanin 27901.
ABC: Node 27918 has dup fanin 27901.
ABC: Node 27918 has dup fanin 27901.
ABC: Node 27919 has dup fanin 27901.
ABC: Node 27919 has dup fanin 27901.
ABC: Node 27920 has dup fanin 27901.
ABC: Node 27920 has dup fanin 27901.
ABC: Node 27921 has dup fanin 27901.
ABC: Node 27921 has dup fanin 27901.
ABC: Node 27922 has dup fanin 27901.
ABC: Node 27922 has dup fanin 27901.
ABC: Node 27923 has dup fanin 27901.
ABC: Node 27923 has dup fanin 27901.
ABC: Node 27924 has dup fanin 27901.
ABC: Node 27924 has dup fanin 27901.
ABC: Node 27925 has dup fanin 27901.
ABC: Node 27925 has dup fanin 27901.
ABC: Node 27926 has dup fanin 27901.
ABC: Node 27926 has dup fanin 27901.
ABC: Node 27927 has dup fanin 27901.
ABC: Node 27927 has dup fanin 27901.
ABC: Node 27928 has dup fanin 27901.
ABC: Node 27928 has dup fanin 27901.
ABC: Node 27929 has dup fanin 27901.
ABC: Node 27929 has dup fanin 27901.
ABC: Node 27930 has dup fanin 27901.
ABC: Node 27930 has dup fanin 27901.
ABC: Node 27931 has dup fanin 27901.
ABC: Node 27931 has dup fanin 27901.
ABC: Node 27932 has dup fanin 27901.
ABC: Node 27932 has dup fanin 27901.
ABC: Node 27933 has dup fanin 27901.
ABC: Node 27933 has dup fanin 27901.
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ABC: Node 27937 has dup fanin 27936.
ABC: Node 27937 has dup fanin 27936.
ABC: Node 27938 has dup fanin 27936.
ABC: Node 27938 has dup fanin 27936.
ABC: Node 27939 has dup fanin 27936.
ABC: Node 27939 has dup fanin 27936.
ABC: Node 27940 has dup fanin 27936.
ABC: Node 27940 has dup fanin 27936.
ABC: Node 27941 has dup fanin 27936.
ABC: Node 27941 has dup fanin 27936.
ABC: Node 27942 has dup fanin 27936.
ABC: Node 27942 has dup fanin 27936.
ABC: Node 27943 has dup fanin 27936.
ABC: Node 27943 has dup fanin 27936.
ABC: Node 27944 has dup fanin 27936.
ABC: Node 27944 has dup fanin 27936.
ABC: Node 27945 has dup fanin 27936.
ABC: Node 27945 has dup fanin 27936.
ABC: Node 27946 has dup fanin 27936.
ABC: Node 27946 has dup fanin 27936.
ABC: Node 27947 has dup fanin 27936.
ABC: Node 27947 has dup fanin 27936.
ABC: Node 27948 has dup fanin 27936.
ABC: Node 27948 has dup fanin 27936.
ABC: Node 27949 has dup fanin 27936.
ABC: Node 27949 has dup fanin 27936.
ABC: Node 27950 has dup fanin 27936.
ABC: Node 27950 has dup fanin 27936.
ABC: Node 27951 has dup fanin 27936.
ABC: Node 27951 has dup fanin 27936.
ABC: Node 27952 has dup fanin 27936.
ABC: Node 27952 has dup fanin 27936.
ABC: Node 27953 has dup fanin 27936.
ABC: Node 27953 has dup fanin 27936.
ABC: Node 27954 has dup fanin 27936.
ABC: Node 27954 has dup fanin 27936.
ABC: Node 27955 has dup fanin 27936.
ABC: Node 27955 has dup fanin 27936.
ABC: Node 27956 has dup fanin 27936.
ABC: Node 27956 has dup fanin 27936.
ABC: Node 27957 has dup fanin 27936.
ABC: Node 27957 has dup fanin 27936.
ABC: Node 27958 has dup fanin 27936.
ABC: Node 27958 has dup fanin 27936.
ABC: Node 27959 has dup fanin 27936.
ABC: Node 27959 has dup fanin 27936.
ABC: Node 27960 has dup fanin 27936.
ABC: Node 27960 has dup fanin 27936.
ABC: Node 27961 has dup fanin 27936.
ABC: Node 27961 has dup fanin 27936.
ABC: Node 27962 has dup fanin 27936.
ABC: Node 27962 has dup fanin 27936.
ABC: Node 27963 has dup fanin 27936.
ABC: Node 27963 has dup fanin 27936.
ABC: Node 27964 has dup fanin 27936.
ABC: Node 27964 has dup fanin 27936.
ABC: Node 27965 has dup fanin 27936.
ABC: Node 27965 has dup fanin 27936.
ABC: Node 27966 has dup fanin 27936.
ABC: Node 27966 has dup fanin 27936.
ABC: Node 27967 has dup fanin 27936.
ABC: Node 27967 has dup fanin 27936.
ABC: Node 27968 has dup fanin 27936.
ABC: Node 27968 has dup fanin 27936.
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ABC: Node 27970 has dup fanin 27969.
ABC: Node 27971 has dup fanin 27969.
ABC: Node 27971 has dup fanin 27969.
ABC: Node 27972 has dup fanin 27969.
ABC: Node 27972 has dup fanin 27969.
ABC: Node 27973 has dup fanin 27969.
ABC: Node 27973 has dup fanin 27969.
ABC: Node 27974 has dup fanin 27969.
ABC: Node 27974 has dup fanin 27969.
ABC: Node 27975 has dup fanin 27969.
ABC: Node 27975 has dup fanin 27969.
ABC: Node 27976 has dup fanin 27969.
ABC: Node 27976 has dup fanin 27969.
ABC: Node 27977 has dup fanin 27969.
ABC: Node 27977 has dup fanin 27969.
ABC: Node 27978 has dup fanin 27969.
ABC: Node 27978 has dup fanin 27969.
ABC: Node 27979 has dup fanin 27969.
ABC: Node 27979 has dup fanin 27969.
ABC: Node 27980 has dup fanin 27969.
ABC: Node 27980 has dup fanin 27969.
ABC: Node 27981 has dup fanin 27969.
ABC: Node 27981 has dup fanin 27969.
ABC: Node 27982 has dup fanin 27969.
ABC: Node 27982 has dup fanin 27969.
ABC: Node 27983 has dup fanin 27969.
ABC: Node 27983 has dup fanin 27969.
ABC: Node 27984 has dup fanin 27969.
ABC: Node 27984 has dup fanin 27969.
ABC: Node 27985 has dup fanin 27969.
ABC: Node 27985 has dup fanin 27969.
ABC: Node 27986 has dup fanin 27969.
ABC: Node 27986 has dup fanin 27969.
ABC: Node 27987 has dup fanin 27969.
ABC: Node 27987 has dup fanin 27969.
ABC: Node 27988 has dup fanin 27969.
ABC: Node 27988 has dup fanin 27969.
ABC: Node 27989 has dup fanin 27969.
ABC: Node 27989 has dup fanin 27969.
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ABC: Node 27990 has dup fanin 27969.
ABC: Node 27991 has dup fanin 27969.
ABC: Node 27991 has dup fanin 27969.
ABC: Node 27992 has dup fanin 27969.
ABC: Node 27992 has dup fanin 27969.
ABC: Node 27993 has dup fanin 27969.
ABC: Node 27993 has dup fanin 27969.
ABC: Node 27994 has dup fanin 27969.
ABC: Node 27994 has dup fanin 27969.
ABC: Node 27995 has dup fanin 27969.
ABC: Node 27995 has dup fanin 27969.
ABC: Node 27996 has dup fanin 27969.
ABC: Node 27996 has dup fanin 27969.
ABC: Node 27997 has dup fanin 27969.
ABC: Node 27997 has dup fanin 27969.
ABC: Node 27998 has dup fanin 27969.
ABC: Node 27998 has dup fanin 27969.
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ABC: Node 27999 has dup fanin 27969.
ABC: Node 28000 has dup fanin 27969.
ABC: Node 28000 has dup fanin 27969.
ABC: Node 28001 has dup fanin 27969.
ABC: Node 28001 has dup fanin 27969.
ABC: Node 28003 has dup fanin 28002.
ABC: Node 28003 has dup fanin 28002.
ABC: Node 28004 has dup fanin 28002.
ABC: Node 28004 has dup fanin 28002.
ABC: Node 28005 has dup fanin 28002.
ABC: Node 28005 has dup fanin 28002.
ABC: Node 28006 has dup fanin 28002.
ABC: Node 28006 has dup fanin 28002.
ABC: Node 28007 has dup fanin 28002.
ABC: Node 28007 has dup fanin 28002.
ABC: Node 28008 has dup fanin 28002.
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ABC: Node 28009 has dup fanin 28002.
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ABC: Node 28011 has dup fanin 28002.
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ABC: Node 28013 has dup fanin 28002.
ABC: Node 28014 has dup fanin 28002.
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ABC: Node 28015 has dup fanin 28002.
ABC: Node 28016 has dup fanin 28002.
ABC: Node 28016 has dup fanin 28002.
ABC: Node 28017 has dup fanin 28002.
ABC: Node 28017 has dup fanin 28002.
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ABC: Node 28018 has dup fanin 28002.
ABC: Node 28019 has dup fanin 28002.
ABC: Node 28019 has dup fanin 28002.
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ABC: Node 28020 has dup fanin 28002.
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ABC: Node 28022 has dup fanin 28002.
ABC: Node 28023 has dup fanin 28002.
ABC: Node 28023 has dup fanin 28002.
ABC: Node 28024 has dup fanin 28002.
ABC: Node 28024 has dup fanin 28002.
ABC: Node 28025 has dup fanin 28002.
ABC: Node 28025 has dup fanin 28002.
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ABC: Node 28027 has dup fanin 28002.
ABC: Node 28027 has dup fanin 28002.
ABC: Node 28028 has dup fanin 28002.
ABC: Node 28028 has dup fanin 28002.
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ABC: Node 28029 has dup fanin 28002.
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ABC: Node 28030 has dup fanin 28002.
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ABC: Node 28031 has dup fanin 28002.
ABC: Node 28032 has dup fanin 28002.
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ABC: Node 28033 has dup fanin 28002.
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ABC: Node 28036 has dup fanin 28035.
ABC: Node 28037 has dup fanin 28035.
ABC: Node 28037 has dup fanin 28035.
ABC: Node 28038 has dup fanin 28035.
ABC: Node 28038 has dup fanin 28035.
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ABC: Node 28039 has dup fanin 28035.
ABC: Node 28040 has dup fanin 28035.
ABC: Node 28040 has dup fanin 28035.
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ABC: Node 28041 has dup fanin 28035.
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ABC: Node 28042 has dup fanin 28035.
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ABC: Node 28043 has dup fanin 28035.
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ABC: Node 28044 has dup fanin 28035.
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ABC: Node 28045 has dup fanin 28035.
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ABC: Node 28046 has dup fanin 28035.
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ABC: Node 28048 has dup fanin 28035.
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ABC: Node 28049 has dup fanin 28035.
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ABC: Node 28050 has dup fanin 28035.
ABC: Node 28051 has dup fanin 28035.
ABC: Node 28051 has dup fanin 28035.
ABC: Node 28052 has dup fanin 28035.
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ABC: Node 28053 has dup fanin 28035.
ABC: Node 28053 has dup fanin 28035.
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ABC: Node 28054 has dup fanin 28035.
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ABC: Node 28055 has dup fanin 28035.
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ABC: Node 28057 has dup fanin 28035.
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ABC: Node 28059 has dup fanin 28035.
ABC: Node 28059 has dup fanin 28035.
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ABC: Node 28060 has dup fanin 28035.
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ABC: Node 28061 has dup fanin 28035.
ABC: Node 28062 has dup fanin 28035.
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ABC: Node 28063 has dup fanin 28035.
ABC: Node 28063 has dup fanin 28035.
ABC: Node 28064 has dup fanin 28035.
ABC: Node 28064 has dup fanin 28035.
ABC: Node 28065 has dup fanin 28035.
ABC: Node 28065 has dup fanin 28035.
ABC: Node 28066 has dup fanin 28035.
ABC: Node 28066 has dup fanin 28035.
ABC: Node 28067 has dup fanin 28035.
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ABC: Node 28069 has dup fanin 28068.
ABC: Node 28070 has dup fanin 28068.
ABC: Node 28070 has dup fanin 28068.
ABC: Node 28071 has dup fanin 28068.
ABC: Node 28071 has dup fanin 28068.
ABC: Node 28072 has dup fanin 28068.
ABC: Node 28072 has dup fanin 28068.
ABC: Node 28073 has dup fanin 28068.
ABC: Node 28073 has dup fanin 28068.
ABC: Node 28074 has dup fanin 28068.
ABC: Node 28074 has dup fanin 28068.
ABC: Node 28075 has dup fanin 28068.
ABC: Node 28075 has dup fanin 28068.
ABC: Node 28076 has dup fanin 28068.
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ABC: Node 28077 has dup fanin 28068.
ABC: Node 28077 has dup fanin 28068.
ABC: Node 28078 has dup fanin 28068.
ABC: Node 28078 has dup fanin 28068.
ABC: Node 28079 has dup fanin 28068.
ABC: Node 28079 has dup fanin 28068.
ABC: Node 28080 has dup fanin 28068.
ABC: Node 28080 has dup fanin 28068.
ABC: Node 28081 has dup fanin 28068.
ABC: Node 28081 has dup fanin 28068.
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ABC: Node 28082 has dup fanin 28068.
ABC: Node 28083 has dup fanin 28068.
ABC: Node 28083 has dup fanin 28068.
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ABC: Node 28084 has dup fanin 28068.
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ABC: Node 28086 has dup fanin 28068.
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ABC: Node 28087 has dup fanin 28068.
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ABC: Node 28099 has dup fanin 28068.
ABC: Node 28100 has dup fanin 28068.
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ABC: Node 28104 has dup fanin 28101.
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ABC: Node 28106 has dup fanin 28101.
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ABC: Node 28107 has dup fanin 28101.
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ABC: Node 28115 has dup fanin 28101.
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ABC: Node 28210 has dup fanin 28200.
ABC: Node 28211 has dup fanin 28200.
ABC: Node 28211 has dup fanin 28200.
ABC: Node 28212 has dup fanin 28200.
ABC: Node 28212 has dup fanin 28200.
ABC: Node 28213 has dup fanin 28200.
ABC: Node 28213 has dup fanin 28200.
ABC: Node 28214 has dup fanin 28200.
ABC: Node 28214 has dup fanin 28200.
ABC: Node 28215 has dup fanin 28200.
ABC: Node 28215 has dup fanin 28200.
ABC: Node 28216 has dup fanin 28200.
ABC: Node 28216 has dup fanin 28200.
ABC: Node 28217 has dup fanin 28200.
ABC: Node 28217 has dup fanin 28200.
ABC: Node 28218 has dup fanin 28200.
ABC: Node 28218 has dup fanin 28200.
ABC: Node 28219 has dup fanin 28200.
ABC: Node 28219 has dup fanin 28200.
ABC: Node 28220 has dup fanin 28200.
ABC: Node 28220 has dup fanin 28200.
ABC: Node 28221 has dup fanin 28200.
ABC: Node 28221 has dup fanin 28200.
ABC: Node 28222 has dup fanin 28200.
ABC: Node 28222 has dup fanin 28200.
ABC: Node 28223 has dup fanin 28200.
ABC: Node 28223 has dup fanin 28200.
ABC: Node 28224 has dup fanin 28200.
ABC: Node 28224 has dup fanin 28200.
ABC: Node 28225 has dup fanin 28200.
ABC: Node 28225 has dup fanin 28200.
ABC: Node 28226 has dup fanin 28200.
ABC: Node 28226 has dup fanin 28200.
ABC: Node 28227 has dup fanin 28200.
ABC: Node 28227 has dup fanin 28200.
ABC: Node 28228 has dup fanin 28200.
ABC: Node 28228 has dup fanin 28200.
ABC: Node 28229 has dup fanin 28200.
ABC: Node 28229 has dup fanin 28200.
ABC: Node 28230 has dup fanin 28200.
ABC: Node 28230 has dup fanin 28200.
ABC: Node 28231 has dup fanin 28200.
ABC: Node 28231 has dup fanin 28200.
ABC: Node 28232 has dup fanin 28200.
ABC: Node 28232 has dup fanin 28200.
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ABC: Node 28238 has dup fanin 10412.
ABC: Node 28244 has dup fanin 28243.
ABC: Node 28244 has dup fanin 28243.
ABC: Node 28245 has dup fanin 28243.
ABC: Node 28245 has dup fanin 28243.
ABC: Node 28246 has dup fanin 28243.
ABC: Node 28246 has dup fanin 28243.
ABC: Node 28247 has dup fanin 28243.
ABC: Node 28247 has dup fanin 28243.
ABC: Node 28248 has dup fanin 28243.
ABC: Node 28248 has dup fanin 28243.
ABC: Node 28249 has dup fanin 28243.
ABC: Node 28249 has dup fanin 28243.
ABC: Node 28250 has dup fanin 28243.
ABC: Node 28250 has dup fanin 28243.
ABC: Node 28251 has dup fanin 28243.
ABC: Node 28251 has dup fanin 28243.
ABC: Node 28252 has dup fanin 28243.
ABC: Node 28252 has dup fanin 28243.
ABC: Node 28253 has dup fanin 28243.
ABC: Node 28253 has dup fanin 28243.
ABC: Node 28254 has dup fanin 28243.
ABC: Node 28254 has dup fanin 28243.
ABC: Node 28255 has dup fanin 28243.
ABC: Node 28255 has dup fanin 28243.
ABC: Node 28256 has dup fanin 28243.
ABC: Node 28256 has dup fanin 28243.
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ABC: Node 28257 has dup fanin 28243.
ABC: Node 28258 has dup fanin 28243.
ABC: Node 28258 has dup fanin 28243.
ABC: Node 28259 has dup fanin 28243.
ABC: Node 28259 has dup fanin 28243.
ABC: Node 28260 has dup fanin 28243.
ABC: Node 28260 has dup fanin 28243.
ABC: Node 28261 has dup fanin 28243.
ABC: Node 28261 has dup fanin 28243.
ABC: Node 28262 has dup fanin 28243.
ABC: Node 28262 has dup fanin 28243.
ABC: Node 28263 has dup fanin 28243.
ABC: Node 28263 has dup fanin 28243.
ABC: Node 28264 has dup fanin 28243.
ABC: Node 28264 has dup fanin 28243.
ABC: Node 28265 has dup fanin 28243.
ABC: Node 28265 has dup fanin 28243.
ABC: Node 28266 has dup fanin 28243.
ABC: Node 28266 has dup fanin 28243.
ABC: Node 28267 has dup fanin 28243.
ABC: Node 28267 has dup fanin 28243.
ABC: Node 28268 has dup fanin 28243.
ABC: Node 28268 has dup fanin 28243.
ABC: Node 28269 has dup fanin 28243.
ABC: Node 28269 has dup fanin 28243.
ABC: Node 28270 has dup fanin 28243.
ABC: Node 28270 has dup fanin 28243.
ABC: Node 28271 has dup fanin 28243.
ABC: Node 28271 has dup fanin 28243.
ABC: Node 28272 has dup fanin 28243.
ABC: Node 28272 has dup fanin 28243.
ABC: Node 28273 has dup fanin 28243.
ABC: Node 28273 has dup fanin 28243.
ABC: Node 28274 has dup fanin 28243.
ABC: Node 28274 has dup fanin 28243.
ABC: Node 28275 has dup fanin 28243.
ABC: Node 28275 has dup fanin 28243.
ABC: Node 28277 has dup fanin 28276.
ABC: Node 28277 has dup fanin 28276.
ABC: Node 28278 has dup fanin 28276.
ABC: Node 28278 has dup fanin 28276.
ABC: Node 28279 has dup fanin 28276.
ABC: Node 28279 has dup fanin 28276.
ABC: Node 28280 has dup fanin 28276.
ABC: Node 28280 has dup fanin 28276.
ABC: Node 28281 has dup fanin 28276.
ABC: Node 28281 has dup fanin 28276.
ABC: Node 28282 has dup fanin 28276.
ABC: Node 28282 has dup fanin 28276.
ABC: Node 28283 has dup fanin 28276.
ABC: Node 28283 has dup fanin 28276.
ABC: Node 28284 has dup fanin 28276.
ABC: Node 28284 has dup fanin 28276.
ABC: Node 28285 has dup fanin 28276.
ABC: Node 28285 has dup fanin 28276.
ABC: Node 28286 has dup fanin 28276.
ABC: Node 28286 has dup fanin 28276.
ABC: Node 28287 has dup fanin 28276.
ABC: Node 28287 has dup fanin 28276.
ABC: Node 28288 has dup fanin 28276.
ABC: Node 28288 has dup fanin 28276.
ABC: Node 28289 has dup fanin 28276.
ABC: Node 28289 has dup fanin 28276.
ABC: Node 28290 has dup fanin 28276.
ABC: Node 28290 has dup fanin 28276.
ABC: Node 28291 has dup fanin 28276.
ABC: Node 28291 has dup fanin 28276.
ABC: Node 28292 has dup fanin 28276.
ABC: Node 28292 has dup fanin 28276.
ABC: Node 28293 has dup fanin 28276.
ABC: Node 28293 has dup fanin 28276.
ABC: Node 28294 has dup fanin 28276.
ABC: Node 28294 has dup fanin 28276.
ABC: Node 28295 has dup fanin 28276.
ABC: Node 28295 has dup fanin 28276.
ABC: Node 28296 has dup fanin 28276.
ABC: Node 28296 has dup fanin 28276.
ABC: Node 28297 has dup fanin 28276.
ABC: Node 28297 has dup fanin 28276.
ABC: Node 28298 has dup fanin 28276.
ABC: Node 28298 has dup fanin 28276.
ABC: Node 28299 has dup fanin 28276.
ABC: Node 28299 has dup fanin 28276.
ABC: Node 28300 has dup fanin 28276.
ABC: Node 28300 has dup fanin 28276.
ABC: Node 28301 has dup fanin 28276.
ABC: Node 28301 has dup fanin 28276.
ABC: Node 28302 has dup fanin 28276.
ABC: Node 28302 has dup fanin 28276.
ABC: Node 28303 has dup fanin 28276.
ABC: Node 28303 has dup fanin 28276.
ABC: Node 28304 has dup fanin 28276.
ABC: Node 28304 has dup fanin 28276.
ABC: Node 28305 has dup fanin 28276.
ABC: Node 28305 has dup fanin 28276.
ABC: Node 28306 has dup fanin 28276.
ABC: Node 28306 has dup fanin 28276.
ABC: Node 28307 has dup fanin 28276.
ABC: Node 28307 has dup fanin 28276.
ABC: Node 28308 has dup fanin 28276.
ABC: Node 28308 has dup fanin 28276.
ABC: Node 28310 has dup fanin 28309.
ABC: Node 28310 has dup fanin 28309.
ABC: Node 28311 has dup fanin 28309.
ABC: Node 28311 has dup fanin 28309.
ABC: Node 28312 has dup fanin 28309.
ABC: Node 28312 has dup fanin 28309.
ABC: Node 28313 has dup fanin 28309.
ABC: Node 28313 has dup fanin 28309.
ABC: Node 28314 has dup fanin 28309.
ABC: Node 28314 has dup fanin 28309.
ABC: Node 28315 has dup fanin 28309.
ABC: Node 28315 has dup fanin 28309.
ABC: Node 28316 has dup fanin 28309.
ABC: Node 28316 has dup fanin 28309.
ABC: Node 28317 has dup fanin 28309.
ABC: Node 28317 has dup fanin 28309.
ABC: Node 28318 has dup fanin 28309.
ABC: Node 28318 has dup fanin 28309.
ABC: Node 28319 has dup fanin 28309.
ABC: Node 28319 has dup fanin 28309.
ABC: Node 28320 has dup fanin 28309.
ABC: Node 28320 has dup fanin 28309.
ABC: Node 28321 has dup fanin 28309.
ABC: Node 28321 has dup fanin 28309.
ABC: Node 28322 has dup fanin 28309.
ABC: Node 28322 has dup fanin 28309.
ABC: Node 28323 has dup fanin 28309.
ABC: Node 28323 has dup fanin 28309.
ABC: Node 28324 has dup fanin 28309.
ABC: Node 28324 has dup fanin 28309.
ABC: Node 28325 has dup fanin 28309.
ABC: Node 28325 has dup fanin 28309.
ABC: Node 28326 has dup fanin 28309.
ABC: Node 28326 has dup fanin 28309.
ABC: Node 28327 has dup fanin 28309.
ABC: Node 28327 has dup fanin 28309.
ABC: Node 28328 has dup fanin 28309.
ABC: Node 28328 has dup fanin 28309.
ABC: Node 28329 has dup fanin 28309.
ABC: Node 28329 has dup fanin 28309.
ABC: Node 28330 has dup fanin 28309.
ABC: Node 28330 has dup fanin 28309.
ABC: Node 28331 has dup fanin 28309.
ABC: Node 28331 has dup fanin 28309.
ABC: Node 28332 has dup fanin 28309.
ABC: Node 28332 has dup fanin 28309.
ABC: Node 28333 has dup fanin 28309.
ABC: Node 28333 has dup fanin 28309.
ABC: Node 28334 has dup fanin 28309.
ABC: Node 28334 has dup fanin 28309.
ABC: Node 28335 has dup fanin 28309.
ABC: Node 28335 has dup fanin 28309.
ABC: Node 28336 has dup fanin 28309.
ABC: Node 28336 has dup fanin 28309.
ABC: Node 28337 has dup fanin 28309.
ABC: Node 28337 has dup fanin 28309.
ABC: Node 28338 has dup fanin 28309.
ABC: Node 28338 has dup fanin 28309.
ABC: Node 28339 has dup fanin 28309.
ABC: Node 28339 has dup fanin 28309.
ABC: Node 28340 has dup fanin 28309.
ABC: Node 28340 has dup fanin 28309.
ABC: Node 28341 has dup fanin 28309.
ABC: Node 28341 has dup fanin 28309.
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ABC: Node 28343 has dup fanin 28342.
ABC: Node 28344 has dup fanin 28342.
ABC: Node 28344 has dup fanin 28342.
ABC: Node 28345 has dup fanin 28342.
ABC: Node 28345 has dup fanin 28342.
ABC: Node 28346 has dup fanin 28342.
ABC: Node 28346 has dup fanin 28342.
ABC: Node 28347 has dup fanin 28342.
ABC: Node 28347 has dup fanin 28342.
ABC: Node 28348 has dup fanin 28342.
ABC: Node 28348 has dup fanin 28342.
ABC: Node 28349 has dup fanin 28342.
ABC: Node 28349 has dup fanin 28342.
ABC: Node 28350 has dup fanin 28342.
ABC: Node 28350 has dup fanin 28342.
ABC: Node 28351 has dup fanin 28342.
ABC: Node 28351 has dup fanin 28342.
ABC: Node 28352 has dup fanin 28342.
ABC: Node 28352 has dup fanin 28342.
ABC: Node 28353 has dup fanin 28342.
ABC: Node 28353 has dup fanin 28342.
ABC: Node 28354 has dup fanin 28342.
ABC: Node 28354 has dup fanin 28342.
ABC: Node 28355 has dup fanin 28342.
ABC: Node 28355 has dup fanin 28342.
ABC: Node 28356 has dup fanin 28342.
ABC: Node 28356 has dup fanin 28342.
ABC: Node 28357 has dup fanin 28342.
ABC: Node 28357 has dup fanin 28342.
ABC: Node 28358 has dup fanin 28342.
ABC: Node 28358 has dup fanin 28342.
ABC: Node 28359 has dup fanin 28342.
ABC: Node 28359 has dup fanin 28342.
ABC: Node 28360 has dup fanin 28342.
ABC: Node 28360 has dup fanin 28342.
ABC: Node 28361 has dup fanin 28342.
ABC: Node 28361 has dup fanin 28342.
ABC: Node 28362 has dup fanin 28342.
ABC: Node 28362 has dup fanin 28342.
ABC: Node 28363 has dup fanin 28342.
ABC: Node 28363 has dup fanin 28342.
ABC: Node 28364 has dup fanin 28342.
ABC: Node 28364 has dup fanin 28342.
ABC: Node 28365 has dup fanin 28342.
ABC: Node 28365 has dup fanin 28342.
ABC: Node 28366 has dup fanin 28342.
ABC: Node 28366 has dup fanin 28342.
ABC: Node 28367 has dup fanin 28342.
ABC: Node 28367 has dup fanin 28342.
ABC: Node 28368 has dup fanin 28342.
ABC: Node 28368 has dup fanin 28342.
ABC: Node 28369 has dup fanin 28342.
ABC: Node 28369 has dup fanin 28342.
ABC: Node 28370 has dup fanin 28342.
ABC: Node 28370 has dup fanin 28342.
ABC: Node 28371 has dup fanin 28342.
ABC: Node 28371 has dup fanin 28342.
ABC: Node 28372 has dup fanin 28342.
ABC: Node 28372 has dup fanin 28342.
ABC: Node 28373 has dup fanin 28342.
ABC: Node 28373 has dup fanin 28342.
ABC: Node 28374 has dup fanin 28342.
ABC: Node 28374 has dup fanin 28342.
ABC: Node 28376 has dup fanin 28375.
ABC: Node 28376 has dup fanin 28375.
ABC: Node 28377 has dup fanin 28375.
ABC: Node 28377 has dup fanin 28375.
ABC: Node 28378 has dup fanin 28375.
ABC: Node 28378 has dup fanin 28375.
ABC: Node 28379 has dup fanin 28375.
ABC: Node 28379 has dup fanin 28375.
ABC: Node 28380 has dup fanin 28375.
ABC: Node 28380 has dup fanin 28375.
ABC: Node 28381 has dup fanin 28375.
ABC: Node 28381 has dup fanin 28375.
ABC: Node 28382 has dup fanin 28375.
ABC: Node 28382 has dup fanin 28375.
ABC: Node 28383 has dup fanin 28375.
ABC: Node 28383 has dup fanin 28375.
ABC: Node 28384 has dup fanin 28375.
ABC: Node 28384 has dup fanin 28375.
ABC: Node 28385 has dup fanin 28375.
ABC: Node 28385 has dup fanin 28375.
ABC: Node 28386 has dup fanin 28375.
ABC: Node 28386 has dup fanin 28375.
ABC: Node 28387 has dup fanin 28375.
ABC: Node 28387 has dup fanin 28375.
ABC: Node 28388 has dup fanin 28375.
ABC: Node 28388 has dup fanin 28375.
ABC: Node 28389 has dup fanin 28375.
ABC: Node 28389 has dup fanin 28375.
ABC: Node 28390 has dup fanin 28375.
ABC: Node 28390 has dup fanin 28375.
ABC: Node 28391 has dup fanin 28375.
ABC: Node 28391 has dup fanin 28375.
ABC: Node 28392 has dup fanin 28375.
ABC: Node 28392 has dup fanin 28375.
ABC: Node 28393 has dup fanin 28375.
ABC: Node 28393 has dup fanin 28375.
ABC: Node 28394 has dup fanin 28375.
ABC: Node 28394 has dup fanin 28375.
ABC: Node 28395 has dup fanin 28375.
ABC: Node 28395 has dup fanin 28375.
ABC: Node 28396 has dup fanin 28375.
ABC: Node 28396 has dup fanin 28375.
ABC: Node 28397 has dup fanin 28375.
ABC: Node 28397 has dup fanin 28375.
ABC: Node 28398 has dup fanin 28375.
ABC: Node 28398 has dup fanin 28375.
ABC: Node 28399 has dup fanin 28375.
ABC: Node 28399 has dup fanin 28375.
ABC: Node 28400 has dup fanin 28375.
ABC: Node 28400 has dup fanin 28375.
ABC: Node 28401 has dup fanin 28375.
ABC: Node 28401 has dup fanin 28375.
ABC: Node 28402 has dup fanin 28375.
ABC: Node 28402 has dup fanin 28375.
ABC: Node 28403 has dup fanin 28375.
ABC: Node 28403 has dup fanin 28375.
ABC: Node 28404 has dup fanin 28375.
ABC: Node 28404 has dup fanin 28375.
ABC: Node 28405 has dup fanin 28375.
ABC: Node 28405 has dup fanin 28375.
ABC: Node 28406 has dup fanin 28375.
ABC: Node 28406 has dup fanin 28375.
ABC: Node 28407 has dup fanin 28375.
ABC: Node 28407 has dup fanin 28375.
ABC: Node 28409 has dup fanin 28408.
ABC: Node 28409 has dup fanin 28408.
ABC: Node 28410 has dup fanin 28408.
ABC: Node 28410 has dup fanin 28408.
ABC: Node 28411 has dup fanin 28408.
ABC: Node 28411 has dup fanin 28408.
ABC: Node 28412 has dup fanin 28408.
ABC: Node 28412 has dup fanin 28408.
ABC: Node 28413 has dup fanin 28408.
ABC: Node 28413 has dup fanin 28408.
ABC: Node 28414 has dup fanin 28408.
ABC: Node 28414 has dup fanin 28408.
ABC: Node 28415 has dup fanin 28408.
ABC: Node 28415 has dup fanin 28408.
ABC: Node 28416 has dup fanin 28408.
ABC: Node 28416 has dup fanin 28408.
ABC: Node 28417 has dup fanin 28408.
ABC: Node 28417 has dup fanin 28408.
ABC: Node 28418 has dup fanin 28408.
ABC: Node 28418 has dup fanin 28408.
ABC: Node 28419 has dup fanin 28408.
ABC: Node 28419 has dup fanin 28408.
ABC: Node 28420 has dup fanin 28408.
ABC: Node 28420 has dup fanin 28408.
ABC: Node 28421 has dup fanin 28408.
ABC: Node 28421 has dup fanin 28408.
ABC: Node 28422 has dup fanin 28408.
ABC: Node 28422 has dup fanin 28408.
ABC: Node 28423 has dup fanin 28408.
ABC: Node 28423 has dup fanin 28408.
ABC: Node 28424 has dup fanin 28408.
ABC: Node 28424 has dup fanin 28408.
ABC: Node 28425 has dup fanin 28408.
ABC: Node 28425 has dup fanin 28408.
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ABC: Node 28426 has dup fanin 28408.
ABC: Node 28427 has dup fanin 28408.
ABC: Node 28427 has dup fanin 28408.
ABC: Node 28428 has dup fanin 28408.
ABC: Node 28428 has dup fanin 28408.
ABC: Node 28429 has dup fanin 28408.
ABC: Node 28429 has dup fanin 28408.
ABC: Node 28430 has dup fanin 28408.
ABC: Node 28430 has dup fanin 28408.
ABC: Node 28431 has dup fanin 28408.
ABC: Node 28431 has dup fanin 28408.
ABC: Node 28432 has dup fanin 28408.
ABC: Node 28432 has dup fanin 28408.
ABC: Node 28433 has dup fanin 28408.
ABC: Node 28433 has dup fanin 28408.
ABC: Node 28434 has dup fanin 28408.
ABC: Node 28434 has dup fanin 28408.
ABC: Node 28435 has dup fanin 28408.
ABC: Node 28435 has dup fanin 28408.
ABC: Node 28436 has dup fanin 28408.
ABC: Node 28436 has dup fanin 28408.
ABC: Node 28437 has dup fanin 28408.
ABC: Node 28437 has dup fanin 28408.
ABC: Node 28438 has dup fanin 28408.
ABC: Node 28438 has dup fanin 28408.
ABC: Node 28439 has dup fanin 28408.
ABC: Node 28439 has dup fanin 28408.
ABC: Node 28440 has dup fanin 28408.
ABC: Node 28440 has dup fanin 28408.
ABC: Node 28442 has dup fanin 28441.
ABC: Node 28442 has dup fanin 28441.
ABC: Node 28443 has dup fanin 28441.
ABC: Node 28443 has dup fanin 28441.
ABC: Node 28444 has dup fanin 28441.
ABC: Node 28444 has dup fanin 28441.
ABC: Node 28445 has dup fanin 28441.
ABC: Node 28445 has dup fanin 28441.
ABC: Node 28446 has dup fanin 28441.
ABC: Node 28446 has dup fanin 28441.
ABC: Node 28447 has dup fanin 28441.
ABC: Node 28447 has dup fanin 28441.
ABC: Node 28448 has dup fanin 28441.
ABC: Node 28448 has dup fanin 28441.
ABC: Node 28449 has dup fanin 28441.
ABC: Node 28449 has dup fanin 28441.
ABC: Node 28450 has dup fanin 28441.
ABC: Node 28450 has dup fanin 28441.
ABC: Node 28451 has dup fanin 28441.
ABC: Node 28451 has dup fanin 28441.
ABC: Node 28452 has dup fanin 28441.
ABC: Node 28452 has dup fanin 28441.
ABC: Node 28453 has dup fanin 28441.
ABC: Node 28453 has dup fanin 28441.
ABC: Node 28454 has dup fanin 28441.
ABC: Node 28454 has dup fanin 28441.
ABC: Node 28455 has dup fanin 28441.
ABC: Node 28455 has dup fanin 28441.
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ABC: Node 28456 has dup fanin 28441.
ABC: Node 28457 has dup fanin 28441.
ABC: Node 28457 has dup fanin 28441.
ABC: Node 28458 has dup fanin 28441.
ABC: Node 28458 has dup fanin 28441.
ABC: Node 28459 has dup fanin 28441.
ABC: Node 28459 has dup fanin 28441.
ABC: Node 28460 has dup fanin 28441.
ABC: Node 28460 has dup fanin 28441.
ABC: Node 28461 has dup fanin 28441.
ABC: Node 28461 has dup fanin 28441.
ABC: Node 28462 has dup fanin 28441.
ABC: Node 28462 has dup fanin 28441.
ABC: Node 28463 has dup fanin 28441.
ABC: Node 28463 has dup fanin 28441.
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ABC: Node 28464 has dup fanin 28441.
ABC: Node 28465 has dup fanin 28441.
ABC: Node 28465 has dup fanin 28441.
ABC: Node 28466 has dup fanin 28441.
ABC: Node 28466 has dup fanin 28441.
ABC: Node 28467 has dup fanin 28441.
ABC: Node 28467 has dup fanin 28441.
ABC: Node 28468 has dup fanin 28441.
ABC: Node 28468 has dup fanin 28441.
ABC: Node 28469 has dup fanin 28441.
ABC: Node 28469 has dup fanin 28441.
ABC: Node 28470 has dup fanin 28441.
ABC: Node 28470 has dup fanin 28441.
ABC: Node 28471 has dup fanin 28441.
ABC: Node 28471 has dup fanin 28441.
ABC: Node 28472 has dup fanin 28441.
ABC: Node 28472 has dup fanin 28441.
ABC: Node 28473 has dup fanin 28441.
ABC: Node 28473 has dup fanin 28441.
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ABC: Node 28476 has dup fanin 28474.
ABC: Node 28477 has dup fanin 28474.
ABC: Node 28477 has dup fanin 28474.
ABC: Node 28478 has dup fanin 28474.
ABC: Node 28478 has dup fanin 28474.
ABC: Node 28479 has dup fanin 28474.
ABC: Node 28479 has dup fanin 28474.
ABC: Node 28480 has dup fanin 28474.
ABC: Node 28480 has dup fanin 28474.
ABC: Node 28481 has dup fanin 28474.
ABC: Node 28481 has dup fanin 28474.
ABC: Node 28482 has dup fanin 28474.
ABC: Node 28482 has dup fanin 28474.
ABC: Node 28483 has dup fanin 28474.
ABC: Node 28483 has dup fanin 28474.
ABC: Node 28484 has dup fanin 28474.
ABC: Node 28484 has dup fanin 28474.
ABC: Node 28485 has dup fanin 28474.
ABC: Node 28485 has dup fanin 28474.
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ABC: Node 28486 has dup fanin 28474.
ABC: Node 28487 has dup fanin 28474.
ABC: Node 28487 has dup fanin 28474.
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ABC: Node 28488 has dup fanin 28474.
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ABC: Node 28489 has dup fanin 28474.
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ABC: Node 28490 has dup fanin 28474.
ABC: Node 28491 has dup fanin 28474.
ABC: Node 28491 has dup fanin 28474.
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ABC: Node 28492 has dup fanin 28474.
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ABC: Node 28493 has dup fanin 28474.
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ABC: Node 28494 has dup fanin 28474.
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ABC: Node 28497 has dup fanin 28474.
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ABC: Node 28502 has dup fanin 28475.
ABC: Node 28503 has dup fanin 28475.
ABC: Node 28503 has dup fanin 28475.
ABC: Node 28504 has dup fanin 28475.
ABC: Node 28504 has dup fanin 28475.
ABC: Node 28507 has dup fanin 28475.
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ABC: Node 28510 has dup fanin 28509.
ABC: Node 28510 has dup fanin 28509.
ABC: Node 28511 has dup fanin 28509.
ABC: Node 28511 has dup fanin 28509.
ABC: Node 28512 has dup fanin 28509.
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ABC: Node 28516 has dup fanin 28509.
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ABC: Node 28521 has dup fanin 28509.
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ABC: Node 28522 has dup fanin 28509.
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ABC: Node 28523 has dup fanin 28509.
ABC: Node 28523 has dup fanin 28509.
ABC: Node 28524 has dup fanin 28509.
ABC: Node 28524 has dup fanin 28509.
ABC: Node 28525 has dup fanin 28509.
ABC: Node 28525 has dup fanin 28509.
ABC: Node 28526 has dup fanin 28509.
ABC: Node 28526 has dup fanin 28509.
ABC: Node 28527 has dup fanin 28509.
ABC: Node 28527 has dup fanin 28509.
ABC: Node 28528 has dup fanin 28509.
ABC: Node 28528 has dup fanin 28509.
ABC: Node 28529 has dup fanin 28509.
ABC: Node 28529 has dup fanin 28509.
ABC: Node 28530 has dup fanin 28509.
ABC: Node 28530 has dup fanin 28509.
ABC: Node 28531 has dup fanin 28509.
ABC: Node 28531 has dup fanin 28509.
ABC: Node 28532 has dup fanin 28509.
ABC: Node 28532 has dup fanin 28509.
ABC: Node 28533 has dup fanin 28509.
ABC: Node 28533 has dup fanin 28509.
ABC: Node 28534 has dup fanin 28509.
ABC: Node 28534 has dup fanin 28509.
ABC: Node 28535 has dup fanin 28509.
ABC: Node 28535 has dup fanin 28509.
ABC: Node 28536 has dup fanin 28509.
ABC: Node 28536 has dup fanin 28509.
ABC: Node 28537 has dup fanin 28509.
ABC: Node 28537 has dup fanin 28509.
ABC: Node 28538 has dup fanin 28509.
ABC: Node 28538 has dup fanin 28509.
ABC: Node 28539 has dup fanin 28509.
ABC: Node 28539 has dup fanin 28509.
ABC: Node 28540 has dup fanin 28509.
ABC: Node 28540 has dup fanin 28509.
ABC: Node 28541 has dup fanin 28509.
ABC: Node 28541 has dup fanin 28509.
ABC: Node 28543 has dup fanin 28542.
ABC: Node 28543 has dup fanin 28542.
ABC: Node 28544 has dup fanin 28542.
ABC: Node 28544 has dup fanin 28542.
ABC: Node 28545 has dup fanin 28542.
ABC: Node 28545 has dup fanin 28542.
ABC: Node 28546 has dup fanin 28542.
ABC: Node 28546 has dup fanin 28542.
ABC: Node 28547 has dup fanin 28542.
ABC: Node 28547 has dup fanin 28542.
ABC: Node 28548 has dup fanin 28542.
ABC: Node 28548 has dup fanin 28542.
ABC: Node 28549 has dup fanin 28542.
ABC: Node 28549 has dup fanin 28542.
ABC: Node 28550 has dup fanin 28542.
ABC: Node 28550 has dup fanin 28542.
ABC: Node 28551 has dup fanin 28542.
ABC: Node 28551 has dup fanin 28542.
ABC: Node 28552 has dup fanin 28542.
ABC: Node 28552 has dup fanin 28542.
ABC: Node 28553 has dup fanin 28542.
ABC: Node 28553 has dup fanin 28542.
ABC: Node 28554 has dup fanin 28542.
ABC: Node 28554 has dup fanin 28542.
ABC: Node 28555 has dup fanin 28542.
ABC: Node 28555 has dup fanin 28542.
ABC: Node 28556 has dup fanin 28542.
ABC: Node 28556 has dup fanin 28542.
ABC: Node 28557 has dup fanin 28542.
ABC: Node 28557 has dup fanin 28542.
ABC: Node 28558 has dup fanin 28542.
ABC: Node 28558 has dup fanin 28542.
ABC: Node 28559 has dup fanin 28542.
ABC: Node 28559 has dup fanin 28542.
ABC: Node 28560 has dup fanin 28542.
ABC: Node 28560 has dup fanin 28542.
ABC: Node 28561 has dup fanin 28542.
ABC: Node 28561 has dup fanin 28542.
ABC: Node 28562 has dup fanin 28542.
ABC: Node 28562 has dup fanin 28542.
ABC: Node 28563 has dup fanin 28542.
ABC: Node 28563 has dup fanin 28542.
ABC: Node 28564 has dup fanin 28542.
ABC: Node 28564 has dup fanin 28542.
ABC: Node 28565 has dup fanin 28542.
ABC: Node 28565 has dup fanin 28542.
ABC: Node 28566 has dup fanin 28542.
ABC: Node 28566 has dup fanin 28542.
ABC: Node 28567 has dup fanin 28542.
ABC: Node 28567 has dup fanin 28542.
ABC: Node 28568 has dup fanin 28542.
ABC: Node 28568 has dup fanin 28542.
ABC: Node 28569 has dup fanin 28542.
ABC: Node 28569 has dup fanin 28542.
ABC: Node 28570 has dup fanin 28542.
ABC: Node 28570 has dup fanin 28542.
ABC: Node 28571 has dup fanin 28542.
ABC: Node 28571 has dup fanin 28542.
ABC: Node 28572 has dup fanin 28542.
ABC: Node 28572 has dup fanin 28542.
ABC: Node 28573 has dup fanin 28542.
ABC: Node 28573 has dup fanin 28542.
ABC: Node 28574 has dup fanin 28542.
ABC: Node 28574 has dup fanin 28542.
ABC: Node 28576 has dup fanin 19317.
ABC: Node 28576 has dup fanin 19317.
ABC: Node 28619 has dup fanin 19317.
ABC: Node 28619 has dup fanin 19317.
ABC: Node 28622 has dup fanin 28621.
ABC: Node 28622 has dup fanin 28621.
ABC: Node 28623 has dup fanin 28621.
ABC: Node 28623 has dup fanin 28621.
ABC: Node 28624 has dup fanin 28621.
ABC: Node 28624 has dup fanin 28621.
ABC: Node 28625 has dup fanin 28621.
ABC: Node 28625 has dup fanin 28621.
ABC: Node 28626 has dup fanin 28621.
ABC: Node 28626 has dup fanin 28621.
ABC: Node 28627 has dup fanin 28621.
ABC: Node 28627 has dup fanin 28621.
ABC: Node 28628 has dup fanin 28621.
ABC: Node 28628 has dup fanin 28621.
ABC: Node 28629 has dup fanin 28621.
ABC: Node 28629 has dup fanin 28621.
ABC: Node 28632 has dup fanin 28631.
ABC: Node 28632 has dup fanin 28631.
ABC: Node 28633 has dup fanin 28631.
ABC: Node 28633 has dup fanin 28631.
ABC: Node 28634 has dup fanin 28631.
ABC: Node 28634 has dup fanin 28631.
ABC: Node 28635 has dup fanin 28631.
ABC: Node 28635 has dup fanin 28631.
ABC: Node 28636 has dup fanin 28631.
ABC: Node 28636 has dup fanin 28631.
ABC: Node 28637 has dup fanin 28631.
ABC: Node 28637 has dup fanin 28631.
ABC: Node 28638 has dup fanin 28631.
ABC: Node 28638 has dup fanin 28631.
ABC: Node 28639 has dup fanin 28631.
ABC: Node 28639 has dup fanin 28631.
ABC: Node 28670 has dup fanin 28669.
ABC: Node 28670 has dup fanin 28669.
ABC: Node 28671 has dup fanin 28669.
ABC: Node 28671 has dup fanin 28669.
ABC: Node 28672 has dup fanin 28669.
ABC: Node 28672 has dup fanin 28669.
ABC: Node 28673 has dup fanin 28669.
ABC: Node 28673 has dup fanin 28669.
ABC: Node 28674 has dup fanin 28669.
ABC: Node 28674 has dup fanin 28669.
ABC: Node 28675 has dup fanin 28669.
ABC: Node 28675 has dup fanin 28669.
ABC: Node 28676 has dup fanin 28669.
ABC: Node 28676 has dup fanin 28669.
ABC: Node 28677 has dup fanin 28669.
ABC: Node 28677 has dup fanin 28669.
ABC: Node 28704 has dup fanin 19318.
ABC: Node 28704 has dup fanin 19318.
ABC: Node 28705 has dup fanin 19318.
ABC: Node 28705 has dup fanin 19318.
ABC: Node 28706 has dup fanin 19318.
ABC: Node 28706 has dup fanin 19318.
ABC: Node 28707 has dup fanin 19318.
ABC: Node 28707 has dup fanin 19318.
ABC: Node 28708 has dup fanin 19318.
ABC: Node 28708 has dup fanin 19318.
ABC: Node 28709 has dup fanin 19318.
ABC: Node 28709 has dup fanin 19318.
ABC: Node 28710 has dup fanin 19318.
ABC: Node 28710 has dup fanin 19318.
ABC: Node 28711 has dup fanin 19318.
ABC: Node 28711 has dup fanin 19318.
ABC: Node 28712 has dup fanin 19318.
ABC: Node 28712 has dup fanin 19318.
ABC: Node 28713 has dup fanin 19318.
ABC: Node 28713 has dup fanin 19318.
ABC: Node 28714 has dup fanin 19318.
ABC: Node 28714 has dup fanin 19318.
ABC: Node 28715 has dup fanin 19318.
ABC: Node 28715 has dup fanin 19318.
ABC: Node 28716 has dup fanin 19318.
ABC: Node 28716 has dup fanin 19318.
ABC: Node 28717 has dup fanin 19318.
ABC: Node 28717 has dup fanin 19318.
ABC: Node 28718 has dup fanin 19318.
ABC: Node 28718 has dup fanin 19318.
ABC: Node 28719 has dup fanin 19318.
ABC: Node 28719 has dup fanin 19318.
ABC: Node 28720 has dup fanin 19318.
ABC: Node 28720 has dup fanin 19318.
ABC: Node 28721 has dup fanin 19318.
ABC: Node 28721 has dup fanin 19318.
ABC: Node 28722 has dup fanin 19318.
ABC: Node 28722 has dup fanin 19318.
ABC: Node 28723 has dup fanin 19318.
ABC: Node 28723 has dup fanin 19318.
ABC: Node 28724 has dup fanin 19318.
ABC: Node 28724 has dup fanin 19318.
ABC: Node 28725 has dup fanin 19318.
ABC: Node 28725 has dup fanin 19318.
ABC: Node 28726 has dup fanin 19318.
ABC: Node 28726 has dup fanin 19318.
ABC: Node 28727 has dup fanin 19318.
ABC: Node 28727 has dup fanin 19318.
ABC: Node 28728 has dup fanin 19318.
ABC: Node 28728 has dup fanin 19318.
ABC: Node 28729 has dup fanin 19318.
ABC: Node 28729 has dup fanin 19318.
ABC: Node 28730 has dup fanin 19318.
ABC: Node 28730 has dup fanin 19318.
ABC: Node 28731 has dup fanin 19318.
ABC: Node 28731 has dup fanin 19318.
ABC: Node 28732 has dup fanin 19318.
ABC: Node 28732 has dup fanin 19318.
ABC: Node 28733 has dup fanin 19318.
ABC: Node 28733 has dup fanin 19318.
ABC: Node 28734 has dup fanin 19318.
ABC: Node 28734 has dup fanin 19318.
ABC: Node 28735 has dup fanin 19318.
ABC: Node 28735 has dup fanin 19318.
ABC: Node 28845 has dup fanin 28736.
ABC: Node 28845 has dup fanin 28736.
ABC: Node 28881 has dup fanin 28736.
ABC: Node 28881 has dup fanin 28736.
ABC: Node 28917 has dup fanin 28736.
ABC: Node 28917 has dup fanin 28736.
ABC: Node 28953 has dup fanin 28736.
ABC: Node 28953 has dup fanin 28736.
ABC: Node 28989 has dup fanin 28736.
ABC: Node 28989 has dup fanin 28736.
ABC: Node 29025 has dup fanin 28736.
ABC: Node 29025 has dup fanin 28736.
ABC: Node 29061 has dup fanin 28736.
ABC: Node 29061 has dup fanin 28736.
ABC: Node 29097 has dup fanin 28736.
ABC: Node 29097 has dup fanin 28736.
ABC: Node 29133 has dup fanin 28736.
ABC: Node 29133 has dup fanin 28736.
ABC: Node 29167 has dup fanin 29166.
ABC: Node 29167 has dup fanin 29166.
ABC: Node 29168 has dup fanin 29166.
ABC: Node 29168 has dup fanin 29166.
ABC: Node 29169 has dup fanin 29166.
ABC: Node 29169 has dup fanin 29166.
ABC: Node 29170 has dup fanin 29166.
ABC: Node 29170 has dup fanin 29166.
ABC: Node 29171 has dup fanin 29166.
ABC: Node 29171 has dup fanin 29166.
ABC: Node 29172 has dup fanin 29166.
ABC: Node 29172 has dup fanin 29166.
ABC: Node 29173 has dup fanin 29166.
ABC: Node 29173 has dup fanin 29166.
ABC: Node 29174 has dup fanin 29166.
ABC: Node 29174 has dup fanin 29166.
ABC: Node 29175 has dup fanin 29166.
ABC: Node 29175 has dup fanin 29166.
ABC: Node 29176 has dup fanin 29166.
ABC: Node 29176 has dup fanin 29166.
ABC: Node 29177 has dup fanin 29166.
ABC: Node 29177 has dup fanin 29166.
ABC: Node 29178 has dup fanin 29166.
ABC: Node 29178 has dup fanin 29166.
ABC: Node 29179 has dup fanin 29166.
ABC: Node 29179 has dup fanin 29166.
ABC: Node 29180 has dup fanin 29166.
ABC: Node 29180 has dup fanin 29166.
ABC: Node 29181 has dup fanin 29166.
ABC: Node 29181 has dup fanin 29166.
ABC: Node 29182 has dup fanin 29166.
ABC: Node 29182 has dup fanin 29166.
ABC: Node 29183 has dup fanin 29166.
ABC: Node 29183 has dup fanin 29166.
ABC: Node 29184 has dup fanin 29166.
ABC: Node 29184 has dup fanin 29166.
ABC: Node 29185 has dup fanin 29166.
ABC: Node 29185 has dup fanin 29166.
ABC: Node 29186 has dup fanin 29166.
ABC: Node 29186 has dup fanin 29166.
ABC: Node 29187 has dup fanin 29166.
ABC: Node 29187 has dup fanin 29166.
ABC: Node 29188 has dup fanin 29166.
ABC: Node 29188 has dup fanin 29166.
ABC: Node 29189 has dup fanin 29166.
ABC: Node 29189 has dup fanin 29166.
ABC: Node 29190 has dup fanin 29166.
ABC: Node 29190 has dup fanin 29166.
ABC: Node 29191 has dup fanin 29166.
ABC: Node 29191 has dup fanin 29166.
ABC: Node 29192 has dup fanin 29166.
ABC: Node 29192 has dup fanin 29166.
ABC: Node 29193 has dup fanin 29166.
ABC: Node 29193 has dup fanin 29166.
ABC: Node 29194 has dup fanin 29166.
ABC: Node 29194 has dup fanin 29166.
ABC: Node 29195 has dup fanin 29166.
ABC: Node 29195 has dup fanin 29166.
ABC: Node 29196 has dup fanin 29166.
ABC: Node 29196 has dup fanin 29166.
ABC: Node 29197 has dup fanin 29166.
ABC: Node 29197 has dup fanin 29166.
ABC: Node 29198 has dup fanin 29166.
ABC: Node 29198 has dup fanin 29166.
ABC: Node 29276 has dup fanin 29270.
ABC: Node 29276 has dup fanin 29270.
ABC: Node 29277 has dup fanin 14002.
ABC: Node 29277 has dup fanin 14002.
ABC: Node 29283 has dup fanin 29269.
ABC: Node 29283 has dup fanin 29269.
ABC: Node 29298 has dup fanin 29269.
ABC: Node 29298 has dup fanin 29269.
ABC: Node 29304 has dup fanin 29269.
ABC: Node 29304 has dup fanin 29269.
ABC: Node 29309 has dup fanin 29270.
ABC: Node 29309 has dup fanin 29270.
ABC: Node 29313 has dup fanin 29269.
ABC: Node 29313 has dup fanin 29269.
ABC: Node 29318 has dup fanin 29270.
ABC: Node 29318 has dup fanin 29270.
ABC: Node 29359 has dup fanin 12742.
ABC: Node 29359 has dup fanin 12742.
ABC: Node 29364 has dup fanin 12742.
ABC: Node 29364 has dup fanin 12742.
ABC: Node 29367 has dup fanin 12742.
ABC: Node 29367 has dup fanin 12742.
ABC: Node 29370 has dup fanin 12742.
ABC: Node 29370 has dup fanin 12742.
ABC: Node 29373 has dup fanin 12742.
ABC: Node 29373 has dup fanin 12742.
ABC: Node 29376 has dup fanin 12742.
ABC: Node 29376 has dup fanin 12742.
ABC: Node 29379 has dup fanin 12742.
ABC: Node 29379 has dup fanin 12742.
ABC: Node 29382 has dup fanin 12742.
ABC: Node 29382 has dup fanin 12742.
ABC: Node 29385 has dup fanin 12742.
ABC: Node 29385 has dup fanin 12742.
ABC: Node 29592 has dup fanin 1149.
ABC: Node 29592 has dup fanin 1149.
ABC: Node 29629 has dup fanin 8641.
ABC: Node 29629 has dup fanin 8641.
ABC: Node 29639 has dup fanin 29585.
ABC: Node 29639 has dup fanin 29585.
ABC: Node 29646 has dup fanin 8628.
ABC: Node 29646 has dup fanin 29645.
ABC: Node 29646 has dup fanin 8628.
ABC: Node 29646 has dup fanin 29645.
ABC: Node 29676 has dup fanin 8625.
ABC: Node 29676 has dup fanin 29675.
ABC: Node 29676 has dup fanin 8625.
ABC: Node 29676 has dup fanin 29675.
ABC: Node 29683 has dup fanin 8624.
ABC: Node 29683 has dup fanin 29682.
ABC: Node 29683 has dup fanin 8624.
ABC: Node 29683 has dup fanin 29682.
ABC: Node 29701 has dup fanin 8622.
ABC: Node 29701 has dup fanin 29700.
ABC: Node 29701 has dup fanin 8622.
ABC: Node 29701 has dup fanin 29700.
ABC: Node 29709 has dup fanin 8621.
ABC: Node 29709 has dup fanin 29708.
ABC: Node 29709 has dup fanin 8621.
ABC: Node 29709 has dup fanin 29708.
ABC: Node 29717 has dup fanin 8620.
ABC: Node 29717 has dup fanin 29716.
ABC: Node 29717 has dup fanin 8620.
ABC: Node 29717 has dup fanin 29716.
ABC: Node 29725 has dup fanin 8619.
ABC: Node 29725 has dup fanin 29724.
ABC: Node 29725 has dup fanin 8619.
ABC: Node 29725 has dup fanin 29724.
ABC: Node 29733 has dup fanin 8618.
ABC: Node 29733 has dup fanin 29732.
ABC: Node 29733 has dup fanin 8618.
ABC: Node 29733 has dup fanin 29732.
ABC: Node 29741 has dup fanin 8617.
ABC: Node 29741 has dup fanin 29740.
ABC: Node 29741 has dup fanin 8617.
ABC: Node 29741 has dup fanin 29740.
ABC: Node 29749 has dup fanin 8616.
ABC: Node 29749 has dup fanin 29748.
ABC: Node 29749 has dup fanin 8616.
ABC: Node 29749 has dup fanin 29748.
ABC: Node 29767 has dup fanin 8614.
ABC: Node 29767 has dup fanin 29766.
ABC: Node 29767 has dup fanin 8614.
ABC: Node 29767 has dup fanin 29766.
ABC: Node 29775 has dup fanin 8613.
ABC: Node 29775 has dup fanin 29774.
ABC: Node 29775 has dup fanin 8613.
ABC: Node 29775 has dup fanin 29774.
ABC: Node 29783 has dup fanin 8612.
ABC: Node 29783 has dup fanin 29782.
ABC: Node 29783 has dup fanin 8612.
ABC: Node 29783 has dup fanin 29782.
ABC: Node 29791 has dup fanin 8611.
ABC: Node 29791 has dup fanin 29790.
ABC: Node 29791 has dup fanin 8611.
ABC: Node 29791 has dup fanin 29790.
ABC: Node 29799 has dup fanin 8610.
ABC: Node 29799 has dup fanin 29798.
ABC: Node 29799 has dup fanin 8610.
ABC: Node 29799 has dup fanin 29798.
ABC: Node 29807 has dup fanin 8609.
ABC: Node 29807 has dup fanin 29806.
ABC: Node 29807 has dup fanin 8609.
ABC: Node 29807 has dup fanin 29806.
ABC: Node 29815 has dup fanin 8608.
ABC: Node 29815 has dup fanin 29814.
ABC: Node 29815 has dup fanin 8608.
ABC: Node 29815 has dup fanin 29814.
ABC: Node 29823 has dup fanin 8607.
ABC: Node 29823 has dup fanin 29822.
ABC: Node 29823 has dup fanin 8607.
ABC: Node 29823 has dup fanin 29822.
ABC: Node 29831 has dup fanin 8606.
ABC: Node 29831 has dup fanin 29830.
ABC: Node 29831 has dup fanin 8606.
ABC: Node 29831 has dup fanin 29830.
ABC: Node 29839 has dup fanin 8605.
ABC: Node 29839 has dup fanin 29838.
ABC: Node 29839 has dup fanin 8605.
ABC: Node 29839 has dup fanin 29838.
ABC: Node 29847 has dup fanin 8604.
ABC: Node 29847 has dup fanin 29846.
ABC: Node 29847 has dup fanin 8604.
ABC: Node 29847 has dup fanin 29846.
ABC: Node 29855 has dup fanin 8603.
ABC: Node 29855 has dup fanin 29854.
ABC: Node 29855 has dup fanin 8603.
ABC: Node 29855 has dup fanin 29854.
ABC: Node 29863 has dup fanin 8602.
ABC: Node 29863 has dup fanin 29862.
ABC: Node 29863 has dup fanin 8602.
ABC: Node 29863 has dup fanin 29862.
ABC: Node 29880 has dup fanin 8600.
ABC: Node 29880 has dup fanin 29879.
ABC: Node 29880 has dup fanin 8600.
ABC: Node 29880 has dup fanin 29879.
ABC: Node 29992 has dup fanin 12693.
ABC: Node 29992 has dup fanin 12693.
ABC: Node 29995 has dup fanin 12693.
ABC: Node 29995 has dup fanin 12693.
ABC: Node 30004 has dup fanin 12693.
ABC: Node 30004 has dup fanin 12693.
ABC: Node 30017 has dup fanin 12693.
ABC: Node 30017 has dup fanin 12693.
ABC: Node 30026 has dup fanin 12693.
ABC: Node 30026 has dup fanin 12693.
ABC: Node 30040 has dup fanin 12693.
ABC: Node 30040 has dup fanin 12693.
ABC: Node 30059 has dup fanin 12693.
ABC: Node 30059 has dup fanin 12693.
ABC: Node 30066 has dup fanin 12693.
ABC: Node 30066 has dup fanin 12693.
ABC: Node 30076 has dup fanin 12693.
ABC: Node 30076 has dup fanin 12693.
ABC: Node 30125 has dup fanin 8899.
ABC: Node 30125 has dup fanin 8899.
ABC: Node 30126 has dup fanin 1067.
ABC: Node 30126 has dup fanin 1067.
ABC: Node 30170 has dup fanin 509.
ABC: Node 30170 has dup fanin 509.
ABC: Node 30206 has dup fanin 9427.
ABC: Node 30206 has dup fanin 9427.
ABC: Node 30249 has dup fanin 9428.
ABC: Node 30249 has dup fanin 9428.
ABC: Node 30295 has dup fanin 9427.
ABC: Node 30295 has dup fanin 9427.
ABC: Node 30342 has dup fanin 9427.
ABC: Node 30342 has dup fanin 9427.
ABC: Node 30376 has dup fanin 9428.
ABC: Node 30376 has dup fanin 9428.
ABC: Node 30385 has dup fanin 8511.
ABC: Node 30385 has dup fanin 8511.
ABC: Node 30398 has dup fanin 9427.
ABC: Node 30398 has dup fanin 9427.
ABC: Node 30433 has dup fanin 8511.
ABC: Node 30433 has dup fanin 8511.
ABC: Node 30477 has dup fanin 8511.
ABC: Node 30477 has dup fanin 8511.
ABC: Node 30521 has dup fanin 8511.
ABC: Node 30521 has dup fanin 8511.
ABC: Node 30544 has dup fanin 8511.
ABC: Node 30544 has dup fanin 8511.
ABC: Node 30565 has dup fanin 8511.
ABC: Node 30565 has dup fanin 8511.
ABC: Node 30608 has dup fanin 8511.
ABC: Node 30608 has dup fanin 8511.
ABC: Node 30801 has dup fanin 8511.
ABC: Node 30801 has dup fanin 8511.
ABC: Node 30820 has dup fanin 8511.
ABC: Node 30820 has dup fanin 8511.
ABC: Node 30839 has dup fanin 8511.
ABC: Node 30839 has dup fanin 8511.
ABC: Node 30858 has dup fanin 8511.
ABC: Node 30858 has dup fanin 8511.
ABC: Node 30878 has dup fanin 8511.
ABC: Node 30878 has dup fanin 8511.
ABC: + upsize -D 50000 
ABC: Current delay (12524.61 ps) does not exceed the target delay (50000.00 ps). Upsizing is not performed.
ABC: + dnsize -D 50000 
ABC: + stime -p 
ABC: WireLoad = "none"  Gates =  30744 ( 39.6 %)   Cap =  9.4 ff (  0.0 %)   Area =   305431.69 (100.0 %)   Delay = 12524.61 ps  (  0.2 %)               
ABC: Path  0 --    3968 : 0    3 pi                      A =   0.00  Df =  12.0   -8.1 ps  S =  25.0 ps  Cin =  0.0 ff  Cout =   9.6 ff  Cmax =   0.0 ff  G =    0  
ABC: Path  1 --   24771 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df = 149.3   -1.3 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path  2 --   24772 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df = 303.9   -9.6 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path  3 --   24773 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df = 459.7  -20.5 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path  4 --   24774 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df = 615.4  -31.3 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path  5 --   24775 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df = 771.2  -42.1 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path  6 --   24776 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df = 927.0  -52.9 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path  7 --   24777 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =1082.7  -63.7 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path  8 --   24778 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =1238.5  -74.6 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path  9 --   24779 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =1394.3  -85.4 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 10 --   24780 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =1550.0  -96.2 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 11 --   24781 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =1705.8 -107.0 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 12 --   24782 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =1861.6 -117.8 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 13 --   24783 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =2017.3 -128.7 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 14 --   24784 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =2173.1 -139.5 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 15 --   24785 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =2328.9 -150.3 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 16 --   24786 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =2484.6 -161.1 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 17 --   24787 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =2640.4 -171.9 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 18 --   24788 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =2796.1 -182.8 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 19 --   24789 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =2951.9 -193.6 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 20 --   24790 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =3107.7 -204.4 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 21 --   24791 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =3263.4 -215.2 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 22 --   24792 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =3419.2 -226.0 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 23 --   24793 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =3575.0 -236.9 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 24 --   24794 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =3730.7 -247.7 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 25 --   24795 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =3886.5 -258.5 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 26 --   24796 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =4042.3 -269.3 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 27 --   24797 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =4198.0 -280.1 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 28 --   24798 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =4353.8 -291.0 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 29 --   24799 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =4509.6 -301.8 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 30 --   24800 : 2    3 sky130_fd_sc_hd__and2_4 A =   8.76  Df =4665.3 -312.6 ps  S =  50.2 ps  Cin =  2.4 ff  Cout =   9.7 ff  Cmax = 539.3 ff  G =  389  
ABC: Path 31 --   24801 : 2    2 sky130_fd_sc_hd__and2_4 A =   8.76  Df =4817.0 -325.7 ps  S =  43.6 ps  Cin =  2.4 ff  Cout =   7.2 ff  Cmax = 539.3 ff  G =  287  
ABC: Path 32 --   24802 : 1    2 sky130_fd_sc_hd__inv_2  A =   3.75  Df =4859.6 -338.5 ps  S =  31.1 ps  Cin =  4.5 ff  Cout =   5.0 ff  Cmax = 331.4 ff  G =  106  
ABC: Path 33 --   24803 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =4979.1 -223.0 ps  S =  60.4 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 34 --   24804 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =5108.7 -103.6 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 35 --   24805 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =5253.9  -15.6 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 36 --   24806 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =5502.7 -134.9 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 37 --   24807 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =5751.6 -254.1 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 38 --   24808 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =6000.4 -373.4 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 39 --   24809 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =6249.2 -492.6 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 40 --   24810 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =6498.0 -611.9 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 41 --   24811 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =6746.8 -731.1 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 42 --   24812 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =6995.6 -850.4 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 43 --   24813 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =7244.4 -969.6 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 44 --   24814 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =7493.3-1088.9 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 45 --   24815 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =7742.1-1208.1 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 46 --   24816 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =7990.9-1327.3 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 47 --   24817 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =8239.7-1446.6 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 48 --   24818 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =8488.5-1565.8 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 49 --   24819 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =8737.3-1685.1 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 50 --   24820 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =8986.1-1804.3 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 51 --   24821 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =9235.0-1923.6 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 52 --   24822 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =9483.8-2042.8 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 53 --   24823 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =9732.6-2162.1 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 54 --   24824 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =9981.4-2281.3 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 55 --   24825 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =10230.2-2400.5 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 56 --   24826 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =10479.0-2519.8 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 57 --   24827 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =10727.8-2639.0 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 58 --   24828 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =10976.7-2758.3 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 59 --   24829 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =11225.5-2877.5 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 60 --   24830 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =11474.3-2996.8 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 61 --   24831 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =11723.1-3116.0 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 62 --   24832 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =11971.9-3235.3 ps  S =  60.0 ps  Cin =  2.4 ff  Cout =  14.3 ff  Cmax = 514.5 ff  G =  568  
ABC: Path 63 --   24833 : 2    3 sky130_fd_sc_hd__or2_4  A =   8.76  Df =12226.2-3354.1 ps  S =  65.7 ps  Cin =  2.4 ff  Cout =  16.9 ff  Cmax = 514.5 ff  G =  672  
ABC: Path 64 --   24835 : 3    1 sky130_fd_sc_hd__o21a_4 A =  15.01  Df =12524.6  -78.3 ps  S =  69.6 ps  Cin =  4.6 ff  Cout =  17.6 ff  Cmax = 510.0 ff  G =  383  
ABC: Start-point = pi3967 (\soc.cpu.picorv32_core.count_cycle [1]).  End-point = po1836 ($auto$rtlil.cc:2290:MuxGate$90069).
ABC: + print_stats -m 
ABC: netlist                       : i/o = 4227/ 4046  lat =    0  nd = 30744  edge =  68827  area =305393.20  delay =75.00  lev = 75
ABC: + write_blif /tmp/yosys-abc-BEDAcD/output.blif 

20.1.2. Re-integrating ABC results.
ABC RESULTS:   sky130_fd_sc_hd__a2111o_4 cells:       22
ABC RESULTS:   sky130_fd_sc_hd__a211o_4 cells:     1752
ABC RESULTS:   sky130_fd_sc_hd__a21bo_4 cells:       39
ABC RESULTS:   sky130_fd_sc_hd__a21boi_4 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__a21o_4 cells:      142
ABC RESULTS:   sky130_fd_sc_hd__a21oi_4 cells:      127
ABC RESULTS:   sky130_fd_sc_hd__a22oi_4 cells:      103
ABC RESULTS:   sky130_fd_sc_hd__a2bb2o_4 cells:     2128
ABC RESULTS:   sky130_fd_sc_hd__a32o_4 cells:      678
ABC RESULTS:   sky130_fd_sc_hd__a41o_4 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__and2_4 cells:     1445
ABC RESULTS:   sky130_fd_sc_hd__and3_4 cells:     1929
ABC RESULTS:   sky130_fd_sc_hd__and4_4 cells:      144
ABC RESULTS:   sky130_fd_sc_hd__buf_2 cells:     8087
ABC RESULTS:   sky130_fd_sc_hd__inv_2 cells:     4077
ABC RESULTS:   sky130_fd_sc_hd__nand2_4 cells:      292
ABC RESULTS:   sky130_fd_sc_hd__nor2_4 cells:      997
ABC RESULTS:   sky130_fd_sc_hd__o21a_4 cells:      895
ABC RESULTS:   sky130_fd_sc_hd__o21ai_4 cells:      134
ABC RESULTS:   sky130_fd_sc_hd__o22a_4 cells:     1815
ABC RESULTS:   sky130_fd_sc_hd__o32a_4 cells:       58
ABC RESULTS:   sky130_fd_sc_hd__o41a_4 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__or2_4 cells:     4428
ABC RESULTS:   sky130_fd_sc_hd__or3_4 cells:      832
ABC RESULTS:   sky130_fd_sc_hd__or4_4 cells:      611
ABC RESULTS:        internal signals:    20842
ABC RESULTS:           input signals:     4227
ABC RESULTS:          output signals:     4046
Removing temp directory.

21. Executing SETUNDEF pass (replace undef values with defined constants).

22. Executing HILOMAP pass (mapping to constant drivers).

23. Executing SPLITNETS pass (splitting up multi-bit signals).

24. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \mgmt_core..
Removed 269 unused cells and 30419 unused wires.
<suppressed ~1317 debug messages>

25. Executing INSBUF pass (insert buffer cells for connected wires).
Added mgmt_core.$auto$insbuf.cc:79:execute$127869: \flash_clk_oeb -> \flash_csb_oeb
Added mgmt_core.$auto$insbuf.cc:79:execute$127870: \mgmt_addr [0] -> \mgmt_addr_ro [0]
Added mgmt_core.$auto$insbuf.cc:79:execute$127871: \mgmt_addr [1] -> \mgmt_addr_ro [1]
Added mgmt_core.$auto$insbuf.cc:79:execute$127872: \mgmt_addr [2] -> \mgmt_addr_ro [2]
Added mgmt_core.$auto$insbuf.cc:79:execute$127873: \mgmt_addr [3] -> \mgmt_addr_ro [3]
Added mgmt_core.$auto$insbuf.cc:79:execute$127874: \mgmt_addr [4] -> \mgmt_addr_ro [4]
Added mgmt_core.$auto$insbuf.cc:79:execute$127875: \mgmt_addr [5] -> \mgmt_addr_ro [5]
Added mgmt_core.$auto$insbuf.cc:79:execute$127876: \mgmt_addr [6] -> \mgmt_addr_ro [6]
Added mgmt_core.$auto$insbuf.cc:79:execute$127877: \mgmt_addr [7] -> \mgmt_addr_ro [7]
Added mgmt_core.$auto$insbuf.cc:79:execute$127878: \mgmt_wen [1] -> \mgmt_wen [0]
Added mgmt_core.$auto$insbuf.cc:79:execute$127879: \mgmt_wen_mask [4] -> \mgmt_wen_mask [0]
Added mgmt_core.$auto$insbuf.cc:79:execute$127880: \mgmt_wen_mask [5] -> \mgmt_wen_mask [1]
Added mgmt_core.$auto$insbuf.cc:79:execute$127881: \mgmt_wen_mask [6] -> \mgmt_wen_mask [2]
Added mgmt_core.$auto$insbuf.cc:79:execute$127882: \mgmt_wen_mask [7] -> \mgmt_wen_mask [3]
Added mgmt_core.$auto$insbuf.cc:79:execute$127883: \mgmt_addr [0] -> \mprj_adr_o [2]
Added mgmt_core.$auto$insbuf.cc:79:execute$127884: \mgmt_addr [1] -> \mprj_adr_o [3]
Added mgmt_core.$auto$insbuf.cc:79:execute$127885: \mgmt_addr [2] -> \mprj_adr_o [4]
Added mgmt_core.$auto$insbuf.cc:79:execute$127886: \mgmt_addr [3] -> \mprj_adr_o [5]
Added mgmt_core.$auto$insbuf.cc:79:execute$127887: \mgmt_addr [4] -> \mprj_adr_o [6]
Added mgmt_core.$auto$insbuf.cc:79:execute$127888: \mgmt_addr [5] -> \mprj_adr_o [7]
Added mgmt_core.$auto$insbuf.cc:79:execute$127889: \mgmt_addr [6] -> \mprj_adr_o [8]
Added mgmt_core.$auto$insbuf.cc:79:execute$127890: \mgmt_addr [7] -> \mprj_adr_o [9]
Added mgmt_core.$auto$insbuf.cc:79:execute$127891: \mgmt_wdata [0] -> \mprj_dat_o [0]
Added mgmt_core.$auto$insbuf.cc:79:execute$127892: \mgmt_wdata [1] -> \mprj_dat_o [1]
Added mgmt_core.$auto$insbuf.cc:79:execute$127893: \mgmt_wdata [2] -> \mprj_dat_o [2]
Added mgmt_core.$auto$insbuf.cc:79:execute$127894: \mgmt_wdata [3] -> \mprj_dat_o [3]
Added mgmt_core.$auto$insbuf.cc:79:execute$127895: \mgmt_wdata [4] -> \mprj_dat_o [4]
Added mgmt_core.$auto$insbuf.cc:79:execute$127896: \mgmt_wdata [5] -> \mprj_dat_o [5]
Added mgmt_core.$auto$insbuf.cc:79:execute$127897: \mgmt_wdata [6] -> \mprj_dat_o [6]
Added mgmt_core.$auto$insbuf.cc:79:execute$127898: \mgmt_wdata [7] -> \mprj_dat_o [7]
Added mgmt_core.$auto$insbuf.cc:79:execute$127899: \mgmt_wdata [8] -> \mprj_dat_o [8]
Added mgmt_core.$auto$insbuf.cc:79:execute$127900: \mgmt_wdata [9] -> \mprj_dat_o [9]
Added mgmt_core.$auto$insbuf.cc:79:execute$127901: \mgmt_wdata [10] -> \mprj_dat_o [10]
Added mgmt_core.$auto$insbuf.cc:79:execute$127902: \mgmt_wdata [11] -> \mprj_dat_o [11]
Added mgmt_core.$auto$insbuf.cc:79:execute$127903: \mgmt_wdata [12] -> \mprj_dat_o [12]
Added mgmt_core.$auto$insbuf.cc:79:execute$127904: \mgmt_wdata [13] -> \mprj_dat_o [13]
Added mgmt_core.$auto$insbuf.cc:79:execute$127905: \mgmt_wdata [14] -> \mprj_dat_o [14]
Added mgmt_core.$auto$insbuf.cc:79:execute$127906: \mgmt_wdata [15] -> \mprj_dat_o [15]
Added mgmt_core.$auto$insbuf.cc:79:execute$127907: \mgmt_wdata [16] -> \mprj_dat_o [16]
Added mgmt_core.$auto$insbuf.cc:79:execute$127908: \mgmt_wdata [17] -> \mprj_dat_o [17]
Added mgmt_core.$auto$insbuf.cc:79:execute$127909: \mgmt_wdata [18] -> \mprj_dat_o [18]
Added mgmt_core.$auto$insbuf.cc:79:execute$127910: \mgmt_wdata [19] -> \mprj_dat_o [19]
Added mgmt_core.$auto$insbuf.cc:79:execute$127911: \mgmt_wdata [20] -> \mprj_dat_o [20]
Added mgmt_core.$auto$insbuf.cc:79:execute$127912: \mgmt_wdata [21] -> \mprj_dat_o [21]
Added mgmt_core.$auto$insbuf.cc:79:execute$127913: \mgmt_wdata [22] -> \mprj_dat_o [22]
Added mgmt_core.$auto$insbuf.cc:79:execute$127914: \mgmt_wdata [23] -> \mprj_dat_o [23]
Added mgmt_core.$auto$insbuf.cc:79:execute$127915: \mgmt_wdata [24] -> \mprj_dat_o [24]
Added mgmt_core.$auto$insbuf.cc:79:execute$127916: \mgmt_wdata [25] -> \mprj_dat_o [25]
Added mgmt_core.$auto$insbuf.cc:79:execute$127917: \mgmt_wdata [26] -> \mprj_dat_o [26]
Added mgmt_core.$auto$insbuf.cc:79:execute$127918: \mgmt_wdata [27] -> \mprj_dat_o [27]
Added mgmt_core.$auto$insbuf.cc:79:execute$127919: \mgmt_wdata [28] -> \mprj_dat_o [28]
Added mgmt_core.$auto$insbuf.cc:79:execute$127920: \mgmt_wdata [29] -> \mprj_dat_o [29]
Added mgmt_core.$auto$insbuf.cc:79:execute$127921: \mgmt_wdata [30] -> \mprj_dat_o [30]
Added mgmt_core.$auto$insbuf.cc:79:execute$127922: \mgmt_wdata [31] -> \mprj_dat_o [31]

26. Executing CHECK pass (checking for obvious problems).
checking module mgmt_core..
Warning: Wire mgmt_core.\user_clk is used but has no driver.
Warning: Wire mgmt_core.\sdo_outenb is used but has no driver.
Warning: Wire mgmt_core.\sdo_out is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [3] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [2] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [1] is used but has no driver.
Warning: Wire mgmt_core.\pwr_ctrl_out [0] is used but has no driver.
Warning: Wire mgmt_core.\mprj_we_o is used but has no driver.
Warning: Wire mgmt_core.\mprj_stb_o is used but has no driver.
Warning: Wire mgmt_core.\mprj_sel_o [3] is used but has no driver.
Warning: Wire mgmt_core.\mprj_sel_o [2] is used but has no driver.
Warning: Wire mgmt_core.\mprj_sel_o [1] is used but has no driver.
Warning: Wire mgmt_core.\mprj_sel_o [0] is used but has no driver.
Warning: Wire mgmt_core.\mprj_io_loader_resetn is used but has no driver.
Warning: Wire mgmt_core.\mprj_io_loader_data is used but has no driver.
Warning: Wire mgmt_core.\mprj_io_loader_clock is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [31] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [30] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [29] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [28] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [27] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [26] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [25] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [24] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [23] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [22] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [21] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [20] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [19] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [18] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [17] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [16] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [15] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [14] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [13] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [12] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [11] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [10] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [9] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [8] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [7] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [6] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [5] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [4] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [3] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [2] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [1] is used but has no driver.
Warning: Wire mgmt_core.\mprj_dat_o [0] is used but has no driver.
Warning: Wire mgmt_core.\mprj_cyc_o is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [31] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [30] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [29] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [28] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [27] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [26] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [25] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [24] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [23] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [22] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [21] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [20] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [19] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [18] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [17] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [16] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [15] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [14] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [13] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [12] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [11] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [10] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [9] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [8] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [7] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [6] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [5] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [4] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [3] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [2] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [1] is used but has no driver.
Warning: Wire mgmt_core.\mprj_adr_o [0] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [7] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [6] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [5] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [4] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [3] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [2] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [1] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen_mask [0] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen [1] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wen [0] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [37] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [36] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [35] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [34] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [33] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [32] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [31] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [30] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [29] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [28] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [27] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [26] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [25] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [24] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [23] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [22] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [21] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [20] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [19] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [18] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [17] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [16] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [15] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [14] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [13] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [12] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [11] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [10] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [9] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [8] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [7] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [6] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [5] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [4] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [3] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [2] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [1] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_out_data [0] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_ena_ro is used but has no driver.
Warning: Wire mgmt_core.\mgmt_ena [1] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_ena [0] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [7] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [6] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [5] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [4] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [3] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [2] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [1] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr_ro [0] is used but has no driver.
Warning: Wire mgmt_core.\la_output [127] is used but has no driver.
Warning: Wire mgmt_core.\la_output [126] is used but has no driver.
Warning: Wire mgmt_core.\la_output [125] is used but has no driver.
Warning: Wire mgmt_core.\la_output [124] is used but has no driver.
Warning: Wire mgmt_core.\la_output [123] is used but has no driver.
Warning: Wire mgmt_core.\la_output [122] is used but has no driver.
Warning: Wire mgmt_core.\la_output [121] is used but has no driver.
Warning: Wire mgmt_core.\la_output [120] is used but has no driver.
Warning: Wire mgmt_core.\la_output [119] is used but has no driver.
Warning: Wire mgmt_core.\la_output [118] is used but has no driver.
Warning: Wire mgmt_core.\la_output [117] is used but has no driver.
Warning: Wire mgmt_core.\la_output [116] is used but has no driver.
Warning: Wire mgmt_core.\la_output [115] is used but has no driver.
Warning: Wire mgmt_core.\la_output [114] is used but has no driver.
Warning: Wire mgmt_core.\la_output [113] is used but has no driver.
Warning: Wire mgmt_core.\la_output [112] is used but has no driver.
Warning: Wire mgmt_core.\la_output [111] is used but has no driver.
Warning: Wire mgmt_core.\la_output [110] is used but has no driver.
Warning: Wire mgmt_core.\la_output [109] is used but has no driver.
Warning: Wire mgmt_core.\la_output [108] is used but has no driver.
Warning: Wire mgmt_core.\la_output [107] is used but has no driver.
Warning: Wire mgmt_core.\la_output [106] is used but has no driver.
Warning: Wire mgmt_core.\la_output [105] is used but has no driver.
Warning: Wire mgmt_core.\la_output [104] is used but has no driver.
Warning: Wire mgmt_core.\la_output [103] is used but has no driver.
Warning: Wire mgmt_core.\la_output [102] is used but has no driver.
Warning: Wire mgmt_core.\la_output [101] is used but has no driver.
Warning: Wire mgmt_core.\la_output [100] is used but has no driver.
Warning: Wire mgmt_core.\la_output [99] is used but has no driver.
Warning: Wire mgmt_core.\la_output [98] is used but has no driver.
Warning: Wire mgmt_core.\la_output [97] is used but has no driver.
Warning: Wire mgmt_core.\la_output [96] is used but has no driver.
Warning: Wire mgmt_core.\la_output [95] is used but has no driver.
Warning: Wire mgmt_core.\la_output [94] is used but has no driver.
Warning: Wire mgmt_core.\la_output [93] is used but has no driver.
Warning: Wire mgmt_core.\la_output [92] is used but has no driver.
Warning: Wire mgmt_core.\la_output [91] is used but has no driver.
Warning: Wire mgmt_core.\la_output [90] is used but has no driver.
Warning: Wire mgmt_core.\la_output [89] is used but has no driver.
Warning: Wire mgmt_core.\la_output [88] is used but has no driver.
Warning: Wire mgmt_core.\la_output [87] is used but has no driver.
Warning: Wire mgmt_core.\la_output [86] is used but has no driver.
Warning: Wire mgmt_core.\la_output [85] is used but has no driver.
Warning: Wire mgmt_core.\la_output [84] is used but has no driver.
Warning: Wire mgmt_core.\la_output [83] is used but has no driver.
Warning: Wire mgmt_core.\la_output [82] is used but has no driver.
Warning: Wire mgmt_core.\la_output [81] is used but has no driver.
Warning: Wire mgmt_core.\la_output [80] is used but has no driver.
Warning: Wire mgmt_core.\la_output [79] is used but has no driver.
Warning: Wire mgmt_core.\la_output [78] is used but has no driver.
Warning: Wire mgmt_core.\la_output [77] is used but has no driver.
Warning: Wire mgmt_core.\la_output [76] is used but has no driver.
Warning: Wire mgmt_core.\la_output [75] is used but has no driver.
Warning: Wire mgmt_core.\la_output [74] is used but has no driver.
Warning: Wire mgmt_core.\la_output [73] is used but has no driver.
Warning: Wire mgmt_core.\la_output [72] is used but has no driver.
Warning: Wire mgmt_core.\la_output [71] is used but has no driver.
Warning: Wire mgmt_core.\la_output [70] is used but has no driver.
Warning: Wire mgmt_core.\la_output [69] is used but has no driver.
Warning: Wire mgmt_core.\la_output [68] is used but has no driver.
Warning: Wire mgmt_core.\la_output [67] is used but has no driver.
Warning: Wire mgmt_core.\la_output [66] is used but has no driver.
Warning: Wire mgmt_core.\la_output [65] is used but has no driver.
Warning: Wire mgmt_core.\la_output [64] is used but has no driver.
Warning: Wire mgmt_core.\la_output [63] is used but has no driver.
Warning: Wire mgmt_core.\la_output [62] is used but has no driver.
Warning: Wire mgmt_core.\la_output [61] is used but has no driver.
Warning: Wire mgmt_core.\la_output [60] is used but has no driver.
Warning: Wire mgmt_core.\la_output [59] is used but has no driver.
Warning: Wire mgmt_core.\la_output [58] is used but has no driver.
Warning: Wire mgmt_core.\la_output [57] is used but has no driver.
Warning: Wire mgmt_core.\la_output [56] is used but has no driver.
Warning: Wire mgmt_core.\la_output [55] is used but has no driver.
Warning: Wire mgmt_core.\la_output [54] is used but has no driver.
Warning: Wire mgmt_core.\la_output [53] is used but has no driver.
Warning: Wire mgmt_core.\la_output [52] is used but has no driver.
Warning: Wire mgmt_core.\la_output [51] is used but has no driver.
Warning: Wire mgmt_core.\la_output [50] is used but has no driver.
Warning: Wire mgmt_core.\la_output [49] is used but has no driver.
Warning: Wire mgmt_core.\la_output [48] is used but has no driver.
Warning: Wire mgmt_core.\la_output [47] is used but has no driver.
Warning: Wire mgmt_core.\la_output [46] is used but has no driver.
Warning: Wire mgmt_core.\la_output [45] is used but has no driver.
Warning: Wire mgmt_core.\la_output [44] is used but has no driver.
Warning: Wire mgmt_core.\la_output [43] is used but has no driver.
Warning: Wire mgmt_core.\la_output [42] is used but has no driver.
Warning: Wire mgmt_core.\la_output [41] is used but has no driver.
Warning: Wire mgmt_core.\la_output [40] is used but has no driver.
Warning: Wire mgmt_core.\la_output [39] is used but has no driver.
Warning: Wire mgmt_core.\la_output [38] is used but has no driver.
Warning: Wire mgmt_core.\la_output [37] is used but has no driver.
Warning: Wire mgmt_core.\la_output [36] is used but has no driver.
Warning: Wire mgmt_core.\la_output [35] is used but has no driver.
Warning: Wire mgmt_core.\la_output [34] is used but has no driver.
Warning: Wire mgmt_core.\la_output [33] is used but has no driver.
Warning: Wire mgmt_core.\la_output [32] is used but has no driver.
Warning: Wire mgmt_core.\la_output [31] is used but has no driver.
Warning: Wire mgmt_core.\la_output [30] is used but has no driver.
Warning: Wire mgmt_core.\la_output [29] is used but has no driver.
Warning: Wire mgmt_core.\la_output [28] is used but has no driver.
Warning: Wire mgmt_core.\la_output [27] is used but has no driver.
Warning: Wire mgmt_core.\la_output [26] is used but has no driver.
Warning: Wire mgmt_core.\la_output [25] is used but has no driver.
Warning: Wire mgmt_core.\la_output [24] is used but has no driver.
Warning: Wire mgmt_core.\la_output [23] is used but has no driver.
Warning: Wire mgmt_core.\la_output [22] is used but has no driver.
Warning: Wire mgmt_core.\la_output [21] is used but has no driver.
Warning: Wire mgmt_core.\la_output [20] is used but has no driver.
Warning: Wire mgmt_core.\la_output [19] is used but has no driver.
Warning: Wire mgmt_core.\la_output [18] is used but has no driver.
Warning: Wire mgmt_core.\la_output [17] is used but has no driver.
Warning: Wire mgmt_core.\la_output [16] is used but has no driver.
Warning: Wire mgmt_core.\la_output [15] is used but has no driver.
Warning: Wire mgmt_core.\la_output [14] is used but has no driver.
Warning: Wire mgmt_core.\la_output [13] is used but has no driver.
Warning: Wire mgmt_core.\la_output [12] is used but has no driver.
Warning: Wire mgmt_core.\la_output [11] is used but has no driver.
Warning: Wire mgmt_core.\la_output [10] is used but has no driver.
Warning: Wire mgmt_core.\la_output [9] is used but has no driver.
Warning: Wire mgmt_core.\la_output [8] is used but has no driver.
Warning: Wire mgmt_core.\la_output [7] is used but has no driver.
Warning: Wire mgmt_core.\la_output [6] is used but has no driver.
Warning: Wire mgmt_core.\la_output [5] is used but has no driver.
Warning: Wire mgmt_core.\la_output [4] is used but has no driver.
Warning: Wire mgmt_core.\la_output [3] is used but has no driver.
Warning: Wire mgmt_core.\la_output [2] is used but has no driver.
Warning: Wire mgmt_core.\la_output [1] is used but has no driver.
Warning: Wire mgmt_core.\la_output [0] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [127] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [126] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [125] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [124] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [123] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [122] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [121] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [120] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [119] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [118] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [117] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [116] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [115] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [114] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [113] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [112] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [111] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [110] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [109] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [108] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [107] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [106] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [105] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [104] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [103] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [102] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [101] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [100] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [99] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [98] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [97] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [96] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [95] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [94] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [93] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [92] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [91] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [90] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [89] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [88] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [87] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [86] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [85] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [84] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [83] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [82] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [81] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [80] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [79] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [78] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [77] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [76] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [75] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [74] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [73] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [72] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [71] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [70] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [69] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [68] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [67] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [66] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [65] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [64] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [63] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [62] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [61] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [60] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [59] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [58] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [57] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [56] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [55] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [54] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [53] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [52] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [51] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [50] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [49] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [48] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [47] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [46] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [45] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [44] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [43] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [42] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [41] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [40] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [39] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [38] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [37] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [36] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [35] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [34] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [33] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [32] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [31] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [30] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [29] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [28] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [27] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [26] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [25] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [24] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [23] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [22] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [21] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [20] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [19] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [18] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [17] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [16] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [15] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [14] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [13] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [12] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [11] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [10] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [9] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [8] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [7] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [6] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [5] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [4] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [3] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [2] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [1] is used but has no driver.
Warning: Wire mgmt_core.\la_oen [0] is used but has no driver.
Warning: Wire mgmt_core.\jtag_outenb is used but has no driver.
Warning: Wire mgmt_core.\jtag_out is used but has no driver.
Warning: Wire mgmt_core.\gpio_outenb_pad is used but has no driver.
Warning: Wire mgmt_core.\gpio_out_pad is used but has no driver.
Warning: Wire mgmt_core.\gpio_mode1_pad is used but has no driver.
Warning: Wire mgmt_core.\gpio_mode0_pad is used but has no driver.
Warning: Wire mgmt_core.\gpio_inenb_pad is used but has no driver.
Warning: Wire mgmt_core.\flash_io1_oeb is used but has no driver.
Warning: Wire mgmt_core.\flash_io1_ieb is used but has no driver.
Warning: Wire mgmt_core.\flash_io1_do is used but has no driver.
Warning: Wire mgmt_core.\flash_io0_oeb is used but has no driver.
Warning: Wire mgmt_core.\flash_io0_ieb is used but has no driver.
Warning: Wire mgmt_core.\flash_io0_do is used but has no driver.
Warning: Wire mgmt_core.\flash_csb_oeb is used but has no driver.
Warning: Wire mgmt_core.\flash_csb_ieb is used but has no driver.
Warning: Wire mgmt_core.\flash_csb is used but has no driver.
Warning: Wire mgmt_core.\flash_clk_oeb is used but has no driver.
Warning: Wire mgmt_core.\flash_clk_ieb is used but has no driver.
Warning: Wire mgmt_core.\flash_clk is used but has no driver.
Warning: Wire mgmt_core.\core_rstn is used but has no driver.
Warning: Wire mgmt_core.\soc.soc_mem.mem.wen[3] is used but has no driver.
Warning: Wire mgmt_core.\soc.soc_mem.mem.wen[2] is used but has no driver.
Warning: Wire mgmt_core.\soc.soc_mem.mem.wen[1] is used but has no driver.
Warning: Wire mgmt_core.\soc.soc_mem.mem.wen[0] is used but has no driver.
Warning: Wire mgmt_core.\soc.soc_mem.mem.ena is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [31] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [30] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [29] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [28] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [27] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [26] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [25] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [24] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [23] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [22] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [21] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [20] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [19] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [18] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [17] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [16] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [15] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [14] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [13] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [12] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [11] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [10] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [9] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [8] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [7] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [6] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [5] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [4] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [3] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [2] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [1] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_wdata [0] is used but has no driver.
Warning: Wire mgmt_core.\core_clk is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [7] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [6] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [5] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [4] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [3] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [2] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [1] is used but has no driver.
Warning: Wire mgmt_core.\mgmt_addr [0] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[25] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[24] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[23] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[22] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[21] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[20] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[19] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[18] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[17] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[16] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[15] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[14] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[13] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[12] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[11] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[10] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[9] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[8] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[7] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[6] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[5] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[4] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[3] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[2] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[1] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_trim[0] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_ena is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_div[4] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_div[3] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_div[2] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_div[1] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_div[0] is used but has no driver.
Warning: Wire mgmt_core.\housekeeping.pll_dco_ena is used but has no driver.
found and reported 495 problems.

27. Printing statistics.

=== mgmt_core ===

   Number of wires:              34324
   Number of wire bits:          35057
   Number of public wires:        3633
   Number of public wire bits:    4366
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              34676
     DFFRAM                          1
     digital_pll                     1
     sky130_fd_sc_hd__a2111o_4      22
     sky130_fd_sc_hd__a211o_4     1752
     sky130_fd_sc_hd__a21bo_4       39
     sky130_fd_sc_hd__a21boi_4       1
     sky130_fd_sc_hd__a21o_4       142
     sky130_fd_sc_hd__a21oi_4      127
     sky130_fd_sc_hd__a22oi_4      103
     sky130_fd_sc_hd__a2bb2o_4    2128
     sky130_fd_sc_hd__a32o_4       678
     sky130_fd_sc_hd__a41o_4         4
     sky130_fd_sc_hd__and2_4      1445
     sky130_fd_sc_hd__and3_4      1929
     sky130_fd_sc_hd__and4_4       144
     sky130_fd_sc_hd__buf_2       8141
     sky130_fd_sc_hd__conb_1        10
     sky130_fd_sc_hd__dfbbn_2       18
     sky130_fd_sc_hd__dfrtp_4      268
     sky130_fd_sc_hd__dfstp_4       70
     sky130_fd_sc_hd__dfxtp_4     3510
     sky130_fd_sc_hd__inv_2       4077
     sky130_fd_sc_hd__nand2_4      292
     sky130_fd_sc_hd__nor2_4       997
     sky130_fd_sc_hd__o21a_4       895
     sky130_fd_sc_hd__o21ai_4      134
     sky130_fd_sc_hd__o22a_4      1815
     sky130_fd_sc_hd__o32a_4        58
     sky130_fd_sc_hd__o41a_4         4
     sky130_fd_sc_hd__or2_4       4428
     sky130_fd_sc_hd__or3_4        832
     sky130_fd_sc_hd__or4_4        611

   Area for cell type \DFFRAM is unknown!
   Area for cell type \digital_pll is unknown!

   Chip area for module '\mgmt_core': 399627.024000

28. Executing Verilog backend.
Dumping module `\mgmt_core'.

Warnings: 555 unique messages, 562 total
End of script. Logfile hash: f172ea2f4b, CPU: user 42.95s system 0.17s, MEM: 219.17 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 43% 2x abc (32 sec), 14% 44x opt_expr (10 sec), ...