Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def
Notice 0: Design: user_proj_example
Notice 0:     Created 614 pins.
Notice 0:     Created 5304 components and 21885 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 1030 nets and 1926 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/routing/user_proj_example.def
Top-level design name: user_proj_example
Found port VPWR of type SIGNAL
Found port VGND of type SIGNAL
Power net:  VPWR
Ground net: VGND
Modified power connections of 5304 cells (Remaining: 0 ).