
reading lef ...

units:       1000
#layers:     13
#macros:     438
#vias:       25
#viarulegen: 25

reading def ...

design:      storage
die area:    ( 0 0 ) ( 450000 950000 )
trackPts:    12
defvias:     5
#components: 4931
#terminals:  160
#snets:      2
#nets:       158

reading guide ...

#guides:     2654
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx
List of default vias:
  Layer mcon
    default via: L1M1_PR_MR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: via2_FR
  Layer via3
    default via: M3M4_PR_M
  Layer via4
    default via: via4_FR
Writing reference output def...

libcell analysis ...

instance analysis ...
#unique instances = 20

init region query ...
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

FR_MASTERSLICE shape region query size = 0
FR_VIA shape region query size = 0
li1 shape region query size = 26220
mcon shape region query size = 62062
met1 shape region query size = 11228
via shape region query size = 2736
met2 shape region query size = 1370
via2 shape region query size = 2736
met3 shape region query size = 1568
via3 shape region query size = 2740
met4 shape region query size = 1051
via4 shape region query size = 109
met5 shape region query size = 148


start pin access
  complete 100 pins
  complete 200 pins
  complete 244 pins
  complete 13 unique inst patterns
  complete 104 groups
Expt1 runtime (pin-level access point gen): 0.148989
Expt2 runtime (design-level access pattern gen): 0.000363704
#scanned instances     = 4931
#unique  instances     = 20
#stdCellGenAp          = 24
#stdCellValidPlanarAp  = 0
#stdCellValidViaAp     = 24
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 104
#instTermValidViaApCnt = 0
#macroGenAp            = 794
#macroValidPlanarAp    = 794
#macroValidViaAp       = 0
#macroNoAp             = 0

complete pin access
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 21.48 (MB), peak = 22.51 (MB)

post process guides ...
GCELLGRID X -1 DO 147 STEP 6440 ;
GCELLGRID Y -1 DO 69 STEP 6440 ;
  complete FR_MASTERSLICE
  complete FR_VIA
  complete li1
  complete mcon
  complete met1
  complete via
  complete met2
  complete via2
  complete met3
  complete via3
  complete met4
  complete via4
  complete met5

building cmap ... 

init guide query ...
  complete FR_MASTERSLICE (guide)
  complete FR_VIA (guide)
  complete li1 (guide)
  complete mcon (guide)
  complete met1 (guide)
  complete via (guide)
  complete met2 (guide)
  complete via2 (guide)
  complete met3 (guide)
  complete via3 (guide)
  complete met4 (guide)
  complete via4 (guide)
  complete met5 (guide)

FR_MASTERSLICE guide region query size = 0
FR_VIA guide region query size = 0
li1 guide region query size = 104
mcon guide region query size = 0
met1 guide region query size = 445
via guide region query size = 0
met2 guide region query size = 581
via2 guide region query size = 0
met3 guide region query size = 413
via3 guide region query size = 0
met4 guide region query size = 205
via4 guide region query size = 0
met5 guide region query size = 0

init gr pin query ...


start track assignment
Done with 890 vertical wires in 2 frboxes and 858 horizontal wires in 3 frboxes.
Done with 194 vertical wires in 2 frboxes and 178 horizontal wires in 3 frboxes.

complete track assignment
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 32.76 (MB), peak = 39.53 (MB)

post processing ...

start routing data preparation
initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 32.77 (MB), peak = 39.53 (MB)

start detail routing ...
start 0th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 53.50 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 54.36 (MB)
    completing 30% with 1213 violations
    elapsed time = 00:00:01, memory = 52.38 (MB)
    completing 40% with 1213 violations
    elapsed time = 00:00:01, memory = 53.45 (MB)
    completing 50% with 1213 violations
    elapsed time = 00:00:01, memory = 52.94 (MB)
    completing 60% with 1027 violations
    elapsed time = 00:00:02, memory = 49.49 (MB)
    completing 70% with 1027 violations
    elapsed time = 00:00:02, memory = 48.59 (MB)
    completing 80% with 1128 violations
    elapsed time = 00:00:03, memory = 49.27 (MB)
    completing 90% with 1128 violations
    elapsed time = 00:00:03, memory = 49.35 (MB)
    completing 100% with 1002 violations
    elapsed time = 00:00:04, memory = 45.30 (MB)
  number of violations = 1002
cpu time = 00:00:13, elapsed time = 00:00:05, memory = 43.97 (MB), peak = 392.31 (MB)
total wire length = 117658 um
total wire length on LAYER li1 = 81 um
total wire length on LAYER met1 = 35780 um
total wire length on LAYER met2 = 52527 um
total wire length on LAYER met3 = 17359 um
total wire length on LAYER met4 = 10814 um
total wire length on LAYER met5 = 1093 um
total number of vias = 1780
up-via summary (total 1780):

-----------------------
 FR_MASTERSLICE       0
            li1     154
           met1     815
           met2     469
           met3     288
           met4      54
-----------------------
                   1780


start 1st optimization iteration ...
    completing 10% with 1002 violations
    elapsed time = 00:00:00, memory = 57.57 (MB)
    completing 20% with 1002 violations
    elapsed time = 00:00:00, memory = 57.57 (MB)
    completing 30% with 803 violations
    elapsed time = 00:00:01, memory = 57.35 (MB)
    completing 40% with 803 violations
    elapsed time = 00:00:01, memory = 59.97 (MB)
    completing 50% with 803 violations
    elapsed time = 00:00:01, memory = 57.40 (MB)
    completing 60% with 603 violations
    elapsed time = 00:00:01, memory = 50.26 (MB)
    completing 70% with 603 violations
    elapsed time = 00:00:02, memory = 57.58 (MB)
    completing 80% with 437 violations
    elapsed time = 00:00:02, memory = 50.18 (MB)
    completing 90% with 437 violations
    elapsed time = 00:00:02, memory = 50.18 (MB)
    completing 100% with 141 violations
    elapsed time = 00:00:03, memory = 44.02 (MB)
  number of violations = 141
cpu time = 00:00:10, elapsed time = 00:00:03, memory = 43.98 (MB), peak = 392.31 (MB)
total wire length = 117776 um
total wire length on LAYER li1 = 460 um
total wire length on LAYER met1 = 35763 um
total wire length on LAYER met2 = 52204 um
total wire length on LAYER met3 = 17420 um
total wire length on LAYER met4 = 10745 um
total wire length on LAYER met5 = 1182 um
total number of vias = 1701
up-via summary (total 1701):

-----------------------
 FR_MASTERSLICE       0
            li1     184
           met1     802
           met2     454
           met3     255
           met4       6
-----------------------
                   1701


start 2nd optimization iteration ...
    completing 10% with 141 violations
    elapsed time = 00:00:00, memory = 46.74 (MB)
    completing 20% with 141 violations
    elapsed time = 00:00:00, memory = 46.74 (MB)
    completing 30% with 146 violations
    elapsed time = 00:00:00, memory = 46.59 (MB)
    completing 40% with 146 violations
    elapsed time = 00:00:00, memory = 53.84 (MB)
    completing 50% with 146 violations
    elapsed time = 00:00:00, memory = 59.25 (MB)
    completing 60% with 158 violations
    elapsed time = 00:00:01, memory = 56.77 (MB)
    completing 70% with 158 violations
    elapsed time = 00:00:01, memory = 56.84 (MB)
    completing 80% with 168 violations
    elapsed time = 00:00:01, memory = 59.25 (MB)
    completing 90% with 168 violations
    elapsed time = 00:00:01, memory = 62.86 (MB)
    completing 100% with 142 violations
    elapsed time = 00:00:01, memory = 43.98 (MB)
  number of violations = 142
cpu time = 00:00:05, elapsed time = 00:00:02, memory = 43.98 (MB), peak = 392.31 (MB)
total wire length = 117826 um
total wire length on LAYER li1 = 272 um
total wire length on LAYER met1 = 35928 um
total wire length on LAYER met2 = 52401 um
total wire length on LAYER met3 = 17309 um
total wire length on LAYER met4 = 10732 um
total wire length on LAYER met5 = 1182 um
total number of vias = 1789
up-via summary (total 1789):

-----------------------
 FR_MASTERSLICE       0
            li1     202
           met1     861
           met2     468
           met3     252
           met4       6
-----------------------
                   1789


start 3rd optimization iteration ...
    completing 10% with 142 violations
    elapsed time = 00:00:01, memory = 64.52 (MB)
    completing 20% with 142 violations
    elapsed time = 00:00:01, memory = 62.72 (MB)
    completing 30% with 131 violations
    elapsed time = 00:00:02, memory = 59.76 (MB)
    completing 40% with 131 violations
    elapsed time = 00:00:02, memory = 59.76 (MB)
    completing 50% with 131 violations
    elapsed time = 00:00:02, memory = 58.65 (MB)
    completing 60% with 112 violations
    elapsed time = 00:00:02, memory = 54.85 (MB)
    completing 70% with 112 violations
    elapsed time = 00:00:02, memory = 56.18 (MB)
    completing 80% with 74 violations
    elapsed time = 00:00:03, memory = 46.54 (MB)
    completing 90% with 74 violations
    elapsed time = 00:00:03, memory = 46.54 (MB)
    completing 100% with 57 violations
    elapsed time = 00:00:04, memory = 46.54 (MB)
  number of violations = 57
cpu time = 00:00:11, elapsed time = 00:00:04, memory = 43.96 (MB), peak = 392.31 (MB)
total wire length = 117820 um
total wire length on LAYER li1 = 529 um
total wire length on LAYER met1 = 36016 um
total wire length on LAYER met2 = 52047 um
total wire length on LAYER met3 = 17268 um
total wire length on LAYER met4 = 10777 um
total wire length on LAYER met5 = 1182 um
total number of vias = 1886
up-via summary (total 1886):

-----------------------
 FR_MASTERSLICE       0
            li1     223
           met1     900
           met2     495
           met3     262
           met4       6
-----------------------
                   1886


start 4th optimization iteration ...
    completing 10% with 57 violations
    elapsed time = 00:00:00, memory = 57.33 (MB)
    completing 20% with 57 violations
    elapsed time = 00:00:00, memory = 59.90 (MB)
    completing 30% with 29 violations
    elapsed time = 00:00:01, memory = 58.25 (MB)
    completing 40% with 29 violations
    elapsed time = 00:00:01, memory = 58.25 (MB)
    completing 50% with 29 violations
    elapsed time = 00:00:01, memory = 57.21 (MB)
    completing 60% with 20 violations
    elapsed time = 00:00:01, memory = 43.92 (MB)
    completing 70% with 20 violations
    elapsed time = 00:00:01, memory = 56.89 (MB)
    completing 80% with 7 violations
    elapsed time = 00:00:01, memory = 43.94 (MB)
    completing 90% with 7 violations
    elapsed time = 00:00:01, memory = 43.96 (MB)
    completing 100% with 4 violations
    elapsed time = 00:00:01, memory = 43.96 (MB)
  number of violations = 4
cpu time = 00:00:05, elapsed time = 00:00:02, memory = 43.96 (MB), peak = 392.31 (MB)
total wire length = 117843 um
total wire length on LAYER li1 = 633 um
total wire length on LAYER met1 = 36152 um
total wire length on LAYER met2 = 51902 um
total wire length on LAYER met3 = 17143 um
total wire length on LAYER met4 = 10828 um
total wire length on LAYER met5 = 1182 um
total number of vias = 1916
up-via summary (total 1916):

-----------------------
 FR_MASTERSLICE       0
            li1     237
           met1     908
           met2     501
           met3     264
           met4       6
-----------------------
                   1916


start 5th optimization iteration ...
    completing 10% with 4 violations
    elapsed time = 00:00:00, memory = 54.39 (MB)
    completing 20% with 4 violations
    elapsed time = 00:00:00, memory = 54.91 (MB)
    completing 30% with 1 violations
    elapsed time = 00:00:00, memory = 49.65 (MB)
    completing 40% with 1 violations
    elapsed time = 00:00:00, memory = 46.94 (MB)
    completing 50% with 1 violations
    elapsed time = 00:00:00, memory = 48.20 (MB)
    completing 60% with 1 violations
    elapsed time = 00:00:00, memory = 48.14 (MB)
    completing 70% with 1 violations
    elapsed time = 00:00:00, memory = 46.39 (MB)
    completing 80% with 1 violations
    elapsed time = 00:00:00, memory = 46.54 (MB)
    completing 90% with 1 violations
    elapsed time = 00:00:00, memory = 47.30 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 43.96 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 43.96 (MB), peak = 392.31 (MB)
total wire length = 117854 um
total wire length on LAYER li1 = 678 um
total wire length on LAYER met1 = 36159 um
total wire length on LAYER met2 = 51860 um
total wire length on LAYER met3 = 17145 um
total wire length on LAYER met4 = 10828 um
total wire length on LAYER met5 = 1182 um
total number of vias = 1920
up-via summary (total 1920):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1     910
           met2     501
           met3     264
           met4       6
-----------------------
                   1920


start 17th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 48.29 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 48.48 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 48.37 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 44.70 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 44.47 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 44.05 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 44.25 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 44.06 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 44.00 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 45.62 (MB)
  number of violations = 0
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 45.62 (MB), peak = 392.31 (MB)
total wire length = 117854 um
total wire length on LAYER li1 = 678 um
total wire length on LAYER met1 = 36159 um
total wire length on LAYER met2 = 51860 um
total wire length on LAYER met3 = 17145 um
total wire length on LAYER met4 = 10828 um
total wire length on LAYER met5 = 1182 um
total number of vias = 1920
up-via summary (total 1920):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1     910
           met2     501
           met3     264
           met4       6
-----------------------
                   1920


start 25th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 45.79 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 45.79 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 46.17 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 46.77 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 46.64 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 45.09 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 45.09 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 45.20 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 45.08 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 46.85 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 46.85 (MB), peak = 392.31 (MB)
total wire length = 117854 um
total wire length on LAYER li1 = 678 um
total wire length on LAYER met1 = 36159 um
total wire length on LAYER met2 = 51860 um
total wire length on LAYER met3 = 17145 um
total wire length on LAYER met4 = 10828 um
total wire length on LAYER met5 = 1182 um
total number of vias = 1920
up-via summary (total 1920):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1     910
           met2     501
           met3     264
           met4       6
-----------------------
                   1920


start 33rd optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 45.19 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 45.19 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 45.29 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 45.28 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 45.23 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 46.12 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 46.12 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 45.22 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 44.11 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 44.76 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 44.76 (MB), peak = 392.31 (MB)
total wire length = 117854 um
total wire length on LAYER li1 = 678 um
total wire length on LAYER met1 = 36159 um
total wire length on LAYER met2 = 51860 um
total wire length on LAYER met3 = 17145 um
total wire length on LAYER met4 = 10828 um
total wire length on LAYER met5 = 1182 um
total number of vias = 1920
up-via summary (total 1920):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1     910
           met2     501
           met3     264
           met4       6
-----------------------
                   1920


start 41st optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 44.03 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 44.03 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 44.04 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 44.12 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 44.00 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 45.41 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 45.41 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 44.95 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 44.10 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 44.04 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 44.04 (MB), peak = 392.31 (MB)
total wire length = 117854 um
total wire length on LAYER li1 = 678 um
total wire length on LAYER met1 = 36159 um
total wire length on LAYER met2 = 51860 um
total wire length on LAYER met3 = 17145 um
total wire length on LAYER met4 = 10828 um
total wire length on LAYER met5 = 1182 um
total number of vias = 1920
up-via summary (total 1920):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1     910
           met2     501
           met3     264
           met4       6
-----------------------
                   1920


start 49th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 46.29 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 46.29 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 45.81 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 45.04 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 45.04 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 45.36 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 44.70 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 45.20 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 44.69 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 44.54 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 44.54 (MB), peak = 392.31 (MB)
total wire length = 117854 um
total wire length on LAYER li1 = 678 um
total wire length on LAYER met1 = 36159 um
total wire length on LAYER met2 = 51860 um
total wire length on LAYER met3 = 17145 um
total wire length on LAYER met4 = 10828 um
total wire length on LAYER met5 = 1182 um
total number of vias = 1920
up-via summary (total 1920):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1     910
           met2     501
           met3     264
           met4       6
-----------------------
                   1920


start 57th optimization iteration ...
    completing 10% with 0 violations
    elapsed time = 00:00:00, memory = 45.32 (MB)
    completing 20% with 0 violations
    elapsed time = 00:00:00, memory = 45.32 (MB)
    completing 30% with 0 violations
    elapsed time = 00:00:00, memory = 44.61 (MB)
    completing 40% with 0 violations
    elapsed time = 00:00:00, memory = 43.96 (MB)
    completing 50% with 0 violations
    elapsed time = 00:00:00, memory = 45.24 (MB)
    completing 60% with 0 violations
    elapsed time = 00:00:00, memory = 45.95 (MB)
    completing 70% with 0 violations
    elapsed time = 00:00:00, memory = 45.95 (MB)
    completing 80% with 0 violations
    elapsed time = 00:00:00, memory = 46.12 (MB)
    completing 90% with 0 violations
    elapsed time = 00:00:00, memory = 43.98 (MB)
    completing 100% with 0 violations
    elapsed time = 00:00:00, memory = 45.41 (MB)
  number of violations = 0
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 45.41 (MB), peak = 392.31 (MB)
total wire length = 117854 um
total wire length on LAYER li1 = 678 um
total wire length on LAYER met1 = 36159 um
total wire length on LAYER met2 = 51860 um
total wire length on LAYER met3 = 17145 um
total wire length on LAYER met4 = 10828 um
total wire length on LAYER met5 = 1182 um
total number of vias = 1920
up-via summary (total 1920):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1     910
           met2     501
           met3     264
           met4       6
-----------------------
                   1920


complete detail routing
total wire length = 117854 um
total wire length on LAYER li1 = 678 um
total wire length on LAYER met1 = 36159 um
total wire length on LAYER met2 = 51860 um
total wire length on LAYER met3 = 17145 um
total wire length on LAYER met4 = 10828 um
total wire length on LAYER met5 = 1182 um
total number of vias = 1920
up-via summary (total 1920):

-----------------------
 FR_MASTERSLICE       0
            li1     239
           met1     910
           met2     501
           met3     264
           met4       6
-----------------------
                   1920

cpu time = 00:00:54, elapsed time = 00:00:21, memory = 45.41 (MB), peak = 392.31 (MB)

post processing ...

Runtime taken (hrt): 22.6143