
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 57 cell types from liberty file.

2. Executing Liberty frontend.
Imported 8 cell types from liberty file.

3. Executing Verilog-2005 frontend: /project/openlane/caravel/../../verilog//rtl/defines.v
Parsing Verilog input from `/project/openlane/caravel/../../verilog//rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /project/openlane/caravel/../../verilog//rtl/pads.v
Parsing Verilog input from `/project/openlane/caravel/../../verilog//rtl/pads.v' to AST representation.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /project/openlane/caravel/../../verilog//rtl/chip_io.v
Parsing Verilog input from `/project/openlane/caravel/../../verilog//rtl/chip_io.v' to AST representation.
Generating RTLIL representation for module `\chip_io'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /project/openlane/caravel/../../verilog//rtl/mgmt_core.v
Parsing Verilog input from `/project/openlane/caravel/../../verilog//rtl/mgmt_core.v' to AST representation.
Generating RTLIL representation for module `\mgmt_core'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /project/openlane/caravel/../../verilog//rtl/storage.v
Parsing Verilog input from `/project/openlane/caravel/../../verilog//rtl/storage.v' to AST representation.
Generating RTLIL representation for module `\storage'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /project/openlane/caravel/../../verilog//rtl/user_project_wrapper.v
Parsing Verilog input from `/project/openlane/caravel/../../verilog//rtl/user_project_wrapper.v' to AST representation.
Generating RTLIL representation for module `\user_project_wrapper'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /project/openlane/caravel/../../verilog//rtl/mgmt_protect.v
Parsing Verilog input from `/project/openlane/caravel/../../verilog//rtl/mgmt_protect.v' to AST representation.
Generating RTLIL representation for module `\mgmt_protect'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /project/openlane/caravel/../../verilog//rtl/gpio_control_block.v
Parsing Verilog input from `/project/openlane/caravel/../../verilog//rtl/gpio_control_block.v' to AST representation.
Generating RTLIL representation for module `\gpio_control_block'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: /project/openlane/caravel/../../verilog//rtl/user_id_programming.v
Parsing Verilog input from `/project/openlane/caravel/../../verilog//rtl/user_id_programming.v' to AST representation.
Generating RTLIL representation for module `\user_id_programming'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: /project/openlane/caravel/../../verilog//rtl/simple_por.v
Parsing Verilog input from `/project/openlane/caravel/../../verilog//rtl/simple_por.v' to AST representation.
Generating RTLIL representation for module `\simple_por'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: /project/openlane/caravel/../../verilog//rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
Parsing Verilog input from `/project/openlane/caravel/../../verilog//rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v' to AST representation.
Generating RTLIL representation for module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: /project/openlane/caravel/../../verilog//rtl/caravel.v
Parsing Verilog input from `/project/openlane/caravel/../../verilog//rtl/caravel.v' to AST representation.
Generating RTLIL representation for module `\caravel'.
Successfully finished Verilog frontend.

15. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/caravel/runs/caravel/tmp/synthesis/hierarchy.dot'.
Dumping module caravel to page 1.

16. Executing HIERARCHY pass (managing design hierarchy).

16.1. Analyzing design hierarchy..
Top module:  \caravel

16.2. Analyzing design hierarchy..
Top module:  \caravel
Removed 0 unused modules.

17. Executing FLATTEN pass (flatten design).

18. Printing statistics.

=== caravel ===

   Number of wires:                140
   Number of wire bits:           2302
   Number of public wires:         140
   Number of public wire bits:    2302
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 46
     chip_io                         1
     gpio_control_block             38
     mgmt_core                       1
     mgmt_protect                    1
     simple_por                      1
     sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped      1
     storage                         1
     user_id_programming             1
     user_project_wrapper            1

19. Executing SPLITNETS pass (splitting up multi-bit signals).

20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \caravel..

21. Executing CHECK pass (checking for obvious problems).
checking module caravel..
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[9]:
    port mgmt_gpio_in[0] of cell gpio_control_in[9] (gpio_control_block)
    port mgmt_out_data[9] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[8]:
    port mgmt_gpio_in[0] of cell gpio_control_in[8] (gpio_control_block)
    port mgmt_out_data[8] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[7]:
    port mgmt_gpio_in[0] of cell gpio_control_in[7] (gpio_control_block)
    port mgmt_out_data[7] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[6]:
    port mgmt_gpio_in[0] of cell gpio_control_in[6] (gpio_control_block)
    port mgmt_out_data[6] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[5]:
    port mgmt_gpio_in[0] of cell gpio_control_in[5] (gpio_control_block)
    port mgmt_out_data[5] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[4]:
    port mgmt_gpio_in[0] of cell gpio_control_in[4] (gpio_control_block)
    port mgmt_out_data[4] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[3]:
    port mgmt_gpio_in[0] of cell gpio_control_in[3] (gpio_control_block)
    port mgmt_out_data[3] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[37]:
    port mgmt_gpio_in[0] of cell gpio_control_in[37] (gpio_control_block)
    port mgmt_out_data[37] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[36]:
    port mgmt_gpio_in[0] of cell gpio_control_in[36] (gpio_control_block)
    port mgmt_out_data[36] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[35]:
    port mgmt_gpio_in[0] of cell gpio_control_in[35] (gpio_control_block)
    port mgmt_out_data[35] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[34]:
    port mgmt_gpio_in[0] of cell gpio_control_in[34] (gpio_control_block)
    port mgmt_out_data[34] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[33]:
    port mgmt_gpio_in[0] of cell gpio_control_in[33] (gpio_control_block)
    port mgmt_out_data[33] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[32]:
    port mgmt_gpio_in[0] of cell gpio_control_in[32] (gpio_control_block)
    port mgmt_out_data[32] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[31]:
    port mgmt_gpio_in[0] of cell gpio_control_in[31] (gpio_control_block)
    port mgmt_out_data[31] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[30]:
    port mgmt_gpio_in[0] of cell gpio_control_in[30] (gpio_control_block)
    port mgmt_out_data[30] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[2]:
    port mgmt_gpio_in[0] of cell gpio_control_in[2] (gpio_control_block)
    port mgmt_out_data[2] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[29]:
    port mgmt_gpio_in[0] of cell gpio_control_in[29] (gpio_control_block)
    port mgmt_out_data[29] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[28]:
    port mgmt_gpio_in[0] of cell gpio_control_in[28] (gpio_control_block)
    port mgmt_out_data[28] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[27]:
    port mgmt_gpio_in[0] of cell gpio_control_in[27] (gpio_control_block)
    port mgmt_out_data[27] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[26]:
    port mgmt_gpio_in[0] of cell gpio_control_in[26] (gpio_control_block)
    port mgmt_out_data[26] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[25]:
    port mgmt_gpio_in[0] of cell gpio_control_in[25] (gpio_control_block)
    port mgmt_out_data[25] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[24]:
    port mgmt_gpio_in[0] of cell gpio_control_in[24] (gpio_control_block)
    port mgmt_out_data[24] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[23]:
    port mgmt_gpio_in[0] of cell gpio_control_in[23] (gpio_control_block)
    port mgmt_out_data[23] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[22]:
    port mgmt_gpio_in[0] of cell gpio_control_in[22] (gpio_control_block)
    port mgmt_out_data[22] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[21]:
    port mgmt_gpio_in[0] of cell gpio_control_in[21] (gpio_control_block)
    port mgmt_out_data[21] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[20]:
    port mgmt_gpio_in[0] of cell gpio_control_in[20] (gpio_control_block)
    port mgmt_out_data[20] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[19]:
    port mgmt_gpio_in[0] of cell gpio_control_in[19] (gpio_control_block)
    port mgmt_out_data[19] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[18]:
    port mgmt_gpio_in[0] of cell gpio_control_in[18] (gpio_control_block)
    port mgmt_out_data[18] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[17]:
    port mgmt_gpio_in[0] of cell gpio_control_in[17] (gpio_control_block)
    port mgmt_out_data[17] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[16]:
    port mgmt_gpio_in[0] of cell gpio_control_in[16] (gpio_control_block)
    port mgmt_out_data[16] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[15]:
    port mgmt_gpio_in[0] of cell gpio_control_in[15] (gpio_control_block)
    port mgmt_out_data[15] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[14]:
    port mgmt_gpio_in[0] of cell gpio_control_in[14] (gpio_control_block)
    port mgmt_out_data[14] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[13]:
    port mgmt_gpio_in[0] of cell gpio_control_in[13] (gpio_control_block)
    port mgmt_out_data[13] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[12]:
    port mgmt_gpio_in[0] of cell gpio_control_in[12] (gpio_control_block)
    port mgmt_out_data[12] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[11]:
    port mgmt_gpio_in[0] of cell gpio_control_in[11] (gpio_control_block)
    port mgmt_out_data[11] of cell soc (mgmt_core)
Warning: multiple conflicting drivers for caravel.\mgmt_io_in[10]:
    port mgmt_gpio_in[0] of cell gpio_control_in[10] (gpio_control_block)
    port mgmt_out_data[10] of cell soc (mgmt_core)
found and reported 36 problems.

22. Printing statistics.

=== caravel ===

   Number of wires:               2262
   Number of wire bits:           2302
   Number of public wires:        2262
   Number of public wire bits:    2302
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 46
     chip_io                         1
     gpio_control_block             38
     mgmt_core                       1
     mgmt_protect                    1
     simple_por                      1
     sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped      1
     storage                         1
     user_id_programming             1
     user_project_wrapper            1

   Area for cell type \chip_io is unknown!
   Area for cell type \mgmt_core is unknown!
   Area for cell type \storage is unknown!
   Area for cell type \user_project_wrapper is unknown!
   Area for cell type \mgmt_protect is unknown!
   Area for cell type \gpio_control_block is unknown!
   Area for cell type \user_id_programming is unknown!
   Area for cell type \simple_por is unknown!
   Area for cell type \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped is unknown!

23. Executing Verilog backend.
Dumping module `\caravel'.

Warnings: 36 unique messages, 36 total
End of script. Logfile hash: d61c85f712, CPU: user 0.76s system 0.01s, MEM: 26.51 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 42% 2x write_verilog (0 sec), 17% 2x stat (0 sec), ...