diff --git a/verilog/rtl/clock_div.v b/verilog/rtl/clock_div.v
index 4b698a4..6f898df 100644
--- a/verilog/rtl/clock_div.v
+++ b/verilog/rtl/clock_div.v
@@ -29,8 +29,8 @@
     // Divider value synchronization (double-synchronized to avoid metastability)
     always @(posedge out or negedge resetb) begin
 	if (resetb == 1'b0) begin
-	    syncN <= 'd2;	// Default to divide-by-2 on system reset
-	    syncNp <= 'd2;	// Default to divide-by-2 on system reset
+	    syncN <= `CLK_DIV;	// Default to divide-by-2 on system reset
+	    syncNp <= `CLK_DIV;	// Default to divide-by-2 on system reset
 	end else begin
 	    syncNp <= N;
 	    syncN <= syncNp;
@@ -71,7 +71,7 @@
     // positive edge counter/divider
     always @(posedge clk or negedge resetb) begin
 	if (resetb == 1'b0) begin
-	    counter <= N;
+	    counter <= `CLK_DIV;
 	    out_counter <= 1;
 	end else if (rst_pulse) begin
 	    counter <= N;
@@ -87,15 +87,16 @@
     end
  
     reg [SIZE-1:0] initial_begin;	// this is used to offset the negative edge counter
-    wire [SIZE:0] interm_3;		// from the positive edge counter in order to
-    assign interm_3 = {1'b0,N} + 2'b11;	// guarante 50% duty cycle.
- 
+    // wire [SIZE:0] interm_3;		// from the positive edge counter in order to
+    // assign interm_3 = {1'b0,N} + 2'b11;	// guarante 50% duty cycle.
+    localparam [SIZE:0] interm_3 = {1'b0,`CLK_DIV} + 2'b11;
+
     // Counter driven by negative edge of clock.
 
     always @(negedge clk or negedge resetb) begin
 	if (resetb == 1'b0) begin
 	    // reset the counter at system reset
-	    counter2 <= N;
+	    counter2 <= `CLK_DIV;
 	    initial_begin <= interm_3[SIZE:1];
 	    out_counter2 <= 1;
 	end else if (rst_pulse) begin
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index 1aec155..a72f0c8 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -18,4 +18,7 @@
 
 // not really parameterized but just to easily keep track of the number
 // of ram_block across different modules
-`define RAM_BLOCKS 2
\ No newline at end of file
+`define RAM_BLOCKS 2
+
+// Clock divisor default value
+`define CLK_DIV 3'b010
\ No newline at end of file