)]}'
{
  "commit": "927f58ae4a9945817980e14a0ee85683d80a4e99",
  "tree": "84ac570b501007e5784bbac8c063ccc832f9472d",
  "parents": [
    "0753acd2dd42a736649c149107ff01b089f951f8"
  ],
  "author": {
    "name": "Kevin",
    "email": "kevindai02@outlook.com",
    "time": "Thu Dec 17 20:43:24 2020 -0500"
  },
  "committer": {
    "name": "Kevin",
    "email": "kevindai02@outlook.com",
    "time": "Thu Dec 17 20:43:24 2020 -0500"
  },
  "message": "Update submodule\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "59961ec3bad9d5d7409151edf3cccd05aeb62f8a",
      "old_mode": 57344,
      "old_path": "verilog/rtl/hs32cpu",
      "new_id": "63e3be34fb9adeb1dfb411f8b6b75598e8d553b0",
      "new_mode": 57344,
      "new_path": "verilog/rtl/hs32cpu"
    }
  ]
}