diff --git a/verilog/dv/caravel/hs32_soc/test4/Makefile b/verilog/dv/caravel/hs32_soc/test4/Makefile
index a2f250a..e7a30d6 100644
--- a/verilog/dv/caravel/hs32_soc/test4/Makefile
+++ b/verilog/dv/caravel/hs32_soc/test4/Makefile
@@ -1,7 +1,7 @@
-FIRMWARE_PATH = ../..
+FIRMWARE_PATH = ../../
 RTL_PATH = ../../../../rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
+BEHAVIOURAL_MODELS = ../../
+VERILOG_PATH = ../../../../
 
 GCC_PATH?=/opt/riscv32i/bin
 GCC_PREFIX?=riscv32-unknown-elf
@@ -9,6 +9,8 @@
 
 .SUFFIXES:
 
+SIM?=RTL
+
 PATTERN = test4
 
 all:  ${PATTERN:=.vcd}
@@ -16,18 +18,24 @@
 hex:  ${PATTERN:=.hex}
 
 %.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
 	iverilog -DSIM -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(RTL_PATH)/hs32cpu \
-	-o $@ $<
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	-I $(RTL_PATH)/hs32cpu $< -o $@
+else
+	iverilog -DSIM -DFUNCTIONAL -DGL_SIM -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	-I $(RTL_PATH)/hs32cpu -I $(VERILOG_PATH) $< -o $@
+endif
 
 %.vcd: %.vvp
-	vvp $<
+	vvp $< -fst-speed $(OPT)
 
 %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
 	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
 
 %.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
 	# to fix flash base address
 	sed -i 's/@10000000/@00000000/g' $@
 
@@ -37,6 +45,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.idx
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.idx *.fst
 
 .PHONY: clean hex all
diff --git a/verilog/dv/caravel/hs32_soc/test4/README.md b/verilog/dv/caravel/hs32_soc/test4/README.md
index fa3ecde..66b2a44 100644
--- a/verilog/dv/caravel/hs32_soc/test4/README.md
+++ b/verilog/dv/caravel/hs32_soc/test4/README.md
@@ -16,6 +16,14 @@
 | I-Type | `oooo_oooo` | `dddd_mmmm` | `iiii_iiii` | `iiii_iiii` |
 | R-Type | `oooo_oooo` | `dddd_mmmm` | `nnnn_ssss` | `sDDb_bxxx` |
 
+## Usage
+
+Use `make` to run test.
+
+Results should match the *Expected result* listed below.
+
+Test will display `Passed all cases.` or `Failed.` message indicating errors.
+
 ## Assembly
 
 ```assembly
@@ -64,27 +72,3 @@
 - [x] `R5   = 0x0B09`
 - [x] `R6   = 0x000F`
 - [x] `R7   = 0x0F00`
-
-
-
-0x 24 00 BE EF
-0x 24 10 0A DD
-0x 20 20 10 00
-0x 60 00 10 00
-0x 30 02 00 00
-0x 10 12 00 00
-0x 24 30 0B AD
-0x 24 50 22 62
-0x 20 50 58 00
-0x 24 50 00 00
-0x 30 53 00 00
-0x 24 40 0B AD
-0x 24 50 21 66
-0x 20 50 58 00
-0x 24 50 00 00
-0x 30 54 00 00
-0x 68 00 10 00
-0x 52 00 0B AD
-0x 68 01 20 00
-0x 59 00 0B 09
-0x 20 70 68 00
\ No newline at end of file
diff --git a/verilog/dv/caravel/hs32_soc/test4/test4_tb.v b/verilog/dv/caravel/hs32_soc/test4/test4_tb.v
index 0101ab0..26250e7 100644
--- a/verilog/dv/caravel/hs32_soc/test4/test4_tb.v
+++ b/verilog/dv/caravel/hs32_soc/test4/test4_tb.v
@@ -1,7 +1,9 @@
-`define DBG1
+`ifdef GL_SIM
+	`define SRAM_LOG_READ
+	`define SRAM_LOG_WRITE
+`endif
 
 `default_nettype none
-
 `timescale 1 ns / 1 ns
 
 `include "caravel.v"
@@ -9,14 +11,22 @@
 
 module tb();
 	parameter TEST_ID = 4;
+	parameter FILENAME = "test4.hex";
+
+	function [0:0] implies;
+		input [0:0] p, q;
+		begin
+			implies = (!p) || q;
+		end
+	endfunction
 
 	reg clock;
-  	reg RSTB;
+	reg RSTB;
 	reg power1, power2;
 	reg power3, power4;
 
-  	wire gpio;
-  	wire [37:0] mprj_io;
+	wire gpio;
+	wire [37:0] mprj_io;
 	wire [7:0] mprj_io_0;
 
 	assign mprj_io_0 = mprj_io[7:0];
@@ -31,6 +41,8 @@
 		clock = 0;
 	end
 
+	reg failed = 1;
+
 	initial begin
 		$dumpfile("tb.vcd");
 		$dumpvars(0, tb);
@@ -39,16 +51,23 @@
 			repeat (1000) @(posedge clock);
 			// $display("+1000 cycles");
 		end
-		//$display("%c[1;31m",27);
-		//$display("Test 1: Failed (timed out)!");
-		//$display("%c[0m",27);
+`ifndef GL_SIM
+		if(failed) begin
+			$display("%c[1;31mTest %0d: Failed. %c[0m", 27, TEST_ID, 27);
+			$finish_and_return(1);
+		end else begin
+			$display("%c[1;32mTest %0d: Passed all cases. %c[0m", 27, TEST_ID, 27);
+			$finish_and_return(0);
+		end
+`endif
 		$finish;
 	end
 
 	initial begin
 		RSTB <= 1'b0;
-		#2000;
+		#1000;
 		RSTB <= 1'b1;	    // Release reset
+		#2000;
 	end
 
 	initial begin			// Power-up sequence
@@ -66,18 +85,63 @@
 		power4 <= 1'b1;
 	end
 
+`ifndef GL_SIM
+	// Weak test cases for debugging
 	initial begin
-	    // Test cases go here
+		wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[0] == 32'h000F);
+		wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[1] == 32'h00F0);
+		wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[2] == 32'h0F00);
+		wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[3] == 32'hF000);
+		wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[4] == 32'h0BAD);
+		wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[5] == 32'h0B09);
+		wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[6] == 32'h000F);
+		wait(tb.uut.mprj.core1.core.EXEC.regfile_s.regs[7] == 32'h0F00);
+		failed = 0;
+		$display("%c[1;32mTest %0d: Passed weak cases. %c[0m", 27, TEST_ID, 27);
 	end
 
+	// Trigger when register write
+	wire trigger = tb.uut.mprj.core1.core.EXEC.regfile_s.we === 1'b1;
+	reg[31:0] step = 0;
+	always @(posedge clock) if(trigger) step <= step + 1;
+	// Strict assertations for each instruction
+	assert a0(clock, implies(trigger && step == 0,
+		tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 0 &&
+		tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'h000F));
+	assert a1(clock, implies(trigger && step == 1,
+		tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 1 &&
+		tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'h00F0));
+	assert a2(clock, implies(trigger && step == 2,
+		tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 2 &&
+		tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'h0F00));
+	assert a3(clock, implies(trigger && step == 3,
+		tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 3 &&
+		tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'hF000));
+	assert a4(clock, implies(trigger && step == 4,
+		tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 4 &&
+		tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'h0BAD));
+	assert a5(clock, implies(trigger && step == 5,
+		tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 5 &&
+		tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'h0B09));
+	assert a6(clock, implies(trigger && step == 6,
+		tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 6 &&
+		tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'h000F));
+	assert a7(clock, implies(trigger && step == 7,
+		tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == 7 &&
+		tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'h0F00));
+	/*assert a{{ STEP }}(clock, implies(trigger && step == {{ STEP }},
+		tb.uut.mprj.core1.core.EXEC.regfile_s.wadr == {{ REGISTER }} &&
+		tb.uut.mprj.core1.core.EXEC.regfile_s.din == 32'h{{ DATA }}));*/
+	assert a8(clock, step <= 8);
+
+	// If fault, then test failed
 	always @(*) begin
 		if(tb.uut.mprj.core1.core.EXEC.fault) begin
-			$display("%c[1;31m",27);
-			$display("Test %d: Faulted!", TEST_ID);
-			$display("%c[0m",27);
-			$finish;
+			$display("%c[1;31mTest %0d: Faulted. %c[0m", 27, TEST_ID, 27);
+			$finish_and_return(1);
 		end
 	end
+`endif
 
 	always @(mprj_io) begin
 		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
@@ -90,8 +154,8 @@
 
 	wire VDD3V3 = power1;
 	wire VDD1V8 = power2;
-	wire USER_VDD3V3 = power3;
-	wire USER_VDD1V8 = power4;
+	wire USER_VDD3V3 = power1;
+	wire USER_VDD1V8 = power2;
 	wire VSS = 1'b0;
 
 	caravel uut (
@@ -120,7 +184,7 @@
 	);
 
 	spiflash #(
-		.FILENAME("test4.hex")
+		.FILENAME(FILENAME)
 	) spiflash (
 		.csb(flash_csb),
 		.clk(flash_clk),
@@ -130,4 +194,16 @@
 		.io3()			// not used
 	);
 endmodule
+
+module assert(input clk, input test);
+    always @(posedge clk)
+    begin
+        if (test !== 1)
+        begin
+            $display("%c[1;31mAssertation failed in %m %c[0m", 27, 27);
+            $finish_and_return(1);
+        end
+    end
+endmodule
+
 `default_nettype wire