)]}'
{
  "commit": "b3cef09d7b95306bcba2dcbcc04b91f513e03d0f",
  "tree": "848cf662f9edb43b3eb617922b6df2def23af8b5",
  "parents": [
    "5ae07d9b4afeab093f9da812ec8cc29a1d800dbb"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu Oct 08 22:15:26 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu Oct 08 22:15:26 2020 -0400"
  },
  "message": "Removed temporary file.\n",
  "tree_diff": [
    {
      "type": "delete",
      "old_id": "25a3197c3b6927f7dfbb6f20461849fb3f63ad31",
      "old_mode": 33188,
      "old_path": "verilog/rtl/test.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    }
  ]
}