project:
  category: processor
  cover_image: doc/ciic_harness.png
  description: This is a minimal SoC built around a RISC-V based 5 stage pipelined
    core Buraq-Mini.
  foundry: SkyWater
  git_url: https://github.com/hadirkhan10/caravel_ibtida_soc.git
  layout_image: gds/caravel.png
  organization: Efabless
  organization_url: https://efabless.com
  owner: Hadir Khan
  process: SKY130
  project_id: '00010007'
  project_name: Ibtida SoC
  shuttle_url: https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-one/slot-007
  tags:
  - Open MPW
  - Chisel
  top_level_netlist: verilog/gl/caravel.v
  user_level_netlist: verilog/gl/user_project_wrapper.v
  version: '1.00'