--- 
project: 
  description: "This is a minimal SoC built around a RISC-V based 5 stage pipelined core Buraq-Mini."
  foundry: "SkyWater"
  git_url: "https://github.com/hadirkhan10/caravel_ibtida_soc.git"
  organization: "Efabless"
  organization_url: "https://efabless.com"
  owner: "Hadir Khan"
  process: "SKY130"
  project_name: "Ibtida SoC"
  tags: 
    - "Open MPW"
    - "Chisel"
  category: "processor"
  top_level_netlist: "verilog/gl/caravel.v"
  user_level_netlist: "verilog/gl/user_project_wrapper.v"
  version: "1.00"
  cover_image: "doc/ciic_harness.png"