diff --git a/README.md b/README.md
index 447fe6a..08083f0 100644
--- a/README.md
+++ b/README.md
@@ -1,28 +1,27 @@
-# CIIC Harness  
+# ابتدا(Ibtida) SoC
 
-A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
+ابتدا means the start of something. This is a minimal SoC built around a RISC-V based 5 stage pipelined core Buraq-Mini. Both the SoC and the core are made from scratch using CHISEL HDL. The CHISEL source code as well as the emitted verilog are provided in the relvant folders. It is still Work In Progress (WIP). The current SoC architecture is given below.
 
 <p align=”center”>
-<img src="/doc/ciic_harness.png" width="75%" height="75%"> 
+<img src="/doc/IbtidaSoC.png" > 
 </p>
 
-## Managment SoC
-The managment SoC runs firmware that can be used to:
-- Configure Mega Project I/O pads
-- Observe and control Mega Project signals (through on-chip logic analyzer probes)
-- Control the Mega Project power supply
+## Contributors
 
-The memory map of the management SoC can be found [here](verilog/rtl/README)
+Main contributors are:
+1. Engr. Muhammad Hadir Khan (RTL design based on CHISEL)(Owner).
+2. Sajjad Ahmed              (RTL design based on CHISEL).
+3. Engr. Aireen Aamir Jalal  (APR flow with OpenLANE RTL-GDSII).
 
-## Mega Project Area
-This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10).  See [the Caravel  premliminary datasheet](doc/caravel_datasheet.pdf) for details.
-The repository contains a [sample mega project](/verilog/rtl/user_proj_example.v) that contains a binary 32-bit up counter.  </br>
-
-<p align=”center”>
-<img src="/doc/counter_32.png" width="50%" height="50%">
-</p>
-
-The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:
-1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/caravel/user_proj_example/io_ports).
-2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/caravel/user_proj_example/la_test1).
-3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles:  [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2).
+Other contributors:
+1. Dr. Ali Ahmed (Supervisor).
+2. Dr. Roomi Naqvi (Supervisor).
+3. Engr. Farhan Ahmed Karim (Supervisor).
+4. Engr. Asad Hussain Jaffri (Supervisor).
+5. Zain Rizwan Khan
+6. Hamza Shabbir
+7. Uzair Khan
+8. Wajeh
+9. Usman Zain
+10. Zeeshan
+11. Waleed