diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c
index 03cb7f5..826bf59 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c
@@ -56,7 +56,7 @@
     while (reg_mprj_xfer == 1);
 
     // Start test
-    reg_mprj_data = 0xa0000000;
+    reg_mprj_datal = 0xa0000000;
 
     // Set clock to 64 kbaud and enable the UART
     reg_uart_clkdiv = 625;
@@ -70,6 +70,6 @@
     print(" |  __/| | (_| (_) |__) | (_) | |___\n");
     print(" |_|   |_|\\___\\___/____/ \\___/ \\____|\n");
 
-    reg_mprj_data = 0xab000000;
+    reg_mprj_datal = 0xab000000;
 }
 
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
index d139182..1922c63 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -14,7 +14,7 @@
 
 	wire gpio;
 	wire [15:0] checkbits;
-	wire [9:0] noconnect;
+	wire [36:0] mprj_io;
 	wire uart_tx;
 	wire uart_rx;
 
@@ -234,14 +234,32 @@
 	assign hk_csb = CSB;
 	assign hk_sdi = SDI;
 
+	assign checkbits = mprj_io[31:16];
+	assign uart_tx = mprj_io[6];
+	assign mprj_io[5] = uart_rx;
+	assign mprj_io[4] = hk_sck;
+	assign mprj_io[3] = hk_csb;
+	assign mprj_io[2] = hk_sdi;
+	assign SDO = mprj_io[1];
+	
 	caravel uut (
-		.vdd3v3	  (VDD3V3),
-		.vdd1v8	  (VDD1V8),
-		.vss	  (VSS),
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
 		.clock	  (clock),
 		.gpio     (gpio),
-		.mprj_io  ({checkbits, noconnect[9:1], uart_tx, uart_rx,
-				hk_sck, hk_csb, hk_sdi, SDO, noconnect[0]}),
+		.mprj_io  (mprj_io),
 		.flash_csb(flash_csb),
 		.flash_clk(flash_clk),
 		.flash_io0(flash_io0),
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem.c b/verilog/dv/caravel/mgmt_soc/mem/mem.c
index 8f4b542..7fbf8ad 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem.c
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem.c
@@ -39,7 +39,7 @@
     while (reg_mprj_xfer == 1);
 
     // start test
-    reg_mprj_data = 0xA0400000;
+    reg_mprj_datal = 0xA0400000;
 
     // Test Word R/W
     for (i=0; i<10; i++)
@@ -47,30 +47,30 @@
 	
     for (i=0; i<10; i++)
 	if ((i*5000+10000) != ints[i])
-	    reg_mprj_data = 0xAB400000;
+	    reg_mprj_datal = 0xAB400000;
 
-    reg_mprj_data = 0xAB410000;
+    reg_mprj_datal = 0xAB410000;
 	
     // Test Half Word R/W
-    reg_mprj_data = 0xA0200000;
+    reg_mprj_datal = 0xA0200000;
     for (i=0; i<10; i++)
 	shorts[i] = i*500 + 100;
 	
     for(i=0; i<10; i++)
 	if((i*500+100) != shorts[i])
-	    reg_mprj_data = 0xAB200000;
+	    reg_mprj_datal = 0xAB200000;
 
-    reg_mprj_data = 0xAB210000;
+    reg_mprj_datal = 0xAB210000;
 
     // Test byte R/W
-    reg_mprj_data = 0xA0100000;
+    reg_mprj_datal = 0xA0100000;
     for(i=0; i<10; i++)
 	bytes[i] = i*5 + 10;
 	
     for(i=0; i<10; i++)
 	if((i*5+10) != bytes[i])
-	    reg_mprj_data = 0xAB100000;
+	    reg_mprj_datal = 0xAB100000;
 
-    reg_mprj_data = 0xAB110000;
+    reg_mprj_datal = 0xAB110000;
 }
 
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
index d815b9d..c3afb8b 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -29,12 +29,14 @@
 
 	wire gpio;
         wire [15:0] checkbits;
-        wire [15:0] noconnect;
+	wire [36:0] mprj_io;
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;
 	wire flash_io1;
 
+	assign checkbits = mprj_io[31:16];
+
 	// External clock is used by default.  Make this artificially fast for the
 	// simulation.  Normally this would be a slow clock and the digital PLL
 	// would be the fast clock.
@@ -117,12 +119,23 @@
 	assign VDD1V8 = 1'b1;
 
 	caravel uut (
-		.vdd3v3	  (VDD3V3),
-		.vdd1v8	  (VDD1V8),
-		.vss	  (VSS),
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
 		.clock	  (clock),
 		.gpio     (gpio),
-                .mprj_io  ({checkbits, noconnect}),
+		.mprj_io  (mprj_io),
 		.flash_csb(flash_csb),
 		.flash_clk(flash_clk),
 		.flash_io0(flash_io0),
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
index e60de7e..c69bb9f 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
@@ -1,3 +1,4 @@
+
 FIRMWARE_PATH = ../..
 RTL_PATH = ../../../../rtl
 IP_PATH = ../../../../ip
@@ -20,13 +21,13 @@
 %.vcd: %.vvp
 	vvp $<
 
-%.elf: %.c  $(FIRMWARE_PATH)/sections.lds  $(FIRMWARE_PATH)/start.s
-	${GCC_PATH}/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,  $(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@  $(FIRMWARE_PATH)/start.s $<
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
 
 %.hex: %.elf
 	${GCC_PATH}/riscv32-unknown-elf-objcopy -O verilog $< $@ 
 	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
+	sed -i 's/@10000000/@00000000/g' $@                     
 
 %.bin: %.elf
 	${GCC_PATH}/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
@@ -37,3 +38,4 @@
 	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
 
 .PHONY: clean hex all
+
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
index fd9d95e..4413573 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
@@ -55,37 +55,37 @@
     reg_mprj_xfer = 1;
     while (reg_mprj_xfer == 1);
 
-    reg_mprj_data = 0;
+    reg_mprj_datal = 0;
 
     // start test
-    reg_mprj_data = 0xA040;
+    reg_mprj_datal = 0xA040;
 
     // Write to IO Control
     reg_mprj_io_0 = 0x004F;
     if (reg_mprj_io_0 != 0x004F)
-	reg_mprj_data = 0xAB400000;
+	reg_mprj_datal = 0xAB400000;
      else
-	reg_mprj_data = 0xAB410000;
+	reg_mprj_datal = 0xAB410000;
 
     // Write to IO Control 
     reg_mprj_io_1 = 0x005F;
     if (reg_mprj_io_1 != 0x005F)
-	reg_mprj_data = 0xAB500000;
+	reg_mprj_datal = 0xAB500000;
     else
-	reg_mprj_data = 0xAB510000;
+	reg_mprj_datal = 0xAB510000;
 
     // Write to IO Control
     reg_mprj_io_2 = 0x006F;
     if (reg_mprj_io_2 != 0x006F)
-	reg_mprj_data = 0xAB600000;
+	reg_mprj_datal = 0xAB600000;
     else
-	reg_mprj_data = 0xAB610000;
+	reg_mprj_datal = 0xAB610000;
 
     // Write to IO Control
     reg_mprj_io_3 = 0xF0F5;
     if (reg_mprj_io_3 != 0xF0F5)
-	reg_mprj_data = 0xAB700000;
+	reg_mprj_datal = 0xAB700000;
     else
-	reg_mprj_data = 0xAB710000;
+	reg_mprj_datal = 0xAB710000;
 }
 
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index 2557229..ef30bcd 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -13,7 +13,7 @@
 	wire flash_clk;
 	wire flash_io0;
 	wire flash_io1;
-	wire [31:0] user_io;
+	wire [36:0] user_io;
 	wire SDO;
 
 	wire [15:0] checkbits;
@@ -67,14 +67,10 @@
 	end
 
 	initial begin
-		CSB <= 1'b1;
-		SCK <= 1'b0;
-		SDI <= 1'b0;
 		RSTB <= 1'b0;
 		#1000;
 		RSTB <= 1'b1;	    // Release reset
 		#2000;
-		CSB <= 1'b0;	    // Apply CSB to start transmission
 	end
 
 	always @(gpio) begin
@@ -90,9 +86,20 @@
 	assign VDD3V3 = 1'b1;
 
 	caravel uut (
-		.vdd3v3	   (VDD3V3),
-		.vdd1v8	   (VDD1V8),
-		.vss	   (VSS),
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
 		.clock	   (clock),
 		.gpio      (gpio),
 		.mprj_io   (user_io),
diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf.c b/verilog/dv/caravel/mgmt_soc/perf/perf.c
index b0edcb9..0d83518 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/perf.c
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf.c
@@ -39,15 +39,15 @@
     reg_mprj_xfer = 1;
     while (reg_mprj_xfer == 1);
 
-    reg_mprj_data = 0;
+    reg_mprj_datal = 0;
 
     // start test
-    reg_mprj_data = 0xA0000000;
+    reg_mprj_datal = 0xA0000000;
 	
     for (i=0; i<100; i++)
         sum += (sum + i);
     
-    reg_mprj_data = 0xAB000000;
+    reg_mprj_datal = 0xAB000000;
     
     return sum;
 }
diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
index 985ca3f..3323480 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
@@ -29,12 +29,14 @@
 
 	wire gpio;
 	wire [15:0] checkbits;
-	wire [15:0] noconnect;
+	wire [36:0] mprj_io;
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;
 	wire flash_io1;
 
+	assign checkbits = mprj_io[31:16];
+
 	// External clock is used by default.  Make this artificially fast for the
 	// simulation.  Normally this would be a slow clock and the digital PLL
 	// would be the fast clock.
@@ -93,12 +95,23 @@
 	assign VDD3V3 = 1'b1;
 
 	caravel uut (
-		.vdd3v3	  (VDD3V3  ),
-		.vdd1v8	  (VDD1V8),
-		.vss	  (VSS),
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
 		.clock	  (clock),
 		.gpio     (gpio),
-		.mprj_io  ({checkbits, noconnect}),
+		.mprj_io  (mprj_io),
 		.flash_csb(flash_csb),
 		.flash_clk(flash_clk),
 		.flash_io0(flash_io0),
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c
index 023a08c..70b5b4a 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c
@@ -2,42 +2,46 @@
 
 // --------------------------------------------------------
 
+// NOTE:  Testbench to be completed.  Needs to use the new
+// architecture in which the SPI master is enabled and used
+// to access the housekeeping SPI directly as an SPI slave
+
 /*
-	System Control Test
-        - Reads default value of SPI-Controlled registers
-        - Flags failure/success using gpio
-*/
+ *	System Control Test
+ *      - Reads default value of SPI-Controlled registers
+ *      - Flags failure/success using gpio
+ */
 void main()
 {
 	int i;
 
-    reg_gpio_data = 0;
+    reg_gpio_datal = 0;
 	reg_gpio_ena =  0x0000;
 
 	// start test
-	reg_gpio_data = 0xA040;
+	reg_gpio_datal = 0xA040;
 
     // Read Product ID value
-    if(0x05 != reg_spi_prod_id) reg_gpio_data = 0xAB40;
-	reg_gpio_data = 0xAB41;
+    if(0x05 != reg_spi_prod_id) reg_gpio_datal = 0xAB40;
+	reg_gpio_datal = 0xAB41;
 
     // Read Manufacturer ID value
-    if(0x456 != reg_spi_mfgr_id) reg_gpio_data = 0xAB50;
-	reg_gpio_data = 0xAB51;
+    if(0x456 != reg_spi_mfgr_id) reg_gpio_datal = 0xAB50;
+	reg_gpio_datal = 0xAB51;
 
     // Read Mask revision 
-    if(0x1 != reg_spi_mask_rev) reg_gpio_data = 0xAB60;
-	reg_gpio_data = 0xAB61;
+    if(0x1 != reg_spi_mask_rev) reg_gpio_datal = 0xAB60;
+	reg_gpio_datal = 0xAB61;
 
     // Read PLL-Bypass
-    if(0x1 != reg_spi_pll_bypass) reg_gpio_data = 0xAB70;
-	reg_gpio_data = 0xAB71;
+    if(0x1 != reg_spi_pll_bypass) reg_gpio_datal = 0xAB70;
+	reg_gpio_datal = 0xAB71;
 
-    if(0x7FFDFFF != reg_spi_pll_config) reg_gpio_data = 0xAB80;
-	reg_gpio_data = 0xAB81;
+    if(0x7FFDFFF != reg_spi_pll_config) reg_gpio_datal = 0xAB80;
+	reg_gpio_datal = 0xAB81;
 
     // Read spi enables
-    if(0x83 != reg_spi_enables) reg_gpio_data = 0xAB90;
-	reg_gpio_data = 0xAB91;
+    if(0x83 != reg_spi_enables) reg_gpio_datal = 0xAB90;
+	reg_gpio_datal = 0xAB91;
 }
 
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
index 708bc9e..c1a1e2a 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -6,18 +6,19 @@
 
 module sysctrl_tb;
 	reg clock;
+	reg RSTB;
 
-	reg SDI, CSB, SCK, RSTB;
-
-	wire [1:0] gpio;
+	wire gpio;
+	wire [15:0] checkbits;
+	wire [36:0] mprj_io;
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;
 	wire flash_io1;
-	wire flash_io2;
-	wire flash_io3;
 	wire SDO;
 
+	assign checkbits = mprj_io[31:16];
+
 	// External clock is used by default.  Make this artificially fast for the
 	// simulation.  Normally this would be a slow clock and the digital PLL
 	// would be the fast clock.
@@ -32,7 +33,7 @@
 		$dumpfile("sysctrl_tb.vcd");
 		$dumpvars(0, sysctrl_tb);
 		repeat (25) begin
-			repeat (1000) @(posedge XCLK);
+			repeat (1000) @(posedge clock);
 			$display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
@@ -41,57 +42,57 @@
 		$finish;
 	end
 
-	always @(gpio) begin
-		if(gpio == 16'hA040) begin
+	always @(checkbits) begin
+		if(checkbits == 16'hA040) begin
 			$display("System control Test started");
 		end
-		else if(gpio == 16'hAB40) begin
+		else if(checkbits == 16'hAB40) begin
 			$display("%c[1;31m",27);
 			$display("Monitor: System control (RTL) Test failed");
 			$display("%c[0m",27);
 			$finish;
 		end
-		else if(gpio == 16'hAB41) begin
+		else if(checkbits == 16'hAB41) begin
 			$display("Monitor: System control product ID read passed");
 		end
-        else if(gpio == 16'hAB50) begin
+        else if(checkbits == 16'hAB50) begin
             $display("%c[1;31m",27);
 			$display("Monitor: System control manufacture ID read failed");
 			$display("%c[0m",27);
 			$finish;
-        end else if(gpio == 16'hAB51) begin
+        end else if(checkbits == 16'hAB51) begin
 			$display("Monitor: System control manufacture ID read passed");
         end
-        else if(gpio == 16'hAB60) begin
+        else if(checkbits == 16'hAB60) begin
             $display("%c[1;31m",27);
 			$display("Monitor: System control mask rev read failed");
 			$display("%c[0m",27);
 			$finish;
-        end else if(gpio == 16'hAB61) begin
+        end else if(checkbits == 16'hAB61) begin
 			$display("Monitor: System control mask rev read passed");
         end
-        else if(gpio == 16'hAB70) begin
+        else if(checkbits == 16'hAB70) begin
             $display("%c[1;31m",27);
 			$display("Monitor: System control pll-bypass read failed");
 			$display("%c[0m",27);
 			$finish;
-        end else if(gpio == 16'hAB71) begin
+        end else if(checkbits == 16'hAB71) begin
 			$display("Monitor: System control pll-bypass read passed");
         end
-        else if(gpio == 16'hAB80) begin
+        else if(checkbits == 16'hAB80) begin
             $display("%c[1;31m",27);
 			$display("Monitor: System control pll-config read failed");
 			$display("%c[0m",27);
 			$finish;
-        end else if(gpio == 16'hAB81) begin
+        end else if(checkbits == 16'hAB81) begin
 			$display("Monitor: System control pll-config read passed");
         end
-        else if(gpio == 16'hAB90) begin
+        else if(checkbits == 16'hAB90) begin
             $display("%c[1;31m",27);
 			$display("Monitor: System control spi-enables read failed");
 			$display("%c[0m",27);
 			$finish;
-        end else if(gpio == 16'hAB91) begin
+        end else if(checkbits == 16'hAB91) begin
 			$display("Monitor: System control spi-enables read passed");
 			$display("Monitor: Sysctrl (RTL) test passed.");
             $finish;
@@ -109,8 +110,8 @@
 		CSB <= 1'b0;	    // Apply CSB to start transmission
 	end
 
-	always @(gpio) begin
-		#1 $display("GPIO state = %b ", gpio);
+	always @(checkbits) begin
+		#1 $display("GPIO state = %b ", checkbits);
 	end
 
 	wire VDD3V3;
@@ -122,25 +123,28 @@
 	assign VDD3V3 = 1'b1;
 
 	caravel uut (
-		.vdd3v3	  (VDD3V3),
-		.vdd1v8	  (VDD1V8),
-		.vss	  (VSS),
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
 		.clock    (clock),
-		.SDI	  (SDI),
-		.SDO	  (SDO),
-		.CSB	  (CSB),
-		.SCK	  (SCK),
-		.ser_rx	  (1'b0),
-		.ser_tx	  (),
-		.irq	  (1'b0),
 		.gpio     (gpio),
+		.mprj_io  (mprj_io),
 		.flash_csb(flash_csb),
 		.flash_clk(flash_clk),
 		.flash_io0(flash_io0),
 		.flash_io1(flash_io1),
-		.flash_io2(flash_io2),
-		.flash_io3(flash_io3),
-		.RSTB	  (RSTB)
+		.resetb	  (RSTB)
 	);
 
 	spiflash #(
@@ -150,8 +154,8 @@
 		.clk(flash_clk),
 		.io0(flash_io0),
 		.io1(flash_io1),
-		.io2(flash_io2),
-		.io3(flash_io3)
+		.io2(),			// not used
+		.io3()			// not used
 	);
 
 endmodule
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart.c b/verilog/dv/caravel/mgmt_soc/uart/uart.c
index a0b5cc3..d89741f 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart.c
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart.c
@@ -41,12 +41,12 @@
     reg_uart_enable = 1;
 
     // Start test
-    reg_mprj_data = 0xa0000000;
+    reg_mprj_datal = 0xa0000000;
 
     // This should appear at the output, received by the testbench UART.
     print("\n");
     // print("Monitor: Test UART (RTL) passed\n\n");
     print("X\n\n");
 
-    reg_mprj_data = 0xab000000;
+    reg_mprj_datal = 0xab000000;
 }
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
index a52693b..aa1a91b 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -33,7 +33,7 @@
 	wire flash_clk;
 	wire flash_io0;
 	wire flash_io1;
-	wire [31:0] mprj_io;
+	wire [36:0] mprj_io;
 	wire [15:0] checkbits;
 	wire uart_tx;
 	wire SDO;
@@ -86,9 +86,20 @@
 	assign VDD3V3 = 1'b1;
 
 	caravel uut (
-		.vdd3v3	  (VDD3V3),
-		.vdd1v8	  (VDD1V8),
-		.vss	  (VSS),
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
 		.clock	  (clock),
 		.gpio     (gpio),
 		.mprj_io  (mprj_io),
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index 39fc3d6..a83b64f 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -10,7 +10,7 @@
 	wire SDO;
 
     	wire gpio;
-    	wire [31:0] mprj_io;
+    	wire [36:0] mprj_io;
 	wire [7:0] mprj_io_0;
 
 	assign mprj_io_0 = mprj_io[7:0];
@@ -84,9 +84,20 @@
 	assign VDD3V3 = 1'b1;
 
 	caravel uut (
-		.vdd3v3	  (VDD3V3),
-		.vdd1v8	  (VDD1V8),
-		.vss	  (VSS),
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
 		.clock	  (clock),
 		.gpio     (gpio),
         	.mprj_io  (mprj_io),
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c b/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c
index 708a761..d3b08d7 100644
--- a/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c
+++ b/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c
@@ -74,7 +74,7 @@
 	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
 
 	// Flag start of the test 
-	reg_mprj_data = 0xAB400000;
+	reg_mprj_datal = 0xAB400000;
 
 	// Set Counter value to zero through LA probes [63:32]
 	reg_la1_data = 0x00000000;
@@ -84,12 +84,12 @@
 
 	while (1) {
 		if (reg_la0_data > 0x1F4) {
-			reg_mprj_data = 0xAB410000;
+			reg_mprj_datal = 0xAB410000;
 			break;
 		}
 	}
 	print("\n");
 	print("Monitor: Test 2 Passed\n\n");
-	reg_mprj_data = 0xAB510000;
+	reg_mprj_datal = 0xAB510000;
 }
 
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
index 722efe6..df9bfaf 100644
--- a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
@@ -12,7 +12,7 @@
 
     	wire gpio;
 	wire uart_tx;
-    	wire [31:0] mprj_io;
+    	wire [36:0] mprj_io;
 	wire [15:0] checkbits;
 
 	assign checkbits  = mprj_io[31:16];
@@ -69,9 +69,20 @@
 	assign VDD3V3 = 1'b1;
 
 	caravel uut (
-		.vdd3v3	  (VDD3V3),
-		.vdd1v8	  (VDD1V8),
-		.vss	  (VSS),
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
 		.clock	  (clock),
 		.gpio     (gpio),
         	.mprj_io  (mprj_io),
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/la_test2.c b/verilog/dv/caravel/user_proj_example/la_test2/la_test2.c
index 54dabb6..18e185b 100644
--- a/verilog/dv/caravel/user_proj_example/la_test2/la_test2.c
+++ b/verilog/dv/caravel/user_proj_example/la_test2/la_test2.c
@@ -60,7 +60,7 @@
 	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
 
 	// Flag start of the test
-	reg_mprj_data = 0xAB600000;
+	reg_mprj_datal = 0xAB600000;
 
 	// Configure LA[64] LA[65] as outputs from the cpu
 	reg_la2_ena  = 0xFFFFFFFC; 
@@ -75,7 +75,7 @@
 	}
 
 	if (reg_la0_data == 0x05) {
-		reg_mprj_data = 0xAB610000;
+		reg_mprj_datal = 0xAB610000;
 	}
 
 }
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
index 99c9cca..7494ddc 100644
--- a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
@@ -10,7 +10,7 @@
 	wire SDO;
 
     	wire gpio;
-    	wire [31:0] mprj_io;
+    	wire [36:0] mprj_io;
 	wire [15:0] checkbits;
 
 	assign checkbits = mprj_io[15:8];
@@ -65,9 +65,20 @@
 	assign VDD3V3 = 1'b1;
 
 	caravel uut (
-		.vdd3v3	  (VDD3V3),
-		.vdd1v8	  (VDD1V8),
-		.vss	  (VSS),
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
 		.clock	  (clock),
 		.gpio     (gpio),
         	.mprj_io  (mprj_io),