# Spectravel - Spectrometer on Caravel  

Block diagram of the Spectravel is given below and detailed explanation of the each block is given inside submodules `spectrometer` and `wb2axip`.

![Global block scheme of the Spectravel](./doc/SpectrometerTest.svg)

This directory contains following submodules and directories:

* Submodule `spectrometer` -  contains digital spectrometer generator with built in test structures designed in [Chisel](http://www.chisel-lang.org) HDL
* Submodule  `wb2axip` - contains wishbone to AXI4 bridge. Current submodule is forked version of the [ZipCPU/wb2axip](https://github.com/ZipCPU/wb2axip)
* `doc` - contains global block scheme of the `Spectravel` block in svg and png format.
* `top/dv/SpectrometerTest` - contains verilog testbenches for Spectravel integrated with Caravel
* `top/rtl/SpectrometerTest` - contains `user_proj_example.v` which is the top level verilog file for Spectravel
* Makefile - have targets for verilog and test generation 

## Verilog generation and Chisel tests

Before running make commands, we could set the size of FFT inside spectrometer. Default size is 128. For example, we could set the size of the FFT inside spectrometer to be equal to 256 with the command:
```sh
$ export SIZE=256
```
To run verilog generation and Chisel tests, sbt and verilator must be installed. For installation details see this [link](https://chipyard.readthedocs.io/en/latest/Chipyard-Basics/Initial-Repo-Setup.html#requirements).

In order to generate verilog file SpectrometerTest.v which contains verilog code for digital spectrometer, run command:
```sh
$ make verilog_spectrometer
```
To run chisel tests for digital spectrometer, run command:
```sh
$ make test_spectrometer
```

## Verilog tests

In order to run verilog tests for Spectravel connected to Caravel, PDK_ROOT and RISCV32 paths must be set. RISCV32 is path to RV32I Toolchain. For RV32I toolchain installation click [here](https://github.com/cliffordwolf/picorv32#building-a-pure-rv32i-toolchain). To check if paths are set, run command:
```sh
$ make check-env
```
Currently there are four different tests for Spectravel connected to Caravel:
* plfg_nco_fft_mag_acc_utx - Data path is: PLFG -> NCO -> FFT -> MAG -> ACC -> uTx (UART output) 
* plfg_nco_fft_mag_acc_pout - Data path is: PLFG -> NCO -> FFT -> MAG -> ACC -> outStream (8b AXI4-Stream)
* pin_nco_fft_mag_acc_pout - Data path is: inStream (8b AXI4-Stream) -> NCO -> FFT -> MAG -> ACC -> outStream (8b AXI4-Stream)
* pin_fft_mag_acc_pout - Data path is: inStream (8b AXI4-Stream) -> FFT -> MAG -> ACC -> outStream (8b AXI4-Stream)

All tests contain C code where appropriate Spectravel registers are set in order to obtain desired functionality. Output of the Spectravel is compared with golden model generated with Chisel. In order for test to pass, Spectravel output data must be the same as golden model data.

By default, caravel_spectrometer repository contains all data needed to run verilog tests. Thus, verilog tests can be run without installing sbt.

In order to test Spectravel added to the Caravel, run command:
```sh
$ make test_top
```
To clean data generated by verilog testbenches, run:
```sh
$ make clean_top
```

In order to regenerate verilog code, run chisel tests and run Spectravel tests, run command:
```sh
$ make run_all
```

## Address space for Spectravel
```
User address space 0x3000_0000
    ├── in_split:   0x3000_0000
    ├── plfg_ram:   0x3000_1000
    ├── plfg:       0x3000_2100
    ├── plfg_split: 0x3000_2200
    ├── plfg_mux_0: 0x3000_2210
    ├── plfg_mux_1: 0x3000_2220
    ├── nco:        0x3000_3000
    ├── nco_split:  0x3000_3100
    ├── nco_mux_0:  0x3000_3110
    ├── nco_mux_1:  0x3000_3120
    ├── fft:        0x3000_4000
    ├── fft_split:  0x3000_4100
    ├── fft_mux_0   0x3000_4110
    ├── fft_mux_1:  0x3000_4120
    ├── mag:        0x3000_5000
    ├── mag_split:  0x3000_5100
    ├── mag_mux_0:  0x3000_5110
    ├── mag_mux_1:  0x3000_5120
    ├── acc_queue:  0x3000_6000
    ├── acc:        0x3000_7000
    ├── out_mux:    0x3000_8000
    ├── out_split:  0x3000_8010
    ├── uart:       0x3000_9000
    └── uart_split: 0x3000_9100
```