)]}'
{
  "commit": "cfe765325711bbb060668c2ed9950436416c9098",
  "tree": "ad66010576200d113deddbabefd01605cb8bee44",
  "parents": [
    "7a3f4789a8a6207f4d5bf2f9d457c5f7c5c2dbf7"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Tue Oct 27 21:31:58 2020 -0400"
  },
  "committer": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Wed Oct 28 22:58:29 2020 +0200"
  },
  "message": "Corrected the timer testbenches for minor count differences due to\nthe slightly different timing of the I/O configuration loading.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "9d04404766c8f401bf2683cb66fbf9611d0f5f7a",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer/timer_tb.v",
      "new_id": "02fef690b643eabec4c3a01d847b346c49869044",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer/timer_tb.v"
    },
    {
      "type": "modify",
      "old_id": "b6db4b8fca0550ccdee30e1dc03c3da0be0d6093",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v",
      "new_id": "7de54631b617f82585da37346570585df203f64f",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v"
    }
  ]
}