)]}'
{
  "commit": "b6dd152556ce2581f06758efc45c9b387bc4c4ab",
  "tree": "77f58827c6d18bbb87dff16e4cffc8ad415fa1c1",
  "parents": [
    "268a90bd2da91eba601fe9f9e6de573bbe272951"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Oct 19 15:58:25 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Oct 19 15:58:25 2020 -0400"
  },
  "message": "Updated testbenches to declare 38 bits for the user project GPIO pins.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a62d3148079725e654b4b1d1bef83b3f2f5b3777",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/defs.h",
      "new_id": "96630f1993a19c56a331dc81a9d1099c5ddda3d2",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/defs.h"
    },
    {
      "type": "modify",
      "old_id": "5a0c95db6db233e53d05cc84b16706e305f1cdb3",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/gpio/Makefile",
      "new_id": "49bbb0ccb7eab18ff6c6180d9e809bfd64d22ca8",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/Makefile"
    },
    {
      "type": "modify",
      "old_id": "7932cbdeba3f074e7cbb7a4734c024112bc9a11c",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v",
      "new_id": "349cac96a70cbfdacd238763d8b7fb8927950601",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v"
    },
    {
      "type": "modify",
      "old_id": "91e36f1897d32f10eb208e0561e189925786d3ff",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/hkspi/Makefile",
      "new_id": "4a8b06675f61df2ecb5aa1373833e008277dd6d7",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/hkspi/Makefile"
    },
    {
      "type": "modify",
      "old_id": "dd1aca232d86c313b5f300a8c6739fc00f9672f1",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v",
      "new_id": "5d7fd1120f1edb66ccfd51747107e7e5f3ea0f87",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v"
    },
    {
      "type": "modify",
      "old_id": "1b791ce738a1dc85bcb1e03ee67a648a99067d19",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/mem/Makefile",
      "new_id": "49a3f73e9dc1e4dc8272e234fa2ee2fade7edf14",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/mem/Makefile"
    },
    {
      "type": "modify",
      "old_id": "8565a6b3583f0d75d9b35670bad9e5f20083f9be",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile",
      "new_id": "b6c988915f909e2ce01e8dee0c479e7d96574e9c",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile"
    },
    {
      "type": "modify",
      "old_id": "2d91c927c3301c0e05712196cc5703aec58eb672",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/pass_thru/Makefile",
      "new_id": "a902f21a1dc71bb869737c5f94860ef0590d8cb7",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/pass_thru/Makefile"
    },
    {
      "type": "modify",
      "old_id": "e741a29462d34839d63ee0efd7c4972a2dc62ebb",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v",
      "new_id": "ef215a255e7ceaaedc80867b27f4c91d48bba1aa",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v"
    },
    {
      "type": "modify",
      "old_id": "e885eb49b5b12b246e70d2383cb079ac071f33bc",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/perf/Makefile",
      "new_id": "4c24533948657c57dd505f9771c81a89f7154c8a",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/perf/Makefile"
    },
    {
      "type": "modify",
      "old_id": "c5721f9cedfd68a49236217d92f721b61474c76f",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/perf/perf_tb.v",
      "new_id": "ca86f6d93ee25625e8e56b8b4168ceb9ef3640a9",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/perf/perf_tb.v"
    },
    {
      "type": "modify",
      "old_id": "31bac9e2bb0be01e42ca16a17b8a9534f964199b",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/pll/Makefile",
      "new_id": "4a5dfc8d1c8d28b2992faeaaab047b298349781b",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/pll/Makefile"
    },
    {
      "type": "modify",
      "old_id": "613364ba4232f4443fe5dd1912b3c43c865842f9",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/pll/pll_tb.v",
      "new_id": "d9448e96e999083a82093543d1907d75055c068d",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/pll/pll_tb.v"
    },
    {
      "type": "modify",
      "old_id": "d07464b3f1c562d9ba6016ec6bfc683376a91305",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/sysctrl/Makefile",
      "new_id": "dd839515fcc78c82e222145bf138e0d3ea55af80",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/sysctrl/Makefile"
    },
    {
      "type": "modify",
      "old_id": "6fb2f6970eae8e32cfc0dcd2b6769e69d38520ea",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v",
      "new_id": "b22309e3fb095d4726fd994aac1bbf2daccc1c63",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v"
    },
    {
      "type": "modify",
      "old_id": "0f0bdb9d90bbc5427dc6d17967fbc6f57e37c6a9",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer/Makefile",
      "new_id": "4a67c440ec562d45663e33607aa7147412f5d150",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer/Makefile"
    },
    {
      "type": "modify",
      "old_id": "131de72bff91bded60cb6866a85c1fd4658f4623",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer/timer.c",
      "new_id": "4b49f4fcfa28b83889274cb1bc36e3a3284c06a3",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer/timer.c"
    },
    {
      "type": "modify",
      "old_id": "c41fb6d94d8fa64b066aac62103d4bca20910030",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer/timer_tb.v",
      "new_id": "5218ee3242b893ff9da76a14fe0c4ab054df45ec",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer/timer_tb.v"
    },
    {
      "type": "modify",
      "old_id": "9fdcf04ccb736f36a16e9cb42c9ed2bdfa29bd4f",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer2/Makefile",
      "new_id": "4255a9b9a06baa4b801e7369a6eac1ddc020b141",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer2/Makefile"
    },
    {
      "type": "modify",
      "old_id": "12c480f3196152481a4043fdd201108dc66f3447",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer2/timer2.c",
      "new_id": "2994082aaf1e8a9999458e6c415fea42414d6ca4",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer2/timer2.c"
    },
    {
      "type": "modify",
      "old_id": "cd0409775751cc45379d80f906113499a8374aaf",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v",
      "new_id": "39e06cc8b6762e1890e9f25b25247e1b23d3f0a1",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v"
    },
    {
      "type": "modify",
      "old_id": "e6fd2843ca0ba0df4f8f0b8145a384ad3d9efe0a",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/uart/Makefile",
      "new_id": "cde1104c4930381cbeecd3fd79cf5ec270d4d080",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/uart/Makefile"
    },
    {
      "type": "modify",
      "old_id": "69071555612815f2d36245c9b74c279cf80c461a",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/uart/uart_tb.v",
      "new_id": "7d4237ab64dceef047ac4a04a08b2403c4365924",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/uart/uart_tb.v"
    },
    {
      "type": "modify",
      "old_id": "2d5a749b9a4e479e02bb88535a293307aa019720",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/io_ports/Makefile",
      "new_id": "0f0482bc711dcac1400960c9d870372e762d06e4",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/user_proj_example/io_ports/Makefile"
    },
    {
      "type": "modify",
      "old_id": "741a982ba865a341d2e0caf478018b752bfbd630",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v",
      "new_id": "0205af3283f7792adcc379f6d3704eff9fb4cafc",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v"
    },
    {
      "type": "modify",
      "old_id": "b026dbc69007a680bfb7df05a4ec0f6401fb6c7c",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/la_test1/Makefile",
      "new_id": "a258d8c232c57b2ed4d321a08ffd7e15968d6928",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/user_proj_example/la_test1/Makefile"
    },
    {
      "type": "modify",
      "old_id": "9bee0a676682cf0bcc4b96cf0a777fe21cc88600",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v",
      "new_id": "b378e1af3d554169aafe120cc39226092df77056",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v"
    },
    {
      "type": "modify",
      "old_id": "397a862745d07a00d1211d1511ed915bd8d068aa",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/la_test2/Makefile",
      "new_id": "1b3823c861e3b7d53fa1a864a3ae24ffe499dfaf",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/user_proj_example/la_test2/Makefile"
    },
    {
      "type": "modify",
      "old_id": "54b671f6132f514a7c0b7da33260f22b1eb649fc",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v",
      "new_id": "96833b84227dfab72375c01f800d5f694136f4c7",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v"
    },
    {
      "type": "modify",
      "old_id": "2ec5f9601ab37a1cb65bbb4b5bc63092970960e6",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v",
      "new_id": "b4fc6a5234803cd97e35f081c53771755dd210d1",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v"
    },
    {
      "type": "modify",
      "old_id": "b10928c94ea9a277fe9b8a08c3634a0202ab6f8a",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "e5af073976cff38b3eeda096cc75572873c55344",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "1edc2dcc010632531890bf0451548c7c2c6267b0",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_proj_example.v",
      "new_id": "d010e77f6ce9398a452c9cfa1fddba363cbcf857",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_proj_example.v"
    },
    {
      "type": "modify",
      "old_id": "841ef643a21b3059409071d7894bd0dddd48c887",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "b37d2e596d72a28ec658ac3f1af22f2f91209487",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}