diff --git a/def/user_project_wrapper.def.xz b/def/user_project_wrapper.def.xz
index 268c4d2..2dbe560 100644
--- a/def/user_project_wrapper.def.xz
+++ b/def/user_project_wrapper.def.xz
Binary files differ
diff --git a/gds/caravel.gds.xz b/gds/caravel.gds.xz
index a76da0b..5559274 100644
--- a/gds/caravel.gds.xz
+++ b/gds/caravel.gds.xz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.xz b/gds/user_project_wrapper.gds.xz
index bf7d0fe..013b3b6 100644
--- a/gds/user_project_wrapper.gds.xz
+++ b/gds/user_project_wrapper.gds.xz
Binary files differ
diff --git a/mag/user_project_wrapper.mag.xz b/mag/user_project_wrapper.mag.xz
index b9ea62e..768d562 100644
--- a/mag/user_project_wrapper.mag.xz
+++ b/mag/user_project_wrapper.mag.xz
Binary files differ
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 03fa5bf..05b6762 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -127,18 +127,11 @@
 set ::env(FP_CORE_UTIL) 22
 set ::env(PL_TARGET_DENSITY) 0.25
 set ::env(PL_SKIP_INITIAL_PLACEMENT) 0
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
 set ::env(ROUTING_CORES) 8
 set ::env(GLB_RT_OVERFLOW_ITERS) 300
 set ::env(GLB_RT_ADJUSTMENT) 0.3
-# set ::env(GLB_RT_TILES) 14
-#set ::env(GLB_RT_ALLOW_CONGESTION) 1
-# set ::env(DIODE_INSERTION_STRATEGY) 3
-# set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 500
-# set ::env(LVS_INSERT_POWER_PINS) 1
-# set ::env(RUN_SPEF_EXTRACTION) 0
 set ::env(MAGIC_DISABLE_HIER_GDS) 1
 set ::env(MAGIC_GENERATE_LEF) 0
 set ::env(DIODE_INSERTION_STRATEGY) 1
 set ::env(MAGIC_WRITE_FULL_LEF) 0
-#set ::env(MAGIC_DRC_USE_GDS) 1
-#set::env(USE_ARC_ANTENNA_CHECK) 0
\ No newline at end of file
diff --git a/verilog/gl/user_project_wrapper.v.xz b/verilog/gl/user_project_wrapper.v.xz
index 25c5060..560a759 100644
--- a/verilog/gl/user_project_wrapper.v.xz
+++ b/verilog/gl/user_project_wrapper.v.xz
Binary files differ