)]}'
{
  "commit": "d0dcdcf506be35da5a1849dbdb09675868369b6c",
  "tree": "577c7eb5c382e88132b057fdfbd38bae6db84d1c",
  "parents": [
    "deaedccead8f57429ba0ecd0071b7cdcbf96360f"
  ],
  "author": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Tue Dec 15 22:00:25 2020 +0200"
  },
  "committer": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Tue Dec 15 22:00:25 2020 +0200"
  },
  "message": "Add a conb cell in gpio_control_block\n\n- this is to be able to enable/disable output without needed extra cells\n  on an upper level\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d58aa9b0ac93da4333e3ea61b36cae4b63fac86f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "fa85ee27d3f8fa54ac26adafec228bba3e17ddb2",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "6faaeffe26bce967a056dc87d996939f1f6cb687",
      "old_mode": 33188,
      "old_path": "verilog/rtl/gpio_control_block.v",
      "new_id": "f011e38511c4f2efa9047ef3ce848f03f45683b0",
      "new_mode": 33188,
      "new_path": "verilog/rtl/gpio_control_block.v"
    }
  ]
}