)]}'
{
  "commit": "69663c76d6f4b937374642818956e4b6ca8dabed",
  "tree": "ad964d3c5de136b7eb0ff01a8fbd9c63a6ff8996",
  "parents": [
    "630d1237e3672507661f31d2e20733f87c8d4cd7"
  ],
  "author": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Wed Nov 18 20:15:53 2020 +0200"
  },
  "committer": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Wed Nov 18 20:15:53 2020 +0200"
  },
  "message": "Eliminate the two inverters at the top level\n\n- Also fix some missing sizes (\u0027_1\u0027) in cell names\n- Also add USE_POWER_PINS guards in the modified files\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "784fdae52339c53ec4b14667ce5d2741dce2500d",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "42ecf451d4a30d3b26258254294bd7a229a996e3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "f8fe7fb3c8f33c77592def3d4168999b6f60fd2b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_protect.v",
      "new_id": "c5c79f365b0fd5e60e71463e56113969db1b53c2",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_protect.v"
    },
    {
      "type": "modify",
      "old_id": "2c51e9a06587ecd9b050de13035b26f4b6d6d6dd",
      "old_mode": 33188,
      "old_path": "verilog/rtl/simple_por.v",
      "new_id": "f6bda390be63bec807eef24a9656b9c4dde261fe",
      "new_mode": 33188,
      "new_path": "verilog/rtl/simple_por.v"
    }
  ]
}