diff --git a/gds/caravel_00010005.gds.gz b/gds/caravel_00010005.gds.gz
deleted file mode 100644
index a85211b..0000000
--- a/gds/caravel_00010005.gds.gz
+++ /dev/null
Binary files differ
diff --git a/signoff/caravel_fix b/signoff/caravel_fix
new file mode 100644
index 0000000..52d6410
--- /dev/null
+++ b/signoff/caravel_fix
@@ -0,0 +1 @@
+2d4e030f63d1966d19ad31f92b8058ab9874cf1d  ./gds/caravel_00010005_b.gds
diff --git a/signoff/run_metal_fix.out b/signoff/run_metal_fix.out
new file mode 100644
index 0000000..96a6630
--- /dev/null
+++ b/signoff/run_metal_fix.out
@@ -0,0 +1,65 @@
+Finding the prefix used for caravel subcells in the user GDS.
+User prefix is rS_
+Replacing cell caravel in the user GDS file.
+Reading GDS file for alternate cell caravel
+Cell caravel found at position 235669746
+Cell caravel ends at position 247680056
+Reading GDS file for original source ./gds/caravel_00010005.gds
+Cell caravel found at position 3202843706
+Cell caravel ends at position 3214853558
+Cell caravel checksum is 12009824
+Info:  Structure caravel matches checksum 12009824
+Info:  Structure caravel at 3202843706 to 3214853558 will be replaced by alternate data.
+Prefixing caravel subcells in the user GDS
+Running:  /usr/share/pdk/bin/change_gds_string.py user_id_textblock rS_user_id_textblock copyright_block rS_copyright_block open_source rS_open_source storage rS_storage sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped rS_sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped user_id_programming rS_user_id_programming simple_por rS_simple_por gpio_control_block rS_gpio_control_block mgmt_core rS_mgmt_core mgmt_protect rS_mgmt_protect chip_io rS_chip_io user_project_wrapper rS_user_project_wrapper ./gds/caravel_00010005_b.gds -debug -verbatim
+Original data length = 3214854280
+Replaced b'open_source\x00' with b'rS_open_source'
+Replaced b'user_id_textblock\x00' with b'rS_user_id_textblock'
+Replaced b'copyright_block\x00' with b'rS_copyright_block'
+Replaced b'storage\x00' with b'rS_storage'
+Replaced b'sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped' with b'rS_sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\x00'
+Replaced b'user_id_programming\x00' with b'rS_user_id_programming'
+Replaced b'simple_por' with b'rS_simple_por\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'mgmt_core\x00' with b'rS_mgmt_core'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'mgmt_protect' with b'rS_mgmt_protect\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'gpio_control_block' with b'rS_gpio_control_block\x00'
+Replaced b'chip_io\x00' with b'rS_chip_io'
+Replaced b'user_project_wrapper' with b'rS_user_project_wrapper\x00'
+Finished.